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sistrip::SpyDigiConverter Class Reference

Converts scope mode like digis into virgin raw like digis by: -extracting the frame payload, -reordering to physical order and -merging the DetSets indexed by FedKey to DetSets indexed by DetId. More...

#include <SiStripSpyDigiConverter.h>

Public Types

typedef edm::DetSetVector< SiStripRawDigiDSVRawDigis
 

Public Member Functions

 SpyDigiConverter ()
 
 ~SpyDigiConverter ()
 

Static Public Member Functions

static std::unique_ptr< DSVRawDigisextractPayloadDigis (const DSVRawDigis *inputScopeDigis, std::vector< uint32_t > *pAPVAddresses, const bool discardDigisWithAPVAddrErr, const sistrip::SpyUtilities::FrameQuality &aQuality, const uint16_t expectedPos)
 Extract frames from the scope digis. More...
 
static std::unique_ptr< DSVRawDigismergeModuleChannels (const DSVRawDigis *inputPhysicalOrderChannelDigis, const SiStripFedCabling &cabling)
 
static std::unique_ptr< DSVRawDigisreorderDigis (const DSVRawDigis *inputPayloadDigis)
 

Private Types

typedef DSVRawDigis::detset DetSetRawDigis
 

Static Private Member Functions

static void processFED (const uint16_t aPreviousFedId, const bool discardDigisWithAPVAddrErr, std::vector< uint32_t > *pAPVAddresses, std::vector< DetSetRawDigis > &outputData, std::vector< uint16_t > &aAddrVec, std::vector< uint16_t > &aHeaderBitVec, std::vector< DSVRawDigis::const_iterator > &aFedScopeDigis)
 

Detailed Description

Converts scope mode like digis into virgin raw like digis by: -extracting the frame payload, -reordering to physical order and -merging the DetSets indexed by FedKey to DetSets indexed by DetId.

Definition at line 25 of file SiStripSpyDigiConverter.h.

Member Typedef Documentation

Definition at line 53 of file SiStripSpyDigiConverter.h.

Definition at line 28 of file SiStripSpyDigiConverter.h.

Constructor & Destructor Documentation

sistrip::SpyDigiConverter::SpyDigiConverter ( )
inline

Definition at line 31 of file SiStripSpyDigiConverter.h.

31 {}
sistrip::SpyDigiConverter::~SpyDigiConverter ( )
inline

Definition at line 32 of file SiStripSpyDigiConverter.h.

References extractPayloadDigis(), mergeModuleChannels(), and reorderDigis().

32 {}

Member Function Documentation

std::unique_ptr< SpyDigiConverter::DSVRawDigis > sistrip::SpyDigiConverter::extractPayloadDigis ( const DSVRawDigis inputScopeDigis,
std::vector< uint32_t > *  pAPVAddresses,
const bool  discardDigisWithAPVAddrErr,
const sistrip::SpyUtilities::FrameQuality aQuality,
const uint16_t  expectedPos 
)
static

Extract frames from the scope digis.

If pAPVAddress is set, the map is filled with a map from FedKey to APVAddress. minAllowedRange is the min allowed range of digis when determine the threshold.

Definition at line 24 of file SiStripSpyDigiConverter.cc.

References sistrip::SpyUtilities::Frame::apvAddress, edm::DetSetVector< T >::begin(), edm::DetSetVector< T >::end(), sistrip::SpyUtilities::extractFrameInfo(), sistrip::FED_ID_MAX, sistrip::FEDCH_PER_FED, l1t::stage2::layer2::fedId, sistrip::SpyUtilities::Frame::firstHeaderBit, sistrip::SpyUtilities::isValid(), sistrip::SpyUtilities::print(), processFED(), edm::DetSetVector< T >::size(), sistrip::SPY_SAMPLES_PER_CHANNEL, and AlCaHLTBitMon_QueryRunRegistry::string.

Referenced by sistrip::SpyDigiConverterModule::produce(), and ~SpyDigiConverter().

29  {
30  // Data is already sorted so push back fast into vector to avoid sorts and create DSV later
31  std::vector<DetSetRawDigis> outputData;
32  outputData.reserve(inputScopeDigis->size());
33 
34  //APV address vector indexed by fedid, majority value written.
35  pAPVAddresses->resize(sistrip::FED_ID_MAX+1,0);
36  std::vector<uint16_t> lAddrVec;
37  lAddrVec.reserve(2*sistrip::FEDCH_PER_FED);
38  uint16_t lPreviousFedId = 0;
39  std::vector<uint16_t> lHeaderBitVec;
40  lHeaderBitVec.reserve(sistrip::FEDCH_PER_FED);
41 
42 
43  //local DSVRawDigis per FED
44  std::vector<DSVRawDigis::const_iterator> lFedScopeDigis;
45  lFedScopeDigis.reserve(sistrip::FEDCH_PER_FED);
46 
47  // Loop over channels in input collection
48  DSVRawDigis::const_iterator inputChannel = inputScopeDigis->begin();
49  const DSVRawDigis::const_iterator endChannels = inputScopeDigis->end();
50  bool hasBeenProcessed = false;
51 
52  for (; inputChannel != endChannels; ++inputChannel) {
53 
54  // Fill frame parameters. Second parameter is to print debug info (if logDebug enabled....)
56 
57  const uint32_t lFedIndex = inputChannel->detId();
58  const uint16_t fedId = static_cast<uint16_t>(lFedIndex/sistrip::FEDCH_PER_FED);
59  const uint16_t fedCh = static_cast<uint16_t>(lFedIndex%sistrip::FEDCH_PER_FED);
60 
61  if (lPreviousFedId == 0) {
62  lPreviousFedId = fedId;
63  }
64 
65  //print out warning only for non-empty frames....
66  if (!sistrip::SpyUtilities::isValid(lFrame,aQuality,expectedPos)){
67  //print out only for non-empty frames, else too many prints...
69  edm::LogWarning("SiStripSpyDigiConverter") << " FED ID: " << fedId << ", channel: " << fedCh << std::endl
71  std::string(" -- Invalid Frame ")
72  );
73  }
74 
75  continue;
76  }
77 
78  //fill local vectors per FED
79  if (fedId == lPreviousFedId) {
80  if (hasBeenProcessed) hasBeenProcessed = false;
81  }
82  if (fedId != lPreviousFedId) {
83  SpyDigiConverter::processFED(lPreviousFedId,
84  discardDigisWithAPVAddrErr,
85  pAPVAddresses,
86  outputData,
87  lAddrVec,
88  lHeaderBitVec,
89  lFedScopeDigis
90  );
91  lPreviousFedId = fedId;
92  hasBeenProcessed = true;
93  }
94  lFedScopeDigis.push_back(inputChannel);
95  lAddrVec.push_back(lFrame.apvAddress.first);
96  lAddrVec.push_back(lFrame.apvAddress.second);
97  lHeaderBitVec.push_back(lFrame.firstHeaderBit);
98 
99 
100  } // end of loop over channels.
101 
102  //process the last one if not already done.
103  if (!hasBeenProcessed) {
104  SpyDigiConverter::processFED(lPreviousFedId,
105  discardDigisWithAPVAddrErr,
106  pAPVAddresses,
107  outputData,
108  lAddrVec,
109  lHeaderBitVec,
110  lFedScopeDigis
111  );
112  }
113 
114  //return DSV of output
115  return std::unique_ptr<DSVRawDigis>( new DSVRawDigis(outputData, true) );
116 
117  } // end of SpyDigiConverter::extractPayloadDigis method
static const bool isValid(const Frame &aFrame, const FrameQuality &aQuality, const uint16_t aExpectedPos)
static const uint16_t SPY_SAMPLES_PER_CHANNEL
std::pair< uint8_t, uint8_t > apvAddress
static const Frame extractFrameInfo(const edm::DetSetVector< SiStripRawDigi >::detset &channelDigis, bool aPrintDebug=false)
static void processFED(const uint16_t aPreviousFedId, const bool discardDigisWithAPVAddrErr, std::vector< uint32_t > *pAPVAddresses, std::vector< DetSetRawDigis > &outputData, std::vector< uint16_t > &aAddrVec, std::vector< uint16_t > &aHeaderBitVec, std::vector< DSVRawDigis::const_iterator > &aFedScopeDigis)
edm::DetSetVector< SiStripRawDigi > DSVRawDigis
static const uint16_t FEDCH_PER_FED
static const uint16_t FED_ID_MAX
static std::string print(const Frame &aFrame, std::string aErr)
collection_type::const_iterator const_iterator
Definition: DetSetVector.h:104
std::unique_ptr< SpyDigiConverter::DSVRawDigis > sistrip::SpyDigiConverter::mergeModuleChannels ( const DSVRawDigis inputPhysicalOrderChannelDigis,
const SiStripFedCabling cabling 
)
static

Definition at line 209 of file SiStripSpyDigiConverter.cc.

References sistrip::DetSetVectorFiller< T, dsvIsSparse >::addItem(), sistrip::DetSetVectorFiller< T, dsvIsSparse >::createDetSetVector(), edm::DetSetVector< T >::end(), sistrip::FED_ID_MAX, sistrip::FED_ID_MIN, sistrip::FEDCH_PER_FED, SiStripFedCabling::fedConnections(), SiStripFedCabling::fedIds(), SiStripFedKey::fedIndex(), edm::DetSetVector< T >::find(), sistrip::invalid32_, sistrip::DetSetVectorFiller< T, dsvIsSparse >::newChannel(), and sistrip::STRIPS_PER_FEDCH.

Referenced by sistrip::SpyDigiConverterModule::produce(), and ~SpyDigiConverter().

211  {
212  // Create filler for detSetVector to create output (with maximum number of DetSets and digis)
213  uint16_t nFeds = static_cast<uint16_t>( FED_ID_MAX - FED_ID_MIN + 1);
214 
216  // Loop over FEDs in cabling
217  auto iFed = cabling.fedIds().begin();
218  auto endFeds = cabling.fedIds().end();
219  for (; iFed != endFeds; ++iFed) {
220  // Loop over cabled channels
221  auto conns = cabling.fedConnections(*iFed);
222  auto iConn = conns.begin();
223  auto endConns = conns.end();
224  for (; iConn != endConns; ++iConn) {
225  // Skip channels not connected to a detector.
226  if (!iConn->isConnected()) continue;
227  if (iConn->detId() == sistrip::invalid32_) continue;
228 
229  // Find the data from the input collection
230  const uint32_t fedIndex = SiStripFedKey::fedIndex(iConn->fedId(),iConn->fedCh());
231  const DSVRawDigis::const_iterator iDetSet = inputPhysicalOrderChannelDigis->find(fedIndex);
232  if (iDetSet == inputPhysicalOrderChannelDigis->end()) {
233  // NOTE: It will display this warning if channel hasn't been unpacked...
234  // Will comment out for now.
235  //edm::LogWarning("SiStripSpyDigiConverter") << "No data found for FED ID: " << iConn->fedId() << " channel: " << iConn->fedCh();
236  continue;
237  }
238 
239  // Start a new channel indexed by the detId in the filler
240  dsvFiller.newChannel(iConn->detId(),iConn->apvPairNumber()*STRIPS_PER_FEDCH);
241 
242  // Add the data
243  DetSetRawDigis::const_iterator iDigi = iDetSet->begin();
244  const DetSetRawDigis::const_iterator endDetSetDigis = iDetSet->end();
245  for (; iDigi != endDetSetDigis; ++iDigi) {
246  dsvFiller.addItem(*iDigi);
247  } // end of loop over the digis.
248  } // end of loop over channels.
249  } // end of loop over FEDs
250 
251  return dsvFiller.createDetSetVector();
252  } // end of SpyDigiConverter::mergeModuleChannels method.
static const uint16_t FED_ID_MIN
static const uint32_t invalid32_
Definition: Constants.h:15
static uint32_t fedIndex(const uint16_t &fed_id, const uint16_t &fed_ch)
DetSetVectorFiller< SiStripRawDigi, false > RawDigiDetSetVectorFiller
FedsConstIterRange fedIds() const
static const uint16_t STRIPS_PER_FEDCH
ConnsConstIterRange fedConnections(uint16_t fed_id) const
static const uint16_t FEDCH_PER_FED
static const uint16_t FED_ID_MAX
collection_type::const_iterator const_iterator
Definition: DetSet.h:33
collection_type::const_iterator const_iterator
Definition: DetSetVector.h:104
void sistrip::SpyDigiConverter::processFED ( const uint16_t  aPreviousFedId,
const bool  discardDigisWithAPVAddrErr,
std::vector< uint32_t > *  pAPVAddresses,
std::vector< DetSetRawDigis > &  outputData,
std::vector< uint16_t > &  aAddrVec,
std::vector< uint16_t > &  aHeaderBitVec,
std::vector< DSVRawDigis::const_iterator > &  aFedScopeDigis 
)
staticprivate

Definition at line 120 of file SiStripSpyDigiConverter.cc.

References popcon2dropbox::copy(), sistrip::FEDCH_PER_FED, sistrip::SpyUtilities::findMajorityValue(), and sistrip::STRIPS_PER_FEDCH.

Referenced by extractPayloadDigis().

128  {
129 
130  //extract majority address
131  uint32_t lMaj = sistrip::SpyUtilities::findMajorityValue(aAddrVec,aPreviousFedId).first;
132  if (pAPVAddresses) (*pAPVAddresses)[aPreviousFedId] = lMaj;
133 
134  //loop over iterators and fill payload
135  std::vector<DSVRawDigis::const_iterator>::iterator lIter;
136  unsigned int lCh = 0;
137  for (lIter = aFedScopeDigis.begin(); lIter != aFedScopeDigis.end(); ++lIter,++lCh) {
138 
139  //discard if APV address different from majority.
140  //Keep if only one of them is wrong: the other APV might be alright ??
141 
142  if ( discardDigisWithAPVAddrErr &&
143  aAddrVec[2*lCh] != lMaj &&
144  aAddrVec[2*lCh+1] != lMaj ) {
145  continue;
146  }
147 
148  DetSetRawDigis::const_iterator iDigi = (*lIter)->begin();
149  const DetSetRawDigis::const_iterator endOfChannel = (*lIter)->end();
150 
151  if (iDigi == endOfChannel) {
152  continue;
153  }
154 
155  //header starts in sample firstHeaderBit and is 18+6 samples long
156  const DetSetRawDigis::const_iterator payloadBegin = iDigi+aHeaderBitVec[lCh]+24;
157  const DetSetRawDigis::const_iterator payloadEnd = payloadBegin + STRIPS_PER_FEDCH;
158 
159 
160  // Copy data into output collection
161  // Create new detSet with same key (in this case it is the fedKey, not detId)
162  outputData.push_back( DetSetRawDigis((*lIter)->detId()) );
163  std::vector<SiStripRawDigi>& outputDetSetData = outputData.back().data;
164  outputDetSetData.resize(STRIPS_PER_FEDCH);
165  std::vector<SiStripRawDigi>::iterator outputBegin = outputDetSetData.begin();
166  std::copy(payloadBegin, payloadEnd, outputBegin);
167 
168  }
169 
170  aFedScopeDigis.clear();
171  aAddrVec.clear();
172  aHeaderBitVec.clear();
173 
174  aAddrVec.reserve(2*sistrip::FEDCH_PER_FED);
175  aHeaderBitVec.reserve(sistrip::FEDCH_PER_FED);
176  aFedScopeDigis.reserve(sistrip::FEDCH_PER_FED);
177 
178 
179  }
DSVRawDigis::detset DetSetRawDigis
static std::pair< uint16_t, uint32_t > findMajorityValue(std::vector< uint16_t > &values, const uint16_t aFedId=0)
static const uint16_t STRIPS_PER_FEDCH
static const uint16_t FEDCH_PER_FED
collection_type::const_iterator const_iterator
Definition: DetSet.h:33
std::unique_ptr< SpyDigiConverter::DSVRawDigis > sistrip::SpyDigiConverter::reorderDigis ( const DSVRawDigis inputPayloadDigis)
static

Definition at line 184 of file SiStripSpyDigiConverter.cc.

References edm::DetSetVector< T >::begin(), edm::DetSetVector< T >::end(), sistrip::FEDStripOrdering::physicalOrderForStripInChannel(), edm::DetSetVector< T >::size(), and sistrip::STRIPS_PER_FEDCH.

Referenced by sistrip::SpyDigiConverterModule::produce(), and ~SpyDigiConverter().

185  {
186  // Data is already sorted so push back fast into vector to avoid sorts and create DSV later
187  std::vector<DetSetRawDigis> outputData;
188  outputData.reserve(inputPayloadDigis->size());
189 
190  // Loop over channels in input collection
191  for (DSVRawDigis::const_iterator inputChannel = inputPayloadDigis->begin(); inputChannel != inputPayloadDigis->end(); ++inputChannel) {
192  const std::vector<SiStripRawDigi>& inputDetSetData = inputChannel->data;
193  // Create new detSet with same key (in this case it is the fedKey, not detId)
194  outputData.push_back( DetSetRawDigis(inputChannel->detId()) );
195  std::vector<SiStripRawDigi>& outputDetSetData = outputData.back().data;
196  outputDetSetData.resize(STRIPS_PER_FEDCH);
197  // Copy the data into the output vector reordering
198  for (uint16_t readoutOrderStripIndex = 0; readoutOrderStripIndex < inputDetSetData.size(); ++readoutOrderStripIndex) {
199  const uint16_t physicalOrderStripIndex = FEDStripOrdering::physicalOrderForStripInChannel(readoutOrderStripIndex);
200  outputDetSetData.at(physicalOrderStripIndex) = inputDetSetData.at(readoutOrderStripIndex);
201  }
202  }
203 
204  //return DSV of output
205  return std::unique_ptr<DSVRawDigis>( new DSVRawDigis(outputData,true) );
206  } // end of SpyDigiConverter::reorderDigis method.
static uint8_t physicalOrderForStripInChannel(const uint8_t readoutOrderStripIndexInChannel)
DSVRawDigis::detset DetSetRawDigis
static const uint16_t STRIPS_PER_FEDCH
edm::DetSetVector< SiStripRawDigi > DSVRawDigis
collection_type::const_iterator const_iterator
Definition: DetSetVector.h:104