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PixelFEDCard.cc
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1 // Read the pixelFED setup parameters from an ASCII file
2 // Will Johns & Danek Kotlinski 04/06.
3 
4 #include <iostream>
5 
6 #include "CalibFormats/SiPixelObjects/interface/PixelFEDCard.h"
7 #include "CalibFormats/SiPixelObjects/interface/PixelTimeFormatter.h"
8 
9 #include <cassert>
10 #include <sstream>
11 #include <map>
12 #include <stdexcept>
13 
14 using namespace std;
15 
16 using namespace pos;
17 
18 
19 PixelFEDCard::PixelFEDCard():
20  PixelConfigBase(" "," "," ")
21 {
22  clear();
23 }
24 
25 // modified by MR on 24-04-2008 12:05:42
26 // Read configuration from DB
27 PixelFEDCard::PixelFEDCard(vector<vector<string> > &tableMat):PixelConfigBase(" "," "," ")
28 {
29  std::string mthn = "[PixelFEDCard::PixelFEDCard()]\t\t " ;
30  vector<string> ins = tableMat[0];
31  map<string , int > colM;
32  vector<string> colNames;
33  bool first = true ;
134  colNames.push_back("BUSYWHENBEHIND" );
135  colNames.push_back("FEATUREREGISTER" );
136  colNames.push_back("FIFO2LIMIT" );
137  colNames.push_back("TIMEOUTOROOSLIMIT" );
138  colNames.push_back("LASTDACOFF" );
139  colNames.push_back("SIMHITSPERROC" );
140  colNames.push_back("BUSYHOLDMIN" );
141  colNames.push_back("SPARE1" );
142  colNames.push_back("SPARE2" );
143  colNames.push_back("SPARE3" );
144  colNames.push_back("SPARE4" );
145  colNames.push_back("SPARE5" );
146  colNames.push_back("SPARE6" );
147  colNames.push_back("SPARE7" );
148  colNames.push_back("SPARE8" );
149  colNames.push_back("SPARE9" );
150  colNames.push_back("SPARE10" );
151  colNames.push_back("CONFIG_KEY" );
152  colNames.push_back("KEY_TYPE" );
153  colNames.push_back("KEY_ALIAS_ID" );
154  colNames.push_back("KEY_ALIAS" );
155  colNames.push_back("VERSION" );
156  colNames.push_back("KIND_OF_COND" );
157  colNames.push_back("CRATE_LABEL" );
158  colNames.push_back("CRATE_NUMBER" );
159  colNames.push_back("SLOT_NUMBER" );
160  colNames.push_back("VME_ADDRS_HEX" );
161  colNames.push_back("PIXEL_FED" );
162  colNames.push_back("CHANNEL_ID" );
163  colNames.push_back("NUM_ROCS" );
164  colNames.push_back("CHAN_OFFST_DAC" );
165  colNames.push_back("CHAN_DELAY" );
166  colNames.push_back("CHAN_BHIGH" );
167  colNames.push_back("CHAN_BLOW" );
168  colNames.push_back("CHAN_UB" );
169  colNames.push_back("OPT1_CAP" );
170  colNames.push_back("OPT2_CAP" );
171  colNames.push_back("OPT3_CAP" );
172  colNames.push_back("OPT1_INP" );
173  colNames.push_back("OPT2_INP" );
174  colNames.push_back("OPT3_INP" );
175  colNames.push_back("OPT1_OUT" );
176  colNames.push_back("OPT2_OUT" );
177  colNames.push_back("OPT3_OUT" );
178  colNames.push_back("NORTH_CLKPHB" );
179  colNames.push_back("NORTHCENTER_CLKPHB" );
180  colNames.push_back("SOUTHCENTER_CLKPHB" );
181  colNames.push_back("SOUTH_CLKPHB" );
182  colNames.push_back("NORTH_CTRL" );
183  colNames.push_back("NORTHCENTER_CTRL" );
184  colNames.push_back("SOUTHCENTER_CTRL" );
185  colNames.push_back("SOUTH_CTRL" );
186  colNames.push_back("REG0_TTCRX_FDLA" );
187  colNames.push_back("REG1_TTCRX_FDLA" );
188  colNames.push_back("REG2_TTCRX_CDLA" );
189  colNames.push_back("REG3_TTCRX_CLKD2" );
190  colNames.push_back("CENTER_CTRL" );
191  colNames.push_back("CENTER_MODE" );
192  colNames.push_back("B1_ADCGN" );
193  colNames.push_back("B2_ADCGN" );
194  colNames.push_back("B3_ADCGN" );
195  colNames.push_back("B4_ADCGN" );
196  colNames.push_back("NORTH_BADJ" );
197  colNames.push_back("NORTHCENTER_BADJ" );
198  colNames.push_back("SOUTHCENTER_BADJ" );
199  colNames.push_back("SOUTH_BADJ" );
200  colNames.push_back("NORTH_TBMMASK" );
201  colNames.push_back("NORTHCENTER_TBMMASK" );
202  colNames.push_back("SOUTHCENTER_TBMMASK" );
203  colNames.push_back("SOUTH_TBMMASK" );
204  colNames.push_back("NORTH_PWORD" );
205  colNames.push_back("NORTHCENTER_PWORD" );
206  colNames.push_back("SOUTH_PWORD" );
207  colNames.push_back("SOUTHCENTER_PWORD" );
208  colNames.push_back("SPECDAC" );
209  colNames.push_back("OOS_LVL" );
210  colNames.push_back("ERR_LVL" );
211  colNames.push_back("NORTH_FIFO1_BZ_LVL" );
212  colNames.push_back("NORTHCENTER_FIFO1_BZ_LVL");
213  colNames.push_back("SOUTHCENTER_FIFO1_BZ_LVL");
214  colNames.push_back("SOUTH_FIFO1_BZ_LVL" );
215  colNames.push_back("FIFO3_WRN_LVL" );
216  colNames.push_back("FED_MASTER_DELAY" );
217  colNames.push_back("NO_HITLIMIT" );
218  colNames.push_back("NC_HITLIMIT" );
219  colNames.push_back("SC_HITLIMIT" );
220  colNames.push_back("SO_HITLIMIT" );
221  colNames.push_back("NO_TESTREG" );
222  colNames.push_back("NC_TESTREG" );
223  colNames.push_back("SC_TESTREG" );
224  colNames.push_back("SO_TESTREG" );
225  colNames.push_back("TRIGGERHOLDOFF" );
226 
227  for(unsigned int c = 0 ; c < ins.size() ; c++)
228  {
229  for(unsigned int n=0; n<colNames.size(); n++)
230  {
231  if(tableMat[0][c] == colNames[n]){
232  colM[colNames[n]] = c;
233  break;
234  }
235  }
236  }//end for
237  for(unsigned int n=0; n<colNames.size(); n++)
238  {
239  if(colM.find(colNames[n]) == colM.end())
240  {
241  std::cerr << __LINE__ << "]\t[PixelFEDCard::PixelFEDCard]\tCouldn't find in the database the column with name " << colNames[n] << std::endl;
242  assert(0);
243  }
244  }
245  // disentagle different tables
246  int size[3] ;
247  int indexsize = 0 ;
248  for(unsigned int r = 0 ; r < tableMat.size() ; r++){ //Goes to every row of the Matrix
249  if(tableMat[r].empty())
250  {
251 // cout << __LINE__ << "]\t" << mthn << "__________________ NEW TABLE __________________"<< endl ;
252  size[indexsize] = r ;
253 // cout << __LINE__ << "]\t" << mthn << "size[" << indexsize << "] = " << size[indexsize] << endl ;
254  indexsize++ ;
255  continue ;
256  }
257  for(vector<string>::iterator it = tableMat[r].begin() ; it != tableMat[r].end() ; ++it)
258  {
259 // cout << __LINE__ << "]\t" << mthn << *it <<"["<<&*it<<"]\t" ;
260 // cout << __LINE__ << "]\t" << mthn << *it <<"\t" ;
261  }
262 // cout << __LINE__ << "]\t" << mthn << endl ;
263  }
264 
265  // Read below quantities pertaining to a single FED that are equal accross 36 channels
266  if(first)
267  {
268  first = false ;
269  //VME base address
270  //Fed Base Address
271  sscanf( tableMat[1][colM["VME_ADDRS_HEX"] ].c_str(),"%lx",&FEDBASE_0);
272  // sscanf(tableMat[1][colM["PIXEL_FED"]].c_str(), "PxlFED_%ld",&fedNumber);
273  fedNumber = atoi(tableMat[1][colM["PIXEL_FED"] ].c_str()) ;
274  //Settable optical input parameters (one for each 12-receiver)
275  opt_cap[0] = atoi(tableMat[1][colM["OPT1_CAP"] ].c_str()) ;
276  opt_cap[1] = atoi(tableMat[1][colM["OPT2_CAP"] ].c_str()) ;
277  opt_cap[2] = atoi(tableMat[1][colM["OPT3_CAP"] ].c_str()) ;
278  opt_inadj[0] = atoi(tableMat[1][colM["OPT1_INP"] ].c_str()) ;
279  opt_inadj[1] = atoi(tableMat[1][colM["OPT2_INP"] ].c_str()) ;
280  opt_inadj[2] = atoi(tableMat[1][colM["OPT3_INP"] ].c_str()) ;
281  opt_ouadj[0] = atoi(tableMat[1][colM["OPT1_OUT"] ].c_str()) ;
282  opt_ouadj[1] = atoi(tableMat[1][colM["OPT2_OUT"] ].c_str()) ;
283  opt_ouadj[2] = atoi(tableMat[1][colM["OPT3_OUT"] ].c_str()) ;
284 
285  //clock phases, use bits 0-8, select the clock edged
286  clkphs1_9 = atoi(tableMat[1][colM["NORTH_CLKPHB"] ].c_str()) ; // TO BE VERIFIED
287  clkphs10_18 = atoi(tableMat[1][colM["NORTHCENTER_CLKPHB"] ].c_str()) ; // TO BE VERIFIED
288  clkphs19_27 = atoi(tableMat[1][colM["SOUTHCENTER_CLKPHB"] ].c_str()) ; // TO BE VERIFIED
289  clkphs28_36 = atoi(tableMat[1][colM["SOUTH_CLKPHB"] ].c_str()) ; // TO BE VERIFIED
290 
291  // Control register and delays for the TTCrx
292  FineDes1Del = atoi(tableMat[1][colM["REG0_TTCRX_FDLA"] ].c_str()) ;
293  FineDes2Del = atoi(tableMat[1][colM["REG1_TTCRX_FDLA"] ].c_str()) ;
294  CoarseDel = atoi(tableMat[1][colM["REG2_TTCRX_CDLA"] ].c_str()) ;
295  ClkDes2 = atoi(tableMat[1][colM["REG3_TTCRX_CLKD2"] ].c_str()) ;
296 
297  Ccntrl = atoi(tableMat[1][colM["CENTER_CTRL"] ].c_str()) ;
298  modeRegister = atoi(tableMat[1][colM["CENTER_MODE"] ].c_str()) ;
299 
300  //data Regs adjustable fifo Almost Full levels
301  Nfifo1Bzlvl = atoi(tableMat[1][colM["NORTH_FIFO1_BZ_LVL"] ].c_str()) ;
302  NCfifo1Bzlvl = atoi(tableMat[1][colM["NORTHCENTER_FIFO1_BZ_LVL"]].c_str()) ;
303  SCfifo1Bzlvl = atoi(tableMat[1][colM["SOUTHCENTER_FIFO1_BZ_LVL"]].c_str()) ;
304  Sfifo1Bzlvl = atoi(tableMat[1][colM["SOUTH_FIFO1_BZ_LVL"] ].c_str()) ;
305 
306  //Bits (1st 8) used to mask TBM trailer bits
307  N_TBMmask = atoi(tableMat[1][colM["NORTH_TBMMASK"] ].c_str()) ;
308  NC_TBMmask = atoi(tableMat[1][colM["NORTHCENTER_TBMMASK"] ].c_str()) ;
309  SC_TBMmask = atoi(tableMat[1][colM["SOUTHCENTER_TBMMASK"] ].c_str()) ;
310  S_TBMmask = atoi(tableMat[1][colM["SOUTH_TBMMASK"] ].c_str()) ;
311 
312  //Bits (1st 8) used to set the Private Word in the gap and filler words
313  N_Pword = atoi(tableMat[1][colM["NORTH_PWORD"] ].c_str()) ;
314  NC_Pword = atoi(tableMat[1][colM["NORTHCENTER_PWORD"] ].c_str()) ;
315  SC_Pword = atoi(tableMat[1][colM["SOUTHCENTER_PWORD"] ].c_str()) ;
316  S_Pword = atoi(tableMat[1][colM["SOUTH_PWORD"] ].c_str()) ;
317 
318  Nbaseln = atoi(tableMat[1][colM["NORTH_BADJ"] ].c_str()) ;
319  NCbaseln = atoi(tableMat[1][colM["NORTHCENTER_BADJ"] ].c_str()) ;
320  SCbaseln = atoi(tableMat[1][colM["SOUTHCENTER_BADJ"] ].c_str()) ;
321  Sbaseln = atoi(tableMat[1][colM["SOUTH_BADJ"] ].c_str()) ;
322 
323  Ncntrl = atoi(tableMat[1][colM["NORTH_CTRL"] ].c_str()) ;
324  NCcntrl = atoi(tableMat[1][colM["NORTHCENTER_CTRL"] ].c_str()) ;
325  SCcntrl = atoi(tableMat[1][colM["SOUTHCENTER_CTRL"] ].c_str()) ;
326  Scntrl = atoi(tableMat[1][colM["SOUTH_CTRL"] ].c_str()) ;
327 
328 
329  //These bit sets the special dac mode for random triggers
330  SpecialDac = atoi(tableMat[1][colM["SPECDAC"] ].c_str()) ;
331 
332  //These bits set the number of Out of consecutive out of sync events until a TTs OOs
333  Ooslvl = atoi(tableMat[1][colM["OOS_LVL"] ].c_str()) ;
334  //These bits set the number of Empty events until a TTs Error
335  Errlvl = atoi(tableMat[1][colM["ERR_LVL"] ].c_str()) ;
336 
337  //Control Regs for setting ADC 1Vpp and 2Vpp
338  Nadcg = atoi(tableMat[1][colM["B1_ADCGN"] ].c_str()) ;
339  NCadcg = atoi(tableMat[1][colM["B2_ADCGN"] ].c_str()) ;
340  SCadcg = atoi(tableMat[1][colM["B3_ADCGN"] ].c_str()) ;
341  Sadcg = atoi(tableMat[1][colM["B4_ADCGN"] ].c_str()) ;
342  fifo3Wrnlvl = atoi(tableMat[1][colM["FIFO3_WRN_LVL"] ].c_str()) ;
343  FedTTCDelay = atoi(tableMat[1][colM["FED_MASTER_DELAY"] ].c_str()) ;
344  N_hitlimit = atoi(tableMat[1][colM["NO_HITLIMIT"] ].c_str()) ;
345  NC_hitlimit = atoi(tableMat[1][colM["NC_HITLIMIT"] ].c_str()) ;
346  SC_hitlimit = atoi(tableMat[1][colM["SC_HITLIMIT"] ].c_str()) ;
347  S_hitlimit = atoi(tableMat[1][colM["SO_HITLIMIT"] ].c_str()) ;
348  N_testreg = atoi(tableMat[1][colM["NO_TESTREG"] ].c_str()) ;
349  NC_testreg = atoi(tableMat[1][colM["NC_TESTREG"] ].c_str()) ;
350  SC_testreg = atoi(tableMat[1][colM["SC_TESTREG"] ].c_str()) ;
351  S_testreg = atoi(tableMat[1][colM["SO_TESTREG"] ].c_str()) ;
352  BusyHoldMin = atoi(tableMat[1][colM["BUSYHOLDMIN"] ].c_str()) ;
353  BusyWhenBehind = atoi(tableMat[1][colM["BUSYWHENBEHIND"] ].c_str()) ;
354  FeatureRegister = atoi(tableMat[1][colM["FEATUREREGISTER"] ].c_str()) ;
355  FIFO2Limit = atoi(tableMat[1][colM["FIFO2LIMIT"] ].c_str()) ;
356  LastDacOff = atoi(tableMat[1][colM["LASTDACOFF"] ].c_str()) ;
357  SimHitsPerRoc = atoi(tableMat[1][colM["SIMHITSPERROC"] ].c_str()) ;
358  TimeoutOROOSLimit = atoi(tableMat[1][colM["TIMEOUTOROOSLIMIT"] ].c_str()) ;
359  TriggerHoldoff = atoi(tableMat[1][colM["TRIGGERHOLDOFF"] ].c_str()) ;
360 
361  SPARE1 = atoi(tableMat[1][colM["SPARE1"] ].c_str()) ;
362  SPARE2 = atoi(tableMat[1][colM["SPARE2"] ].c_str()) ;
363  SPARE3 = atoi(tableMat[1][colM["SPARE3"] ].c_str()) ;
364  SPARE4 = atoi(tableMat[1][colM["SPARE4"] ].c_str()) ;
365  SPARE5 = atoi(tableMat[1][colM["SPARE5"] ].c_str()) ;
366  SPARE6 = atoi(tableMat[1][colM["SPARE6"] ].c_str()) ;
367  SPARE7 = atoi(tableMat[1][colM["SPARE7"] ].c_str()) ;
368  SPARE8 = atoi(tableMat[1][colM["SPARE8"] ].c_str()) ;
369  SPARE9 = atoi(tableMat[1][colM["SPARE9"] ].c_str()) ;
370  SPARE10 = atoi(tableMat[1][colM["SPARE10"] ].c_str()) ;
371 
372  } // end of 'first' condition
373  for(int r = 1 ; r < size[0] ; r++) //Goes to every row of the FIRST Matrix (MUST BE 36, one for each FED channel)
374  {
375  //Number of ROCS per FED channel
376  NRocs[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str())-1] = atoi(tableMat[r][colM["NUM_ROCS"]].c_str() ) ;
377  //input offset dac (one for each channel)
378  offs_dac[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str())-1] = atoi(tableMat[r][colM["CHAN_OFFST_DAC"]].c_str() ) ;
379  //Channel delays, one for each channel, 0=15
380  DelayCh[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str())-1] = atoi(tableMat[r][colM["CHAN_DELAY"]].c_str() ) ;
381  //Blacks and Ultra-blacks, 3 limit per channel
382  BlackHi[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str())-1] = atoi(tableMat[r][colM["CHAN_BHIGH"]].c_str() ) ;
383  BlackLo[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str())-1] = atoi(tableMat[r][colM["CHAN_BLOW"]].c_str() ) ;
384  Ublack[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str())-1] = atoi(tableMat[r][colM["CHAN_UB"]].c_str() ) ;
385  }
386 
387  readDBTBMLevels(tableMat, size[0]+1, size[1]) ;
388  readDBROCLevels(tableMat, size[1]+1, size[2]) ;
389  Ccntrl_original=Ccntrl;
390  modeRegister_original=modeRegister;
391 
392 
393  Ncntrl_original=Ncntrl;
394  NCcntrl_original=NCcntrl;
395  SCcntrl_original=SCcntrl;
396  Scntrl_original=Scntrl;
397 
398  Nbaseln_original=Nbaseln;
399  NCbaseln_original=NCbaseln;
400  SCbaseln_original=SCbaseln;
401  Sbaseln_original=Sbaseln;
402 
403  // Modified by MR on 17-11-2008
404  // This new variable has to be read from DB!!!!!
405  // We need to add a column in the DB. Talk to Umesh.
406  FineDes1Del = 14 ;
407 }
408 
409 void PixelFEDCard::readDBTBMLevels(std::vector<std::vector<std::string> > &tableMat, int firstRow, int lastRow)
410 {
411  string mthn = "[PixelFEDCard::readDBTBMLevels()] ";
412  vector<string> ins = tableMat[firstRow];
413  map<string , int > colM;
414  vector<string> colNames;
415 
444  colNames.push_back("CONFIG_KEY" );
445  colNames.push_back("KEY_TYPE" );
446  colNames.push_back("KEY_ALIAS" );
447  colNames.push_back("VERSION" );
448  colNames.push_back("KIND_OF_COND" );
449  colNames.push_back("TBM_NAME" );
450  colNames.push_back("PIXEL_FED" );
451  colNames.push_back("FED_CHAN" );
452  colNames.push_back("TBMA_HEAD_L0" );
453  colNames.push_back("TBMA_HEAD_L1" );
454  colNames.push_back("TBMA_HEAD_L2" );
455  colNames.push_back("TBMA_HEAD_L3" );
456  colNames.push_back("TBMA_HEAD_L4" );
457  colNames.push_back("TBMA_TRAIL_L0");
458  colNames.push_back("TBMA_TRAIL_L1");
459  colNames.push_back("TBMA_TRAIL_L2");
460  colNames.push_back("TBMA_TRAIL_L3");
461  colNames.push_back("TBMA_TRAIL_L4");
462  colNames.push_back("TBMA_HEAD_B" );
463  colNames.push_back("TBMA_HEAD_UB" );
464  colNames.push_back("TBMA_TRAIL_B" );
465  colNames.push_back("TBMA_TRAIL_UB");
466 /*
467  colNames.push_back("CONFIG_KEY_ID" );
468  colNames.push_back("CONFIG_KEY" );
469  colNames.push_back("VERSION" );
470  colNames.push_back("CONDITION_DATA_SET_ID" );
471  colNames.push_back("KIND_OF_CONDITION_ID" );
472  colNames.push_back("KIND_OF_COND" );
473  colNames.push_back("PXLFED_NAME" );
474  colNames.push_back("FED_CHAN" );
475  colNames.push_back("TBM_PART_ID" );
476  colNames.push_back("TBM_SER_NUM" );
477  colNames.push_back("PANEL_NAME" );
478  colNames.push_back("HUB_ADDRS" );
479  colNames.push_back("TBMA_HEAD_L0" );
480  colNames.push_back("TBMA_HEAD_L1" );
481  colNames.push_back("TBMA_HEAD_L2" );
482  colNames.push_back("TBMA_HEAD_L3" );
483  colNames.push_back("TBMA_HEAD_L4" );
484  colNames.push_back("TBMA_TRAIL_L0" );
485  colNames.push_back("TBMA_TRAIL_L1" );
486  colNames.push_back("TBMA_TRAIL_L2" );
487  colNames.push_back("TBMA_TRAIL_L3" );
488  colNames.push_back("TBMA_TRAIL_L4" );
489 */
490  // Retrieve header row and cross check that everyfield is there.
491  for(unsigned int c = 0 ; c < ins.size() ; c++)
492  {
493  for(unsigned int n=0; n<colNames.size(); n++)
494  {
495  if(tableMat[firstRow][c] == colNames[n]){
496  colM[colNames[n]] = c;
497  break;
498  }
499  }
500  }//end for
501  for(unsigned int n=0; n<colNames.size(); n++)
502  {
503  if(colM.find(colNames[n]) == colM.end())
504  {
505  std::cerr << mthn << "\tCouldn't find in the database the column with name " << colNames[n] << std::endl;
506  assert(0);
507  }
508  }
509  for(int r = firstRow + 1 ; r < lastRow ; r++) //Goes to every row of the Matrix (MUST BE 36, one for each FED channel)
510  {
511  //Signal levels for the TBM, one per channel
512  TBM_L0[atoi(tableMat[r][colM["FED_CHAN"]].c_str())-1] = atoi(tableMat[r][colM["TBMA_HEAD_L0"]].c_str() ) ;
513  TBM_L1[atoi(tableMat[r][colM["FED_CHAN"]].c_str())-1] = atoi(tableMat[r][colM["TBMA_HEAD_L1"]].c_str() ) ;
514  TBM_L2[atoi(tableMat[r][colM["FED_CHAN"]].c_str())-1] = atoi(tableMat[r][colM["TBMA_HEAD_L2"]].c_str() ) ;
515  TBM_L3[atoi(tableMat[r][colM["FED_CHAN"]].c_str())-1] = atoi(tableMat[r][colM["TBMA_HEAD_L3"]].c_str() ) ;
516  TBM_L4[atoi(tableMat[r][colM["FED_CHAN"]].c_str())-1] = atoi(tableMat[r][colM["TBMA_HEAD_L4"]].c_str() ) ;
517  TRL_L0[atoi(tableMat[r][colM["FED_CHAN"]].c_str())-1] = atoi(tableMat[r][colM["TBMA_TRAIL_L0"]].c_str() ) ;
518  TRL_L1[atoi(tableMat[r][colM["FED_CHAN"]].c_str())-1] = atoi(tableMat[r][colM["TBMA_TRAIL_L1"]].c_str() ) ;
519  TRL_L2[atoi(tableMat[r][colM["FED_CHAN"]].c_str())-1] = atoi(tableMat[r][colM["TBMA_TRAIL_L2"]].c_str() ) ;
520  TRL_L3[atoi(tableMat[r][colM["FED_CHAN"]].c_str())-1] = atoi(tableMat[r][colM["TBMA_TRAIL_L3"]].c_str() ) ;
521  TRL_L4[atoi(tableMat[r][colM["FED_CHAN"]].c_str())-1] = atoi(tableMat[r][colM["TBMA_TRAIL_L4"]].c_str() ) ;
522  }
523 }
524 
525 void PixelFEDCard::readDBROCLevels(std::vector<std::vector<std::string> > &tableMat, int firstRow, int lastRow)
526 {
527  string mthn = "[PixelFEDCard::readDBROCLevels()] ";
528  map<string , int > colM;
529  vector<string> colNames;
530 
553  colNames.push_back("CONFIG_KEY" );
554  colNames.push_back("KEY_TYPE" );
555  colNames.push_back("KEY_ALIAS" );
556  colNames.push_back("VERSION" );
557  colNames.push_back("KIND_OF_COND");
558  colNames.push_back("ROC_NAME" );
559  colNames.push_back("FED_ROC_NUM" );
560  colNames.push_back("PIXEL_FED" );
561  colNames.push_back("FED_CHAN" );
562  colNames.push_back("ROC_L0" );
563  colNames.push_back("ROC_L1" );
564  colNames.push_back("ROC_L2" );
565  colNames.push_back("ROC_L3" );
566  colNames.push_back("ROC_L4" );
567  colNames.push_back("ROC_B" );
568  colNames.push_back("ROC_UB" );
569 /*
570  colNames.push_back("CONFIG_KEY_ID" );
571  colNames.push_back("CONFIG_KEY" );
572  colNames.push_back("VERSION" );
573  colNames.push_back("KIND_OF_COND" );
574  colNames.push_back("PXLFED_NAME" );
575  colNames.push_back("FED_CHAN" );
576  colNames.push_back("AOH_CHAN" );
577  colNames.push_back("ROC_NAME" );
578  colNames.push_back("HUB_ADDRS" );
579  colNames.push_back("PORT_NUMBER" );
580  colNames.push_back("ROC_I2C_ADDR" );
581  colNames.push_back("GEOM_ROC_NUM" );
582  colNames.push_back("FED_ROC_NUM" );
583  colNames.push_back("ROC_L0" );
584  colNames.push_back("ROC_L1" );
585  colNames.push_back("ROC_L2" );
586  colNames.push_back("ROC_L3" );
587  colNames.push_back("ROC_L4" );
588 */
589  // Retrieve header row and cross check that everyfield is there.
590  for(unsigned int c = 0 ; c < tableMat[firstRow].size() ; c++)
591  {
592  for(unsigned int n=0; n<colNames.size(); n++)
593  {
594  if(tableMat[firstRow][c] == colNames[n]){
595  colM[colNames[n]] = c;
596  break;
597  }
598  }
599  }//end for
600  for(unsigned int n=0; n<colNames.size(); n++)
601  {
602  if(colM.find(colNames[n]) == colM.end())
603  {
604  std::cerr << mthn << "\tCouldn't find in the database the column with name " << colNames[n] << std::endl;
605  assert(0);
606  }
607  }
608  // Address levels 1 per channel (36) per roc(max=26)
609 // int ROC_L0[36][26],ROC_L1[36][26],ROC_L2[36][26],ROC_L3[36][26],ROC_L4[36][26];
610 
611  for(int r = firstRow + 1 ; r < lastRow ; r++) //Goes to every row of the Matrix (MUST BE 36, one for each FED channel)
612  {
613  ROC_L0[atoi(tableMat[r][colM["FED_CHAN"]].c_str())-1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] = atoi(tableMat[r][colM["ROC_L0"]].c_str()) ;
614  ROC_L1[atoi(tableMat[r][colM["FED_CHAN"]].c_str())-1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] = atoi(tableMat[r][colM["ROC_L1"]].c_str()) ;
615  ROC_L2[atoi(tableMat[r][colM["FED_CHAN"]].c_str())-1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] = atoi(tableMat[r][colM["ROC_L2"]].c_str()) ;
616  ROC_L3[atoi(tableMat[r][colM["FED_CHAN"]].c_str())-1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] = atoi(tableMat[r][colM["ROC_L3"]].c_str()) ;
617  ROC_L4[atoi(tableMat[r][colM["FED_CHAN"]].c_str())-1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] = atoi(tableMat[r][colM["ROC_L4"]].c_str()) ;
618  }
619 
620 }
621 
622 
623 // Read the configuration parameters from file
624 PixelFEDCard::PixelFEDCard(string fileName):
625  PixelConfigBase(" "," "," ")
626 {
627 
628  std::string mthn = "]\t[PixelFEDCard::PixelFEDCard()]\t\t\t\t " ;
629  //const bool localDEBUG = true;
630  const bool localDEBUG = false;
631 
632  // Added by Dario (March 26th, 2008): insure variables are all cleared before read-in
633  clear() ;
634 
635  // cout << __LINE__ << "]\t" << mthn <<" Get setup parameters from file "<<fileName<<endl;
636  FILE *infile = fopen((fileName.c_str()),"r");
637  if (infile == nullptr) throw std::runtime_error("Failed to open FED Card parameter file: "+fileName);
638 
639  //Fed Base Address
640  fscanf(infile,"FED Base address :%lx\n",
641  &FEDBASE_0);
642  fscanf(infile,"FEDID Number :%lx\n",
643  &fedNumber);
644 
645 // if(localDEBUG) cout << __LINE__ << mthn << "FED Base address, FED # : " << std::hex << FEDBASE_0 << std::dec << std::endl ;
646 // if(localDEBUG) printf("FED Base address, FED # :%lx\n",FEDBASE_0);
647  //if(FEDBASE != FEDBASE_0) cout<< __LINE__ << "]\t" << mthn << " Inconsistent FED base address?"<<endl;
648 // if(localDEBUG) cout << __LINE__ << mthn << "FEDID # : " << std::hex << fedNumber << std::dec << std::endl ;
649 // if(localDEBUG) printf("FEDID # :%lx\n",fedNumber);
650 
651  // Number of ROCs
652  int ijx=0;
653  for(int i=0;i<36;i++){
654  ijx=i+1;
655  fscanf(infile,"Number of ROCs Chnl %d:%d \n",&ijx,&NRocs[i]);
656  if(localDEBUG)printf("Number of ROCs per Chnl %d:%d \n",ijx,NRocs[i]);
657  }
658 
659  //Settable optical input parameters
660  fscanf(infile,"Optical reciever 1 Capacitor Adjust(0-3):%d\n",&opt_cap[0]);
661  fscanf(infile,"Optical reciever 2 Capacitor Adjust(0-3):%d\n",&opt_cap[1]);
662  fscanf(infile,"Optical reciever 3 Capacitor Adjust(0-3):%d\n",&opt_cap[2]);
663  fscanf(infile,"Optical reciever 1 Input Offset (0-15) :%d\n",&opt_inadj[0]);
664  fscanf(infile,"Optical reciever 2 Input Offset (0-15) :%d\n",&opt_inadj[1]);
665  fscanf(infile,"Optical reciever 3 Input Offset (0-15) :%d\n",&opt_inadj[2]);
666  fscanf(infile,"Optical reciever 1 Output Offset (0-3) :%d\n",&opt_ouadj[0]);
667  fscanf(infile,"Optical reciever 2 Output Offset (0-3) :%d\n",&opt_ouadj[1]);
668  fscanf(infile,"Optical reciever 3 Output Offset (0-3) :%d\n",&opt_ouadj[2]);
669 
670  if(localDEBUG) {
671  printf("Optical reciever 1 Capacitor Adjust(0-3):%d\n",opt_cap[0]);
672  printf("Optical reciever 2 Capacitor Adjust(0-3):%d\n",opt_cap[1]);
673  printf("Optical reciever 3 Capacitor Adjust(0-3):%d\n",opt_cap[2]);
674  printf("Optical reciever 1 Input Offset (0-15) :%d\n",opt_inadj[0]);
675  printf("Optical reciever 2 Input Offset (0-15) :%d\n",opt_inadj[1]);
676  printf("Optical reciever 3 Input Offset (0-15) :%d\n",opt_inadj[2]);
677  printf("Optical reciever 1 Output Offset (0-3) :%d\n",opt_ouadj[0]);
678  printf("Optical reciever 2 Output Offset (0-3) :%d\n",opt_ouadj[1]);
679  printf("Optical reciever 3 Output Offset (0-3) :%d\n",opt_ouadj[2]);
680  }
681 
682  //input offset dac
683  for(int i=0;i<36;i++) {
684  fscanf(infile,"Offset DAC channel %d:%d\n",&ijx,&offs_dac[i]);
685  if(localDEBUG) printf("Offset DAC channel %d:%d\n",i+1,offs_dac[i]);
686  }
687 
688  //clock phases
689  fscanf(infile,"Clock Phase Bits ch 1-9:%x\n",& clkphs1_9 );
690  fscanf(infile,"Clock Phase Bits ch 10-18:%x\n",&clkphs10_18);
691  fscanf(infile,"Clock Phase Bits ch 19-27:%x\n",&clkphs19_27);
692  fscanf(infile,"Clock Phase Bits ch 28-36:%x\n",&clkphs28_36);
693  if(localDEBUG)printf("Clock Phase Bits ch 1-9:%x\n",clkphs1_9 );
694  if(localDEBUG)printf("Clock Phase Bits ch 10-18:%x\n",clkphs10_18 );
695  if(localDEBUG)printf("Clock Phase Bits ch 19-27:%x\n",clkphs19_27 );
696  if(localDEBUG)printf("Clock Phase Bits ch 28-36:%x\n",clkphs28_36 );
697 
698  //Blacks
699  for(int i=0;i<36;i++){
700  fscanf(infile,"Black HiThold ch %d:%d \n",&ijx,&BlackHi[i]);
701  fscanf(infile,"Black LoThold ch %d:%d \n",&ijx,&BlackLo[i]);
702  fscanf(infile,"ULblack Thold ch %d:%d \n",&ijx, &Ublack[i]);
703  if(localDEBUG)printf("Black HiThold ch %d:%d\n",ijx,BlackHi[i]);
704  if(localDEBUG)printf("Black LoThold ch %d:%d\n",ijx,BlackLo[i]);
705  if(localDEBUG)printf("ULblack Thold ch %d:%d\n",ijx, Ublack[i]);
706  }
707 
708  //Channel delays
709  for(int i=0;i<36;i++) {
710  fscanf(infile,"Delay channel %d(0-15):%d\n",&ijx,&DelayCh[i]);
711  if(localDEBUG)
712  printf("Delay channel %d(0-15):%d\n",i+1,DelayCh[i]);
713  }
714 
715  //Signal levels
716  for(int i=0;i<36;i++) {
717  fscanf(infile,"TBM level 0 Channel %d:%d\n",&ijx,&TBM_L0[i]);
718  fscanf(infile,"TBM level 1 Channel %d:%d\n",&ijx,&TBM_L1[i]);
719  fscanf(infile,"TBM level 2 Channel %d:%d\n",&ijx,&TBM_L2[i]);
720  fscanf(infile,"TBM level 3 Channel %d:%d\n",&ijx,&TBM_L3[i]);
721  fscanf(infile,"TBM level 4 Channel %d:%d\n",&ijx,&TBM_L4[i]);
722  if(localDEBUG)printf("TBM level 0 Channel %d:%d\n",ijx,TBM_L0[i]);
723  if(localDEBUG)printf("TBM level 1 Channel %d:%d\n",ijx,TBM_L1[i]);
724  if(localDEBUG)printf("TBM level 2 Channel %d:%d\n",ijx,TBM_L2[i]);
725  if(localDEBUG)printf("TBM level 3 Channel %d:%d\n",ijx,TBM_L3[i]);
726  if(localDEBUG)printf("TBM level 4 Channel %d:%d\n",ijx,TBM_L4[i]);
727 
728  int ijy=0;
729  for(int j=0;j<NRocs[i];j++) {
730  fscanf(infile,"ROC%d level 0 Channel %d :%d\n",
731  &ijy,&ijx,&ROC_L0[i][j]);
732  fscanf(infile,"ROC%d level 1 Channel %d :%d\n",
733  &ijy,&ijx,&ROC_L1[i][j]);
734  fscanf(infile,"ROC%d level 2 Channel %d :%d\n",
735  &ijy,&ijx,&ROC_L2[i][j]);
736  fscanf(infile,"ROC%d level 3 Channel %d :%d\n",
737  &ijy,&ijx,&ROC_L3[i][j]);
738  fscanf(infile,"ROC%d level 4 Channel %d :%d\n",
739  &ijy,&ijx,&ROC_L4[i][j]);
740  if(localDEBUG)
741  printf("ROC%d level 0 Channel %d :%d\n",ijy,ijx,ROC_L0[i][j]);
742  if(localDEBUG)
743  printf("ROC%d level 1 Channel %d :%d\n",ijy,ijx,ROC_L1[i][j]);
744  if(localDEBUG)
745  printf("ROC%d level 2 Channel %d :%d\n",ijy,ijx,ROC_L2[i][j]);
746  if(localDEBUG)
747  printf("ROC%d level 3 Channel %d :%d\n",ijy,ijx,ROC_L3[i][j]);
748  if(localDEBUG)
749  printf("ROC%d level 4 Channel %d :%d\n",ijy,ijx,ROC_L4[i][j]);
750  }
751 
752  fscanf(infile,"TRLR level 0 Channel %d:%d\n",&ijx,&TRL_L0[i]);
753  fscanf(infile,"TRLR level 1 Channel %d:%d\n",&ijx,&TRL_L1[i]);
754  fscanf(infile,"TRLR level 2 Channel %d:%d\n",&ijx,&TRL_L2[i]);
755  fscanf(infile,"TRLR level 3 Channel %d:%d\n",&ijx,&TRL_L3[i]);
756  fscanf(infile,"TRLR level 4 Channel %d:%d\n",&ijx,&TRL_L4[i]);
757  if(localDEBUG)printf("TRLR level 0 Channel %d:%d\n",ijx,TRL_L0[i]);
758  if(localDEBUG)printf("TRLR level 1 Channel %d:%d\n",ijx,TRL_L1[i]);
759  if(localDEBUG)printf("TRLR level 2 Channel %d:%d\n",ijx,TRL_L2[i]);
760  if(localDEBUG)printf("TRLR level 3 Channel %d:%d\n",ijx,TRL_L3[i]);
761  if(localDEBUG)printf("TRLR level 4 Channel %d:%d\n",ijx,TRL_L4[i]);
762  }
763 
764 
765  //These bits turn off(1) and on(0) channels
766  fscanf(infile,"Channel Enbable bits chnls 1-9 (on = 0):%x\n",
767  &Ncntrl);
768  fscanf(infile,"Channel Enbable bits chnls 10-18(on = 0):%x\n",
769  &NCcntrl);
770  fscanf(infile,"Channel Enbable bits chnls 19-27(on = 0):%x\n",
771  &SCcntrl);
772  fscanf(infile,"Channel Enbable bits chnls 28-36(on = 0):%x\n",
773  &Scntrl);
774  if(localDEBUG)
775  printf("Channel Enbable bits chnls 1-9 (on = 0):%x\n",Ncntrl);
776  if(localDEBUG)
777  printf("Channel Enbable bits chnls 10-18(on = 0):%x\n",NCcntrl);
778  if(localDEBUG)
779  printf("Channel Enbable bits chnls 19-27(on = 0):%x\n",SCcntrl);
780  if(localDEBUG)
781  printf("Channel Enbable bits chnls 28-36(on = 0):%x\n",Scntrl);
782 
783  //These are delays to the TTCrx
784  fscanf(infile,"TTCrx Coarse Delay Register 2:%d\n",&CoarseDel);
785  fscanf(infile,"TTCrc ClkDes2 Register 3:%x\n",&ClkDes2);
786  fscanf(infile,"TTCrc Fine Dlay ClkDes2 Reg 1:%d\n",&FineDes2Del);
787  if(localDEBUG)printf("TTCrx Coarse Delay Register 2:%d\n",CoarseDel);
788  if(localDEBUG)printf("TTCrc ClkDes2 Register 3:%x\n",ClkDes2);
789  if(localDEBUG)printf("TTCrc Fine Dlay ClkDes2 Reg 1:%d\n",FineDes2Del);
790 
791  // Control register
792  fscanf(infile,"Center Chip Control Reg:%x\n",&Ccntrl);
793  if(localDEBUG)printf("Control Reg:0x%x\n",Ccntrl);
794  fscanf(infile,"Initial Slink DAQ mode:%d\n",&modeRegister);
795  if(localDEBUG)printf("Mode Reg:%d\n",modeRegister);
796 
797  //These bits set ADC Gain/Range 1Vpp(0) and 2Vpp(1) for channels
798  fscanf(infile,"Channel ADC Gain bits chnls 1-12(1Vpp = 0):%x\n",
799  &Nadcg);
800  fscanf(infile,"Channel ADC Gain bits chnls 13-20(1Vpp = 0):%x\n",
801  &NCadcg);
802  fscanf(infile,"Channel ADC Gain bits chnls 21-28(1Vpp = 0):%x\n",
803  &SCadcg);
804  fscanf(infile,"Channel ADC Gain bits chnls 29-36(1Vpp = 0):%x\n",
805  &Sadcg);
806  if(localDEBUG)
807  printf("Channel ADC Gain bits chnls 1-12(1Vpp = 0):%x\n",Nadcg);
808  if(localDEBUG)
809  printf("Channel ADC Gain bits chnls 13-20(1Vpp = 0):%x\n",NCadcg);
810  if(localDEBUG)
811  printf("Channel ADC Gain bits chnls 21-28(1Vpp = 0):%x\n",SCadcg);
812  if(localDEBUG)
813  printf("Channel ADC Gain bits chnls 29-36(1Vpp = 0):%x\n",Sadcg);
814 
815  //These bits set Baseline adjustment value (common by FPGA)//can turn on by channel
816  fscanf(infile,"Channel Baseline Enbable chnls 1-9 (on = (0x1ff<<16)+):%x\n",
817  &Nbaseln);
818  fscanf(infile,"Channel Baseline Enbable chnls 10-18(on = (0x1ff<<16)+):%x\n",
819  &NCbaseln);
820  fscanf(infile,"Channel Baseline Enbable chnls 19-27(on = (0x1ff<<16)+):%x\n",
821  &SCbaseln);
822  fscanf(infile,"Channel Baseline Enbable chnls 28-36(on = (0x1ff<<16)+):%x\n",
823  &Sbaseln);
824  if(localDEBUG)
825  printf("Channel Baseline Enbable chnls 1-9 (on = (0x1ff<<16)+):%x\n",Nbaseln);
826  if(localDEBUG)
827  printf("Channel Baseline Enbable chnls 10-18(on = (0x1ff<<16)+):%x\n",NCbaseln);
828  if(localDEBUG)
829  printf("Channel Baseline Enbable chnls 19-27(on = (0x1ff<<16)+):%x\n",SCbaseln);
830  if(localDEBUG)
831  printf("Channel Baseline Enbable chnls 28-36(on = (0x1ff<<16)+):%x\n",Sbaseln);
832 
833  //These bits set TBM trailer mask (common by FPGA)
834  fscanf(infile,"TBM trailer mask chnls 1-9 (0xff = all masked):%x\n",
835  &N_TBMmask);
836  fscanf(infile,"TBM trailer mask chnls 10-18(0xff = all masked):%x\n",
837  &NC_TBMmask);
838  fscanf(infile,"TBM trailer mask chnls 19-27(0xff = all masked):%x\n",
839  &SC_TBMmask);
840  fscanf(infile,"TBM trailer mask chnls 28-36(0xff = all masked):%x\n",
841  &S_TBMmask);
842  if(localDEBUG)
843  printf("TBM trailer mask chnls 1-9 (0xff = all masked):%x\n",N_TBMmask);
844  if(localDEBUG)
845  printf("TBM trailer mask chnls 10-18(0xff = all masked):%x\n",NC_TBMmask);
846  if(localDEBUG)
847  printf("TBM trailer mask chnls 19-27(0xff = all masked):%x\n",SC_TBMmask);
848  if(localDEBUG)
849  printf("TBM trailer mask chnls 28-36(0xff = all masked):%x\n",S_TBMmask);
850 
851  //These bits set the Private fill/gap word value (common by FPGA)
852  fscanf(infile,"Private 8 bit word chnls 1-9 :%x\n",
853  &N_Pword);
854  fscanf(infile,"Private 8 bit word chnls 10-18:%x\n",
855  &NC_Pword);
856  fscanf(infile,"Private 8 bit word chnls 19-27:%x\n",
857  &SC_Pword);
858  fscanf(infile,"Private 8 bit word chnls 28-36:%x\n",
859  &S_Pword);
860  if(localDEBUG)
861  printf("Private 8 bit word chnls 1-9 :%x\n",N_Pword);
862  if(localDEBUG)
863  printf("Private 8 bit word chnls 10-18:%x\n",NC_Pword);
864  if(localDEBUG)
865  printf("Private 8 bit word chnls 19-27:%x\n",SC_Pword);
866  if(localDEBUG)
867  printf("Private 8 bit word chnls 28-36:%x\n",S_Pword);
868 
869  //These bit sets the special dac mode for random triggers
870  fscanf(infile,"Special Random testDAC mode (on = 0x1, off=0x0):%x\n",
871  &SpecialDac);
872  if(localDEBUG)
873  printf("Special Random testDAC mode (on = 0x1, off=0x0):%x\n",SpecialDac);
874 
875 
876  //These bits set the number of Out of consecutive out of sync events until a TTs OOs
877  fscanf(infile,"Number of Consecutive (max 1023) Out of Syncs till TTs OOS set:%d\n",
878  &Ooslvl);
879  if(localDEBUG)
880  printf("Number of Consecutive (max 1023) Out of Syncs till TTs OOS set:%d\n",Ooslvl);
881 
882  //These bits set the number of Empty events until a TTs Error
883  fscanf(infile,"Number of Consecutive (max 1023) Empty events till TTs ERR set:%d\n",
884  &Errlvl);
885  if(localDEBUG)
886  printf("Number of Consecutive (max 1023) Empty events till TTs ERR set:%d\n",Errlvl);
887 
888  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 N
889  fscanf(infile,"N Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n",
890  &Nfifo1Bzlvl);
891  if(localDEBUG)
892  printf("N Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n",Nfifo1Bzlvl);
893 
894  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 NC
895  fscanf(infile,"NC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n",
896  &NCfifo1Bzlvl);
897  if(localDEBUG)
898  printf("NC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n",NCfifo1Bzlvl);
899 
900  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 SC
901  fscanf(infile,"SC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n",
902  &SCfifo1Bzlvl);
903  if(localDEBUG)
904  printf("SC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n",SCfifo1Bzlvl);
905 
906  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 S
907  fscanf(infile,"S Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n",
908  &Sfifo1Bzlvl);
909  if(localDEBUG)
910  printf("S Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n",Sfifo1Bzlvl);
911 
912  //These bits set the Almost Full level in fifo-3, Almost full = TTs WARN in fifo-3
913  fscanf(infile,"Fifo-3 almost full level,sets TTs WARN (max 8191):%d\n",
914  &fifo3Wrnlvl);
915  if(localDEBUG)
916  printf("Fifo-3 almost full level,sets TTs WARN (max 8191):%d\n",fifo3Wrnlvl);
917 
918  fscanf(infile,"FED Master delay 0=0,1=32,2=48,3=64:%d\n",
919  &FedTTCDelay);
920  if(localDEBUG)
921  printf("FED Master delay 0=0,1=32,2=48,3=64:%d\n",FedTTCDelay);
922 
923  fscanf(infile,"TTCrx Register 0 fine delay ClkDes1:%d\n",&FineDes1Del);
924  if(localDEBUG)
925  printf("TTCrx Register 0 fine delay ClkDes1:%d\n",FineDes1Del);
926 
927  int checkword=0;
928  fscanf(infile,"Params FED file check word:%d\n",
929  &checkword);
930  if(checkword!=90508&&checkword!=91509&&checkword!=20211) cout << __LINE__ << "]\t" << mthn
931  << "FEDID: " << fedNumber
932  << " Params FED File read error. Checkword read " << checkword
933  <<" check word expected 090508 or 91509 or 20211" << endl;
934  assert((checkword==90508)|(checkword==91509)|(checkword==20211));
935 
936  if(localDEBUG)
937  cout << __LINE__ << "]\t" << mthn << "Params FED file check word: " << checkword << endl;
938 
939  //These bits set the hit limit in fifo-1 for an event
940 
941  if(checkword==20211){
942  //These bits set the hit limit in fifo-1 for an event
943  fscanf(infile,"N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",&N_hitlimit);
944  if(localDEBUG)
945  printf("N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",N_hitlimit);
946  fscanf(infile,"NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",&NC_hitlimit);
947  if(localDEBUG)
948  printf("NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",NC_hitlimit);
949  fscanf(infile,"SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",&SC_hitlimit);
950  if(localDEBUG)
951  printf("SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",SC_hitlimit);
952  fscanf(infile,"S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",&S_hitlimit);
953  if(localDEBUG)
954  printf("S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",S_hitlimit);
955  //These bits allow a ROC to be skipped (1/fpga)
956 
957  fscanf(infile,"Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",&N_testreg);
958  if(localDEBUG)
959  printf("Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",N_testreg);
960  fscanf(infile,"Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",&NC_testreg);
961  if(localDEBUG)
962  printf("Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",NC_testreg);
963  fscanf(infile,"Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",&SC_testreg);
964  if(localDEBUG)
965  printf("Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",SC_testreg);
966  fscanf(infile,"Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",&S_testreg);
967  if(localDEBUG)
968  printf("Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",S_testreg);
969 
970  fscanf(infile,"Set BUSYWHENBEHIND by this many triggers with timeouts:%d\n",&BusyWhenBehind);
971  if(localDEBUG)
972  printf("Set BUSYWHENBEHIND by this many triggers with timeouts:%d\n",BusyWhenBehind);
973 
974  fscanf(infile,"D[0]=1 enable fed-stuck reset D[1]=1 disable ev# protect(dont):%x\n",&FeatureRegister);
975  if(localDEBUG)
976  printf("D[0]=1 enable fed-stuck reset D[1]=1 disable ev# protect(dont):%x\n",FeatureRegister);
977 
978  fscanf(infile,"Limit for fifo-2 almost full (point for the TTS flag):%x\n",&FIFO2Limit);
979  if(localDEBUG)
980  printf("Limit for fifo-2 almost full (point for the TTS flag):%x\n",FIFO2Limit);
981 
982  fscanf(infile,"Limit for consecutive timeout OR OOSs:%d\n",&TimeoutOROOSLimit);
983  if(localDEBUG)
984  printf("Limit for consecutive timeout OR OOSs:%d\n",TimeoutOROOSLimit);
985 
986  fscanf(infile,"Turn off filling of lastdac fifos(exc 1st ROC):%d\n",&LastDacOff);
987  if(localDEBUG)
988  printf("Turn off filling of lastdac fifos(exc 1st ROC):%d\n",LastDacOff);
989 
990  fscanf(infile,"Number of simulated hits per ROC for internal generator:%d\n",&SimHitsPerRoc);
991  if(localDEBUG)
992  printf("Number of simulated hits per ROC for internal generator:%d\n",SimHitsPerRoc);
993 
994  fscanf(infile,"Miniumum hold time for busy (changing definition):%d\n",&BusyHoldMin);
995  if(localDEBUG)
996  printf("Miniumum hold time for busy (changing definition):%d\n",BusyHoldMin);
997 
998  fscanf(infile,"Trigger Holdoff in units of 25us(0=none):%d\n",&TriggerHoldoff);
999  if(localDEBUG)
1000  printf("Trigger Holdoff in units of 25us(0=none):%d\n",TriggerHoldoff);
1001 
1002  fscanf(infile,"Spare fedcard input 1:%d\n",&SPARE1);
1003  if(localDEBUG)
1004  printf("Spare fedcard input 1:%d\n",SPARE1);
1005  fscanf(infile,"Spare fedcard input 2:%d\n",&SPARE2);
1006  if(localDEBUG)
1007  printf("Spare fedcard input 2:%d\n",SPARE2);
1008  fscanf(infile,"Spare fedcard input 3:%d\n",&SPARE3);
1009  if(localDEBUG)
1010  printf("Spare fedcard input 3:%d\n",SPARE3);
1011  fscanf(infile,"Spare fedcard input 4:%d\n",&SPARE4);
1012  if(localDEBUG)
1013  printf("Spare fedcard input 4:%d\n",SPARE4);
1014  fscanf(infile,"Spare fedcard input 5:%d\n",&SPARE5);
1015  if(localDEBUG)
1016  printf("Spare fedcard input 5:%d\n",SPARE5);
1017  fscanf(infile,"Spare fedcard input 6:%d\n",&SPARE6);
1018  if(localDEBUG)
1019  printf("Spare fedcard input 6:%d\n",SPARE6);
1020  fscanf(infile,"Spare fedcard input 7:%d\n",&SPARE7);
1021  if(localDEBUG)
1022  printf("Spare fedcard input 7:%d\n",SPARE7);
1023  fscanf(infile,"Spare fedcard input 8:%d\n",&SPARE8);
1024  if(localDEBUG)
1025  printf("Spare fedcard input 8:%d\n",SPARE8);
1026  fscanf(infile,"Spare fedcard input 9:%d\n",&SPARE9);
1027  if(localDEBUG)
1028  printf("Spare fedcard input 9:%d\n",SPARE9);
1029  fscanf(infile,"Spare fedcard input 10:%d\n",&SPARE10);
1030  if(localDEBUG)
1031  printf("Spare fedcard input 10:%d\n",SPARE10);
1032 
1033 
1034 
1035  }else if(checkword==91509){
1036  //These bits set the hit limit in fifo-1 for an event
1037  fscanf(infile,"N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",&N_hitlimit);
1038  if(localDEBUG)
1039  printf("N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",N_hitlimit);
1040  fscanf(infile,"NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",&NC_hitlimit);
1041  if(localDEBUG)
1042  printf("NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",NC_hitlimit);
1043  fscanf(infile,"SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",&SC_hitlimit);
1044  if(localDEBUG)
1045  printf("SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",SC_hitlimit);
1046  fscanf(infile,"S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",&S_hitlimit);
1047  if(localDEBUG)
1048  printf("S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",S_hitlimit);
1049  //These bits allow a ROC to be skipped (1/fpga)
1050 
1051  fscanf(infile,"Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",&N_testreg);
1052  if(localDEBUG)
1053  printf("Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",N_testreg);
1054  fscanf(infile,"Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",&NC_testreg);
1055  if(localDEBUG)
1056  printf("Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",NC_testreg);
1057  fscanf(infile,"Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",&SC_testreg);
1058  if(localDEBUG)
1059  printf("Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",SC_testreg);
1060  fscanf(infile,"Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",&S_testreg);
1061  if(localDEBUG)
1062  printf("Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",S_testreg);
1063 
1064  BusyWhenBehind=8;
1065  FeatureRegister=0x1;
1066  FIFO2Limit=0x1C00;
1067  TimeoutOROOSLimit=200;
1068  LastDacOff=0;
1069  SimHitsPerRoc=0;
1070  BusyHoldMin=0;
1071  TriggerHoldoff=0;
1072  SPARE1=0;
1073  SPARE2=0;
1074  SPARE3=0;
1075  SPARE4=0;
1076  SPARE5=0;
1077  SPARE6=0;
1078  SPARE7=0;
1079  SPARE8=0;
1080  SPARE9=0;
1081  SPARE10=0;
1082 
1083  } else {
1084 
1085  N_hitlimit=192;
1086  NC_hitlimit=192;
1087  SC_hitlimit=192;
1088  S_hitlimit=192;
1089 
1090  N_testreg=0;
1091  NC_testreg=0;
1092  SC_testreg=0;
1093  S_testreg=0;
1094 
1095  BusyWhenBehind=8;
1096  FeatureRegister=0x1;
1097  FIFO2Limit=0x1c00;
1098  TimeoutOROOSLimit=200;
1099  LastDacOff=0;
1100  SimHitsPerRoc=0;
1101  BusyHoldMin=0;
1102  TriggerHoldoff=0;
1103  SPARE1=0;
1104  SPARE2=0;
1105  SPARE3=0;
1106  SPARE4=0;
1107  SPARE5=0;
1108  SPARE6=0;
1109  SPARE7=0;
1110  SPARE8=0;
1111  SPARE9=0;
1112  SPARE10=0; }
1113 
1114  fclose(infile);
1115 
1116  Ccntrl_original=Ccntrl;
1117  modeRegister_original=modeRegister;
1118 
1119 
1120  Ncntrl_original=Ncntrl;
1121  NCcntrl_original=NCcntrl;
1122  SCcntrl_original=SCcntrl;
1123  Scntrl_original=Scntrl;
1124 
1125  Nbaseln_original=Nbaseln;
1126  NCbaseln_original=NCbaseln;
1127  SCbaseln_original=SCbaseln;
1128  Sbaseln_original=Sbaseln;
1129 
1130  return;
1131 }
1132 
1133 //==================================================================================
1134 // Added by Dario (March 26th 2008)
1135 void PixelFEDCard::clear(void)
1136 {
1137  FEDBASE_0 = 0 ;
1138  fedNumber = 999 ;
1139  for(int i=0;i<36;i++){
1140  NRocs[i] = 0;
1141  offs_dac[i] = 0;
1142  BlackHi[i] = 0;
1143  BlackLo[i] = 0;
1144  Ublack[i] = 0;
1145  DelayCh[i] = 0;
1146  TBM_L0[i] = 0;
1147  TBM_L1[i] = 0;
1148  TBM_L2[i] = 0;
1149  TBM_L3[i] = 0;
1150  TBM_L4[i] = 0;
1151  TRL_L0[i] = 0;
1152  TRL_L1[i] = 0;
1153  TRL_L2[i] = 0;
1154  TRL_L3[i] = 0;
1155  TRL_L4[i] = 0;
1156  }
1157  for(int i=0;i<3;i++){
1158  opt_cap[i] = 0;
1159  opt_inadj[i] = 0;
1160  opt_ouadj[i] = 0;
1161  }
1162  clkphs1_9 = 0;
1163  clkphs10_18 = 0;
1164  clkphs19_27 = 0;
1165  clkphs28_36 = 0;
1166 
1167  for(int i=0;i<36;i++) {
1168  for(int j=0;j<26;j++) {
1169  ROC_L0[i][j] = 0;
1170  ROC_L1[i][j] = 0;
1171  ROC_L2[i][j] = 0;
1172  ROC_L3[i][j] = 0;
1173  ROC_L4[i][j] = 0;
1174  }
1175  }
1176  Ncntrl = 0;
1177  NCcntrl = 0;
1178  SCcntrl = 0;
1179  Scntrl = 0;
1180  CoarseDel = 0;
1181  ClkDes2 = 0;
1182  FineDes2Del = 0;
1183  FineDes1Del = 0;
1184  Ccntrl = 0;
1185  modeRegister = 0;
1186  Nadcg = 0;
1187  NCadcg = 0;
1188  SCadcg = 0;
1189  Sadcg = 0;
1190  Nbaseln = 0;
1191  NCbaseln = 0;
1192  SCbaseln = 0;
1193  Sbaseln = 0;
1194  N_TBMmask = 0;
1195  NC_TBMmask = 0;
1196  SC_TBMmask = 0;
1197  S_TBMmask = 0;
1198  N_Pword = 0;
1199  NC_Pword = 0;
1200  SC_Pword = 0;
1201  S_Pword = 0;
1202  SpecialDac = 0;
1203  Ooslvl = 0;
1204  Errlvl = 0;
1205  Nfifo1Bzlvl = 0;
1206  NCfifo1Bzlvl = 0;
1207  SCfifo1Bzlvl = 0;
1208  Sfifo1Bzlvl = 0;
1209  fifo3Wrnlvl = 0;
1210 
1211  BusyHoldMin = 0;
1212  BusyWhenBehind = 0;
1213  FeatureRegister = 0;
1214  FIFO2Limit = 0;
1215  LastDacOff = 0;
1216  SimHitsPerRoc = 0;
1217  TimeoutOROOSLimit = 0;
1218  TriggerHoldoff = 0;
1219 
1220  SPARE1 = 0;
1221  SPARE2 = 0;
1222  SPARE3 = 0;
1223  SPARE4 = 0;
1224  SPARE5 = 0;
1225  SPARE6 = 0;
1226  SPARE7 = 0;
1227  SPARE8 = 0;
1228  SPARE9 = 0;
1229  SPARE10 = 0;
1230 }
1231 //==================================================================================
1232 
1233 void PixelFEDCard::writeASCII(std::string dir) const{
1234 
1235  std::string mthn = "[PixelFEDCard::writeASCII()]\t\t\t\t " ;
1236 
1237  ostringstream s1;
1238  s1<<fedNumber;
1239  std::string fedNum=s1.str();
1240 
1241  if (dir!="") dir+="/";
1242 
1243  std::string filename=dir+"params_fed_"+fedNum+".dat";
1244 
1245  FILE *outfile = fopen((filename.c_str()),"w");
1246  if (outfile == nullptr) {
1247  cout<< __LINE__ << "]\t" << mthn << "Could not open file: " << filename << " for writing" << endl;
1248  return;
1249  }
1250 
1251  //Fed Base Address
1252  fprintf(outfile,"FED Base address :0x%lx\n",
1253  FEDBASE_0);
1254  fprintf(outfile,"FEDID Number :0x%lx\n",
1255  fedNumber);
1256 
1257  // Number of ROCs
1258  int ijx=0;
1259  for(int i=0;i<36;i++){
1260  ijx=i+1;
1261  fprintf(outfile,"Number of ROCs Chnl %d:%d\n",ijx,NRocs[i]);
1262 }
1263 
1264  //Settable optical input parameters
1265  fprintf(outfile,"Optical reciever 1 Capacitor Adjust(0-3):%d\n",opt_cap[0]);
1266  fprintf(outfile,"Optical reciever 2 Capacitor Adjust(0-3):%d\n",opt_cap[1]);
1267  fprintf(outfile,"Optical reciever 3 Capacitor Adjust(0-3):%d\n",opt_cap[2]);
1268  fprintf(outfile,"Optical reciever 1 Input Offset (0-15) :%d\n",opt_inadj[0]);
1269  fprintf(outfile,"Optical reciever 2 Input Offset (0-15) :%d\n",opt_inadj[1]);
1270  fprintf(outfile,"Optical reciever 3 Input Offset (0-15) :%d\n",opt_inadj[2]);
1271  fprintf(outfile,"Optical reciever 1 Output Offset (0-3) :%d\n",opt_ouadj[0]);
1272  fprintf(outfile,"Optical reciever 2 Output Offset (0-3) :%d\n",opt_ouadj[1]);
1273  fprintf(outfile,"Optical reciever 3 Output Offset (0-3) :%d\n",opt_ouadj[2]);
1274 
1275  //input offset dac
1276  for(int i=0;i<36;i++) {
1277  fprintf(outfile,"Offset DAC channel %d:%d\n",i+1,offs_dac[i]);
1278  }
1279 
1280  //clock phases
1281  fprintf(outfile,"Clock Phase Bits ch 1-9:0x%x\n",clkphs1_9 );
1282  fprintf(outfile,"Clock Phase Bits ch 10-18:0x%x\n",clkphs10_18);
1283  fprintf(outfile,"Clock Phase Bits ch 19-27:0x%x\n",clkphs19_27);
1284  fprintf(outfile,"Clock Phase Bits ch 28-36:0x%x\n",clkphs28_36);
1285 
1286  //Blacks
1287  for(int i=0;i<36;i++){
1288  fprintf(outfile,"Black HiThold ch %d:%d \n",i+1,BlackHi[i]);
1289  fprintf(outfile,"Black LoThold ch %d:%d \n",i+1,BlackLo[i]);
1290  fprintf(outfile,"ULblack Thold ch %d:%d \n",i+1,Ublack[i]);
1291  }
1292 
1293  //Channel delays
1294  for(int i=0;i<36;i++) {
1295  fprintf(outfile,"Delay channel %d(0-15):%d\n",i+1,DelayCh[i]);
1296  }
1297 
1298  //Signal levels
1299  for(int i=0;i<36;i++) {
1300  fprintf(outfile,"TBM level 0 Channel %d:%d\n",i+1,TBM_L0[i]);
1301  fprintf(outfile,"TBM level 1 Channel %d:%d\n",i+1,TBM_L1[i]);
1302  fprintf(outfile,"TBM level 2 Channel %d:%d\n",i+1,TBM_L2[i]);
1303  fprintf(outfile,"TBM level 3 Channel %d:%d\n",i+1,TBM_L3[i]);
1304  fprintf(outfile,"TBM level 4 Channel %d:%d\n",i+1,TBM_L4[i]);
1305 
1306  for(int j=0;j<NRocs[i];j++) {
1307  fprintf(outfile,"ROC%d level 0 Channel %d :%d\n",
1308  j,i+1,ROC_L0[i][j]);
1309  fprintf(outfile,"ROC%d level 1 Channel %d :%d\n",
1310  j,i+1,ROC_L1[i][j]);
1311  fprintf(outfile,"ROC%d level 2 Channel %d :%d\n",
1312  j,i+1,ROC_L2[i][j]);
1313  fprintf(outfile,"ROC%d level 3 Channel %d :%d\n",
1314  j,i+1,ROC_L3[i][j]);
1315  fprintf(outfile,"ROC%d level 4 Channel %d :%d\n",
1316  j,i+1,ROC_L4[i][j]);
1317  }
1318 
1319  fprintf(outfile,"TRLR level 0 Channel %d:%d\n",i+1,TRL_L0[i]);
1320  fprintf(outfile,"TRLR level 1 Channel %d:%d\n",i+1,TRL_L1[i]);
1321  fprintf(outfile,"TRLR level 2 Channel %d:%d\n",i+1,TRL_L2[i]);
1322  fprintf(outfile,"TRLR level 3 Channel %d:%d\n",i+1,TRL_L3[i]);
1323  fprintf(outfile,"TRLR level 4 Channel %d:%d\n",i+1,TRL_L4[i]);
1324  }
1325 
1326 
1327  //These bits turn off(1) and on(0) channels
1328  fprintf(outfile,"Channel Enbable bits chnls 1-9 (on = 0):0x%x\n",
1329  Ncntrl);
1330  fprintf(outfile,"Channel Enbable bits chnls 10-18(on = 0):0x%x\n",
1331  NCcntrl);
1332  fprintf(outfile,"Channel Enbable bits chnls 19-27(on = 0):0x%x\n",
1333  SCcntrl);
1334  fprintf(outfile,"Channel Enbable bits chnls 28-36(on = 0):0x%x\n",
1335  Scntrl);
1336 
1337  //These are delays to the TTCrx
1338  fprintf(outfile,"TTCrx Coarse Delay Register 2:%d\n",CoarseDel);
1339  fprintf(outfile,"TTCrc ClkDes2 Register 3:0x%x\n",ClkDes2);
1340  fprintf(outfile,"TTCrc Fine Dlay ClkDes2 Reg 1:%d\n",FineDes2Del);
1341 
1342  // Control register
1343  fprintf(outfile,"Center Chip Control Reg:0x%x\n",Ccntrl);
1344  fprintf(outfile,"Initial Slink DAQ mode:%d\n",modeRegister);
1345 
1346  //These bits set ADC Gain/Range 1Vpp(0) and 2Vpp(1) for channels
1347  fprintf(outfile,"Channel ADC Gain bits chnls 1-12(1Vpp = 0):0x%x\n",
1348  Nadcg);
1349  fprintf(outfile,"Channel ADC Gain bits chnls 13-20(1Vpp = 0):0x%x\n",
1350  NCadcg);
1351  fprintf(outfile,"Channel ADC Gain bits chnls 21-28(1Vpp = 0):0x%x\n",
1352  SCadcg);
1353  fprintf(outfile,"Channel ADC Gain bits chnls 29-36(1Vpp = 0):0x%x\n",
1354  Sadcg);
1355 
1356  //These bits set Baseline adjustment value (common by FPGA)//can turn on by channel
1357  fprintf(outfile,"Channel Baseline Enbable chnls 1-9 (on = (0x1ff<<16)+):0x%x\n",
1358  Nbaseln);
1359  fprintf(outfile,"Channel Baseline Enbable chnls 10-18(on = (0x1ff<<16)+):0x%x\n",
1360  NCbaseln);
1361  fprintf(outfile,"Channel Baseline Enbable chnls 19-27(on = (0x1ff<<16)+):0x%x\n",
1362  SCbaseln);
1363  fprintf(outfile,"Channel Baseline Enbable chnls 28-36(on = (0x1ff<<16)+):0x%x\n",
1364  Sbaseln);
1365 
1366  //These bits set TBM trailer mask (common by FPGA)
1367  fprintf(outfile,"TBM trailer mask chnls 1-9 (0xff = all masked):0x%x\n",
1368  N_TBMmask);
1369  fprintf(outfile,"TBM trailer mask chnls 10-18(0xff = all masked):0x%x\n",
1370  NC_TBMmask);
1371  fprintf(outfile,"TBM trailer mask chnls 19-27(0xff = all masked):0x%x\n",
1372  SC_TBMmask);
1373  fprintf(outfile,"TBM trailer mask chnls 28-36(0xff = all masked):0x%x\n",
1374  S_TBMmask);
1375 
1376  //These bits set the Private fill/gap word value (common by FPGA)
1377  fprintf(outfile,"Private 8 bit word chnls 1-9 :0x%x\n",
1378  N_Pword);
1379  fprintf(outfile,"Private 8 bit word chnls 10-18:0x%x\n",
1380  NC_Pword);
1381  fprintf(outfile,"Private 8 bit word chnls 19-27:0x%x\n",
1382  SC_Pword);
1383  fprintf(outfile,"Private 8 bit word chnls 28-36:0x%x\n",
1384  S_Pword);
1385 
1386  //These bit sets the special dac mode for random triggers
1387  fprintf(outfile,"Special Random testDAC mode (on = 0x1, off=0x0):0x%x\n",
1388  SpecialDac);
1389 
1390  //These bits set the number of Out of consecutive out of sync events until a TTs OOs
1391  fprintf(outfile,"Number of Consecutive (max 1023) Out of Syncs till TTs OOS set:%d\n",
1392  Ooslvl);
1393 
1394  //These bits set the number of Empty events until a TTs Error
1395  fprintf(outfile,"Number of Consecutive (max 1023) Empty events till TTs ERR set:%d\n",
1396  Errlvl);
1397 
1398  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 N
1399  fprintf(outfile,"N Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n",
1400  Nfifo1Bzlvl);
1401 
1402  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 NC
1403  fprintf(outfile,"NC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n",
1404  NCfifo1Bzlvl);
1405 
1406  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 SC
1407  fprintf(outfile,"SC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n",
1408  SCfifo1Bzlvl);
1409 
1410  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 S
1411  fprintf(outfile,"S Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n",
1412  Sfifo1Bzlvl);
1413 
1414  //These bits set the Almost Full level in fifo-3, Almost full = TTs WARN in fifo-3
1415  fprintf(outfile,"Fifo-3 almost full level,sets TTs WARN (max 8191):%d\n",
1416  fifo3Wrnlvl);
1417 
1418  fprintf(outfile,"FED Master delay 0=0,1=32,2=48,3=64:%d\n",
1419  FedTTCDelay);
1420 
1421  fprintf(outfile,"TTCrx Register 0 fine delay ClkDes1:%d\n",
1422  FineDes1Del);
1423 
1424  int checkword=20211;
1425 
1426  fprintf(outfile,"Params FED file check word:%d\n",
1427  checkword);
1428 
1429 
1430  //These bits set the hit limit in fifo-1 for an event
1431  fprintf(outfile,"N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1432  N_hitlimit); //ch 1-9
1433 
1434  fprintf(outfile,"NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1435  NC_hitlimit); //ch 10-18
1436 
1437  fprintf(outfile,"SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1438  SC_hitlimit); //ch 19-27
1439 
1440  fprintf(outfile,"S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1441  S_hitlimit); //ch 28-36
1442 
1443 
1444  //These bits allow a ROC to be skipped (1/fpga)
1445  fprintf(outfile,"Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",
1446  N_testreg);
1447 
1448  fprintf(outfile,"Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",
1449  NC_testreg);
1450 
1451  fprintf(outfile,"Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",
1452  SC_testreg);
1453 
1454  fprintf(outfile,"Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n",
1455  S_testreg);
1456 
1457  fprintf(outfile,"Set BUSYWHENBEHIND by this many triggers with timeouts:%d\n",
1458  BusyWhenBehind);
1459 
1460  fprintf(outfile,"D[0]=1 enable fed-stuck reset D[1]=1 disable ev# protect(dont):0x%x\n",
1461  FeatureRegister);
1462 
1463  fprintf(outfile,"Limit for fifo-2 almost full (point for the TTS flag):0x%x\n",
1464  FIFO2Limit);
1465 
1466  fprintf(outfile,"Limit for consecutive timeout OR OOSs:%d\n",
1467  TimeoutOROOSLimit);
1468 
1469  fprintf(outfile,"Turn off filling of lastdac fifos(exc 1st ROC):%d\n",
1470  LastDacOff);
1471 
1472  fprintf(outfile,"Number of simulated hits per ROC for internal generator:%d\n",
1473  SimHitsPerRoc);
1474 
1475  fprintf(outfile,"Miniumum hold time for busy (changing definition):%d\n",
1476  BusyHoldMin);
1477 
1478  fprintf(outfile,"Trigger Holdoff in units of 25us(0=none):%d\n",
1479  TriggerHoldoff);
1480 
1481  fprintf(outfile,"Spare fedcard input 1:%d\n",SPARE1);
1482  fprintf(outfile,"Spare fedcard input 2:%d\n",SPARE2);
1483  fprintf(outfile,"Spare fedcard input 3:%d\n",SPARE3);
1484  fprintf(outfile,"Spare fedcard input 4:%d\n",SPARE4);
1485  fprintf(outfile,"Spare fedcard input 5:%d\n",SPARE5);
1486  fprintf(outfile,"Spare fedcard input 6:%d\n",SPARE6);
1487  fprintf(outfile,"Spare fedcard input 7:%d\n",SPARE7);
1488  fprintf(outfile,"Spare fedcard input 8:%d\n",SPARE8);
1489  fprintf(outfile,"Spare fedcard input 9:%d\n",SPARE9);
1490  fprintf(outfile,"Spare fedcard input 10:%d\n",SPARE10);
1491 
1492 
1493 
1494  fclose(outfile);
1495 
1496 
1497 }
1498 
1499 
1500 //=============================================================================================
1501 void PixelFEDCard::writeXMLHeader(pos::PixelConfigKey key,
1502  int version,
1503  std::string path,
1504  std::ofstream *fedstream,
1505  std::ofstream *rocstream,
1506  std::ofstream *tbmstream) const
1507 {
1508  std::string mthn = "[PixelFEDCard::writeXMLHeader()]\t\t\t " ;
1509  std::stringstream fedfullPath ;
1510  std::stringstream rocfullPath ;
1511  std::stringstream tbmfullPath ;
1512 
1513  // modified by MR on 05-08-2008 16:50:28
1514  // FED MAIN XML FILE
1515  fedfullPath << path << "/FedConfiguration_Template_" << PixelTimeFormatter::getmSecTime() << ".xml" ;
1516  std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << fedfullPath.str() << "" << std::endl ;
1517 
1518  fedstream->open(fedfullPath.str().c_str()) ;
1519 
1520  *fedstream << "<?xml version='1.0' encoding='UTF-8' standalone='yes'?>" << std::endl ;
1521  *fedstream << "<ROOT xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'>" << std::endl ;
1522  *fedstream << "" << std::endl ;
1523  *fedstream << " <HEADER>" << std::endl ;
1524  *fedstream << " <HINTS mode='load-as-group' /> " << std::endl ;
1525  *fedstream << " <TYPE>" << std::endl ;
1526  *fedstream << " <EXTENSION_TABLE_NAME>FED_CONFIGURATION</EXTENSION_TABLE_NAME>" << std::endl ;
1527  *fedstream << " <NAME>Pixel FED Configuration</NAME>" << std::endl ;
1528  *fedstream << " </TYPE>" << std::endl ;
1529  *fedstream << " <RUN>" << std::endl ;
1530  *fedstream << " <RUN_TYPE>Pixel FED Configuration</RUN_TYPE>" << std::endl ;
1531  *fedstream << " <RUN_NUMBER>1</RUN_NUMBER>" << std::endl ;
1532  *fedstream << " <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl ;
1533  *fedstream << " <LOCATION>CERN P5</LOCATION>" << std::endl ;
1534  *fedstream << " </RUN>" << std::endl ;
1535  *fedstream << " </HEADER>" << std::endl ;
1536  *fedstream << "" << std::endl ;
1537  *fedstream << " <DATA_SET>" << std::endl ;
1538  *fedstream << "" << std::endl ;
1539  *fedstream << " <VERSION>" << version << "</VERSION>" << std::endl ;
1540  *fedstream << " <COMMENT_DESCRIPTION>" << getComment() << "</COMMENT_DESCRIPTION>" << std::endl ;
1541  *fedstream << " <CREATED_BY_USER>" << getAuthor() << "</CREATED_BY_USER>" << std::endl ;
1542  *fedstream << "" << std::endl ;
1543  *fedstream << " <PART>" << std::endl ;
1544  *fedstream << " <NAME_LABEL>CMS-PIXEL-ROOT</NAME_LABEL>" << std::endl ;
1545  *fedstream << " <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl ;
1546  *fedstream << " </PART>" << std::endl ;
1547 
1548  // ROC LEVELS MAIN XML FILE
1549  rocfullPath << path << "/Pixel_RocAnalogLevels_" << PixelTimeFormatter::getmSecTime() << ".xml" ;
1550  std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << rocfullPath.str() << "" << std::endl ;
1551 
1552  rocstream->open(rocfullPath.str().c_str()) ;
1553 
1554 
1555  *rocstream << "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"yes\"?>" << std::endl ;
1556  *rocstream << "<ROOT xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\">" << std::endl ;
1557  *rocstream << "" << std::endl ;
1558  *rocstream << " <HEADER>" << std::endl ;
1559  *rocstream << " <HINTS mode='only-det-root,load-as-group'/>" << std::endl ;
1560  *rocstream << " <TYPE>" << std::endl ;
1561  *rocstream << " <EXTENSION_TABLE_NAME>ROC_ANALOG_LEVELS</EXTENSION_TABLE_NAME>" << std::endl ;
1562  *rocstream << " <NAME>ROC Analog Levels</NAME>" << std::endl ;
1563  *rocstream << " </TYPE>" << std::endl ;
1564  *rocstream << " <RUN>" << std::endl ;
1565  *rocstream << " <RUN_TYPE>ROC Analog Levels</RUN_TYPE>" << std::endl ;
1566  *rocstream << " <RUN_NUMBER>1</RUN_NUMBER> " << std::endl ;
1567  *rocstream << " <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl ;
1568  *rocstream << " <CREATED_BY_USER>Umesh Joshi</CREATED_BY_USER> " << std::endl ;
1569  *rocstream << " <LOCATION>CERN</LOCATION> " << std::endl ;
1570  *rocstream << " <COMMENT_DESCRIPTION>ROC Analog Levels Template</COMMENT_DESCRIPTION>" << std::endl ;
1571  *rocstream << " </RUN>" << std::endl ;
1572  *rocstream << " </HEADER>" << std::endl ;
1573  *rocstream << "" << std::endl ;
1574  *rocstream << " <DATA_SET>" << std::endl ;
1575  *rocstream << " <COMMENT_DESCRIPTION>ROC Analog Levels Template</COMMENT_DESCRIPTION>" << std::endl ;
1576  *rocstream << " <VERSION>" << version << "</VERSION>" << std::endl ;
1577  *rocstream << " " << std::endl ;
1578  *rocstream << " <PART>" << std::endl ;
1579  *rocstream << " <SERIAL_NUMBER>CMS-PIXEL-ROOT</SERIAL_NUMBER>" << std::endl ;
1580  *rocstream << " <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl ;
1581  *rocstream << " </PART>" << std::endl ;
1582 
1583  // TBM LEVELS MAIN XML FILE
1584  tbmfullPath << path << "/Pixel_TbmAnalogLevels_" << PixelTimeFormatter::getmSecTime() << ".xml" ;
1585  std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << tbmfullPath.str() << "" << std::endl ;
1586 
1587  tbmstream->open(tbmfullPath.str().c_str()) ;
1588 
1589 
1590  *tbmstream << "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"yes\"?>" << std::endl ;
1591  *tbmstream << "<ROOT xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\">" << std::endl ;
1592  *tbmstream << "" << std::endl ;
1593  *tbmstream << " <HEADER>" << std::endl ;
1594  *tbmstream << " <HINTS mode='only-det-root,load-as-group' />" << std::endl ;
1595  *tbmstream << " <TYPE>" << std::endl ;
1596  *tbmstream << " <EXTENSION_TABLE_NAME>TBM_ANALOG_LEVELS</EXTENSION_TABLE_NAME>" << std::endl ;
1597  *tbmstream << " <NAME>TBM Analog Levels</NAME>" << std::endl ;
1598  *tbmstream << " </TYPE>" << std::endl ;
1599  *tbmstream << " <RUN>" << std::endl ;
1600  *tbmstream << " <RUN_TYPE>TBM Analog Levels</RUN_TYPE>" << std::endl ;
1601  *tbmstream << " <RUN_NUMBER>1</RUN_NUMBER>" << std::endl ;
1602  *tbmstream << " <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl ;
1603  *tbmstream << " <CREATED_BY_USER>Umesh Joshi</CREATED_BY_USER> " << std::endl ;
1604  *tbmstream << " <LOCATION>CERN</LOCATION> " << std::endl ;
1605  *tbmstream << " <COMMENT_DESCRIPTION>TBM Analog Levels</COMMENT_DESCRIPTION>" << std::endl ;
1606  *tbmstream << " </RUN>" << std::endl ;
1607  *tbmstream << " </HEADER>" << std::endl ;
1608  *tbmstream << "" << std::endl ;
1609  *tbmstream << " <DATA_SET>" << std::endl ;
1610  *tbmstream << " <VERSION>" << version << "</VERSION>" << std::endl ;
1611  *tbmstream << " " << std::endl ;
1612  *tbmstream << " <PART>" << std::endl ;
1613  *tbmstream << " <SERIAL_NUMBER>CMS-PIXEL-ROOT</SERIAL_NUMBER>" << std::endl ;
1614  *tbmstream << " <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl ;
1615  *tbmstream << " </PART>" << std::endl ;
1616 
1617 }
1618 
1619 //=============================================================================================
1620 void PixelFEDCard::writeXMLHeader(pos::PixelConfigKey key, int version, std::string path, std::ofstream *out) const {
1621  std::string mthn = "[PixelFEDCard::writeXMLHeader()]\t\t\t " ;
1622  std::stringstream fullPath ;
1623 
1624  fullPath << path << "/fedcard_" << PixelTimeFormatter::getmSecTime() << ".xml" ;
1625  std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << fullPath.str() << "" << std::endl ;
1626 
1627  out->open(fullPath.str().c_str()) ;
1628 
1629  *out << "<?xml version='1.0' encoding='UTF-8' standalone='yes'?>" << std::endl ;
1630  *out << "<ROOT>" << std::endl ;
1631  *out << "" << std::endl ;
1632  *out << " <HEADER>" << std::endl ;
1633  *out << " <TYPE>" << std::endl ;
1634  *out << " <EXTENSION_TABLE_NAME>FED_CONFIGURATION</EXTENSION_TABLE_NAME>" << std::endl ;
1635  *out << " <NAME>Pixel FED Configuration</NAME>" << std::endl ;
1636  *out << " </TYPE>" << std::endl ;
1637  *out << " <RUN>" << std::endl ;
1638  *out << " <RUN_TYPE>Pixel FED Configuration</RUN_TYPE>" << std::endl ;
1639  *out << " <RUN_NUMBER>1</RUN_NUMBER>" << std::endl ;
1640  *out << " <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl ;
1641  *out << " <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl ;
1642  *out << " <LOCATION>CERN TAC</LOCATION>" << std::endl ;
1643  *out << " <CREATED_BY_USER>Dario Menasce</CREATED_BY_USER>" << std::endl ;
1644  *out << " </RUN>" << std::endl ;
1645  *out << " </HEADER>" << std::endl ;
1646  *out << "" << std::endl ;
1647  *out << " <DATA_SET>" << std::endl ;
1648  *out << "" << std::endl ;
1649  *out << " <VERSION>" << version << "</VERSION>" << std::endl ;
1650  *out << " <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl ;
1651  *out << "" << std::endl ;
1652  *out << " <PART>" << std::endl ;
1653  *out << " <NAME_LABEL>CMS-PIXEL-ROOT</NAME_LABEL>" << std::endl ;
1654  *out << " <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl ;
1655  *out << " </PART>" << std::endl ;
1656 }
1657 //=============================================================================================
1658 void PixelFEDCard::writeXML( std::ofstream *out) const
1659 {
1660  std::string mthn = "[PixelFEDCard::writeXML()]\t\t\t " ;
1661 
1662  *out << " <DATA>" << std::endl ;
1663  *out << " " << std::endl ;
1664  *out << " <PXLFED_NAME>PxlFED_" << fedNumber<< "</PXLFED_NAME>" << std::endl ;
1665  *out << " <VME_ADDRESS>268435456</VME_ADDRESS>" << std::endl ;
1666 // *out << " <CRATE_NUMBER>1</CRATE_NUMBER>" << std::endl ;
1667 // *out << " <SLOT_NUMBER>5</SLOT_NUMBER> " << std::endl ;
1668 // *out << " <VME_ADDRESS>268435456</VME_ADDRESS>" << std::endl ;
1669 // *out << " <CRATE_LABEL>S1G03e</CRATE_LABEL>" << std::endl ;
1670  *out << "" << std::endl ;
1671  *out << " <CHANNEL_ID>1</CHANNEL_ID>" << std::endl ;
1672  *out << " <NUMBER_OF_ROCS>21</NUMBER_OF_ROCS>" << std::endl ;
1673  *out << " <CHANNEL_OFFSET_DAC_SETTINGS>0</CHANNEL_OFFSET_DAC_SETTINGS>" << std::endl ;
1674  *out << " <CHANNEL_DELAY_SETTINGS>3</CHANNEL_DELAY_SETTINGS>" << std::endl ;
1675  *out << " <CHANNEL_BLACK_HIGH>400</CHANNEL_BLACK_HIGH>" << std::endl ;
1676  *out << " <CHANNEL_BLACK_LOW>150</CHANNEL_BLACK_LOW>" << std::endl ;
1677  *out << " <CHANNEL_ULTRA_BLACK>120</CHANNEL_ULTRA_BLACK>" << std::endl ;
1678  *out << "" << std::endl ;
1679  *out << " <OPT1_CAP>0</OPT1_CAP>" << std::endl ;
1680  *out << " <OPT2_CAP>0</OPT2_CAP>" << std::endl ;
1681  *out << " <OPT3_CAP>0</OPT3_CAP>" << std::endl ;
1682  *out << " <OPT1_INP>0</OPT1_INP>" << std::endl ;
1683  *out << " <OPT2_INP>0</OPT2_INP>" << std::endl ;
1684  *out << " <OPT3_INP>0</OPT3_INP>" << std::endl ;
1685  *out << " <OPT1_OUT>0</OPT1_OUT>" << std::endl ;
1686  *out << " <OPT2_OUT>0</OPT2_OUT>" << std::endl ;
1687  *out << " <OPT3_OUT>0</OPT3_OUT>" << std::endl ;
1688  *out << " <NORTH_CLKPHB>511</NORTH_CLKPHB>" << std::endl ;
1689  *out << " <NORTHCENTER_CLKPHB>511</NORTHCENTER_CLKPHB>" << std::endl ;
1690  *out << " <SOUTHCENTER_CLKPHB>511</SOUTHCENTER_CLKPHB>" << std::endl ;
1691  *out << " <SOUTH_CLKPHB>511</SOUTH_CLKPHB>" << std::endl ;
1692  *out << " <NORTH_CTRL>0</NORTH_CTRL> " << std::endl ;
1693  *out << " <NORTHCENTER_CTRL>0</NORTHCENTER_CTRL>" << std::endl ;
1694  *out << " <SOUTHCENTER_CTRL>0</SOUTHCENTER_CTRL>" << std::endl ;
1695  *out << " <SOUTH_CTRL>0</SOUTH_CTRL>" << std::endl ;
1696  *out << " <REG1_TTCRX_FDLA>5</REG1_TTCRX_FDLA>" << std::endl ;
1697  *out << " <REG2_TTCRX_CDLA>0</REG2_TTCRX_CDLA>" << std::endl ;
1698  *out << " <REG3_TTCRX_CLKD2>155</REG3_TTCRX_CLKD2>" << std::endl ;
1699  *out << " <CENTER_CTRL>0</CENTER_CTRL>" << std::endl ;
1700  *out << " <CENTER_MODE>0</CENTER_MODE>" << std::endl ;
1701  *out << " <B1_ADCGN>0</B1_ADCGN>" << std::endl ;
1702  *out << " <B2_ADCGN>0</B2_ADCGN>" << std::endl ;
1703  *out << " <B3_ADCGN>0</B3_ADCGN>" << std::endl ;
1704  *out << " <B4_ADCGN>0</B4_ADCGN>" << std::endl ;
1705  *out << " <NORTH_BADJ>330</NORTH_BADJ>" << std::endl ;
1706  *out << " <NORTHCENTER_BADJ>330</NORTHCENTER_BADJ>" << std::endl ;
1707  *out << " <SOUTHCENTER_BADJ>330</SOUTHCENTER_BADJ>" << std::endl ;
1708  *out << " <SOUTH_BADJ>330</SOUTH_BADJ>" << std::endl ;
1709  *out << " <NORTH_TBMMASK>2</NORTH_TBMMASK>" << std::endl ;
1710  *out << " <NORTHCENTER_TBMMASK>2</NORTHCENTER_TBMMASK>" << std::endl ;
1711  *out << " <SOUTHCENTER_TBMMASK>2</SOUTHCENTER_TBMMASK>" << std::endl ;
1712  *out << " <SOUTH_TBMMASK>2</SOUTH_TBMMASK>" << std::endl ;
1713  *out << " <NORTH_PWORD>177</NORTH_PWORD>" << std::endl ;
1714  *out << " <NORTHCENTER_PWORD>178</NORTHCENTER_PWORD>" << std::endl ;
1715  *out << " <SOUTHCENTER_PWORD>179</SOUTHCENTER_PWORD>" << std::endl ;
1716  *out << " <SOUTH_PWORD>180</SOUTH_PWORD>" << std::endl ;
1717  *out << " <SPECDAC>0</SPECDAC>" << std::endl ;
1718  *out << " <OOS_LVL>0</OOS_LVL>" << std::endl ;
1719  *out << " <ERR_LVL>0</ERR_LVL>" << std::endl ;
1720  *out << " <NORTH_FIFO1_BZ_LVL>900</NORTH_FIFO1_BZ_LVL>" << std::endl ;
1721  *out << " <NORTHCENTER_FIFO1_BZ_LVL>900</NORTHCENTER_FIFO1_BZ_LVL>" << std::endl ;
1722  *out << " <SOUTHCENTER_FIFO1_BZ_LVL>900</SOUTHCENTER_FIFO1_BZ_LVL>" << std::endl ;
1723  *out << " <SOUTH_FIFO1_BZ_LVL>900</SOUTH_FIFO1_BZ_LVL>" << std::endl ;
1724  *out << " <FIFO3_WRN_LVL>7680</FIFO3_WRN_LVL> " << std::endl ;
1725  *out << " <FED_MASTER_DELAY>0</FED_MASTER_DELAY>" << std::endl ;
1726  *out << " <NO_HITLIMIT>0</NO_HITLIMIT>" << std::endl ;
1727  *out << " <NC_HITLIMIT>0</NC_HITLIMIT>" << std::endl ;
1728  *out << " <SC_HITLIMIT>0</SC_HITLIMIT>" << std::endl ;
1729  *out << " <SO_HITLIMIT>0</SO_HITLIMIT>" << std::endl ;
1730  *out << " <NO_TESTREG>0</NO_TESTREG>" << std::endl ;
1731  *out << " <NC_TESTREG>0</NC_TESTREG>" << std::endl ;
1732  *out << " <SC_TESTREG>0</SC_TESTREG>" << std::endl ;
1733  *out << " <SO_TESTREG>0</SO_TESTREG>" << std::endl ;
1734  *out << " <BUSYWHENBEHIND>4</BUSYWHENBEHIND>" << std::endl ;
1735  *out << " <FEATUREREGISTER>0X1234</FEATUREREGISTER>" << std::endl ;
1736  *out << " <FIFO2LIMIT>0X1C00</FIFO2LIMIT>" << std::endl ;
1737  *out << " <TIMEOUTOROOSLIMIT>0</TIMEOUTOROOSLIMIT>" << std::endl ;
1738  *out << " <LASTDACOFF>0</LASTDACOFF>" << std::endl ;
1739  *out << " <SIMHITSPERROC>0</SIMHITSPERROC>" << std::endl ;
1740  *out << " <BUSYHOLDMIN>0</BUSYHOLDMIN>" << std::endl ;
1741  *out << " <SPARE1>0</SPARE1>" << std::endl ;
1742  *out << " <SPARE2>0</SPARE2>" << std::endl ;
1743  *out << " <SPARE3>0</SPARE3>" << std::endl ;
1744  *out << " <SPARE4>0</SPARE4>" << std::endl ;
1745  *out << " <SPARE5>0</SPARE5>" << std::endl ;
1746  *out << " <SPARE6>0</SPARE6>" << std::endl ;
1747  *out << " <SPARE7>0</SPARE7>" << std::endl ;
1748  *out << " <SPARE8>0</SPARE8>" << std::endl ;
1749  *out << " <SPARE9>0</SPARE9>" << std::endl ;
1750  *out << " <SPARE10>0</SPARE10>" << std::endl ;
1751  *out << " " << std::endl ;
1752  *out << " </DATA>" << std::endl ;
1753  *out << " " << std::endl ;
1754 }
1755 
1756 //=============================================================================================
1757 void PixelFEDCard::writeXML( std::ofstream *fedstream,
1758  std::ofstream *rocstream,
1759  std::ofstream *tbmstream) const
1760 {
1761  std::string mthn = "[PixelFEDCard::writeXML()]\t\t\t " ;
1762 
1763  for(int i=0;i<36;i++)
1764  {
1765  *fedstream << " <DATA>" << std::endl ;
1766  *fedstream << " " << std::endl ;
1767  *fedstream << " <PIXEL_FED>" << fedNumber << "</PIXEL_FED>" << std::endl ;
1768  *fedstream << " <VME_ADDRS_HEX>0x" << hex << FEDBASE_0 << dec << "</VME_ADDRS_HEX>" << std::endl ;
1769  *fedstream << "" << std::endl ;
1770  *fedstream << " <CHANNEL_ID>" << i+1 << "</CHANNEL_ID>" << std::endl ;
1771  *fedstream << " <NUM_ROCS>" << NRocs[i] << "</NUM_ROCS>" << std::endl ;
1772  *fedstream << " <CHAN_OFFST_DAC>" << offs_dac[i] << "</CHAN_OFFST_DAC>" << std::endl ;
1773  *fedstream << " <CHAN_DELAY>" << DelayCh[i] << "</CHAN_DELAY>" << std::endl ;
1774  *fedstream << " <CHAN_BHIGH>" << BlackHi[i] << "</CHAN_BHIGH>" << std::endl ;
1775  *fedstream << " <CHAN_BLOW>" << BlackLo[i] << "</CHAN_BLOW>" << std::endl ;
1776  *fedstream << " <CHAN_UB>" << Ublack[i] << "</CHAN_UB>" << std::endl ;
1777  *fedstream << "" << std::endl ;
1778  *fedstream << " <OPT1_CAP>" << opt_cap[0] << "</OPT1_CAP>" << std::endl ;
1779  *fedstream << " <OPT2_CAP>" << opt_cap[1] << "</OPT2_CAP>" << std::endl ;
1780  *fedstream << " <OPT3_CAP>" << opt_cap[2] << "</OPT3_CAP>" << std::endl ;
1781  *fedstream << " <OPT1_INP>" << opt_inadj[0] << "</OPT1_INP>" << std::endl ;
1782  *fedstream << " <OPT2_INP>" << opt_inadj[1] << "</OPT2_INP>" << std::endl ;
1783  *fedstream << " <OPT3_INP>" << opt_inadj[2] << "</OPT3_INP>" << std::endl ;
1784  *fedstream << " <OPT1_OUT>" << opt_ouadj[0] << "</OPT1_OUT>" << std::endl ;
1785  *fedstream << " <OPT2_OUT>" << opt_ouadj[1] << "</OPT2_OUT>" << std::endl ;
1786  *fedstream << " <OPT3_OUT>" << opt_ouadj[2] << "</OPT3_OUT>" << std::endl ;
1787  *fedstream << " <NORTH_CLKPHB>" << clkphs1_9 << "</NORTH_CLKPHB>" << std::endl ;
1788  *fedstream << " <NORTHCENTER_CLKPHB>" << clkphs10_18 << "</NORTHCENTER_CLKPHB>" << std::endl ;
1789  *fedstream << " <SOUTHCENTER_CLKPHB>" << clkphs19_27 << "</SOUTHCENTER_CLKPHB>" << std::endl ;
1790  *fedstream << " <SOUTH_CLKPHB>" << clkphs28_36 << "</SOUTH_CLKPHB>" << std::endl ;
1791  *fedstream << " <NORTH_CTRL>" << Ncntrl << "</NORTH_CTRL> " << std::endl ;
1792  *fedstream << " <NORTHCENTER_CTRL>" << NCcntrl << "</NORTHCENTER_CTRL>" << std::endl ;
1793  *fedstream << " <SOUTHCENTER_CTRL>" << SCcntrl << "</SOUTHCENTER_CTRL>" << std::endl ;
1794  *fedstream << " <SOUTH_CTRL>" << Scntrl << "</SOUTH_CTRL>" << std::endl ;
1795  *fedstream << " <REG0_TTCRX_FDLA>" << FineDes1Del << "</REG0_TTCRX_FDLA>" << std::endl ;
1796  *fedstream << " <REG1_TTCRX_FDLA>" << FineDes2Del << "</REG1_TTCRX_FDLA>" << std::endl ;
1797  *fedstream << " <REG2_TTCRX_CDLA>" << CoarseDel << "</REG2_TTCRX_CDLA>" << std::endl ;
1798  *fedstream << " <REG3_TTCRX_CLKD2>" << ClkDes2 << "</REG3_TTCRX_CLKD2>" << std::endl ;
1799  *fedstream << " <CENTER_CTRL>" << Ccntrl << "</CENTER_CTRL>" << std::endl ;
1800  *fedstream << " <CENTER_MODE>" << modeRegister << "</CENTER_MODE>" << std::endl ;
1801  *fedstream << " <B1_ADCGN>" << Nadcg << "</B1_ADCGN>" << std::endl ;
1802  *fedstream << " <B2_ADCGN>" << NCadcg << "</B2_ADCGN>" << std::endl ;
1803  *fedstream << " <B3_ADCGN>" << SCadcg << "</B3_ADCGN>" << std::endl ;
1804  *fedstream << " <B4_ADCGN>" << Sadcg << "</B4_ADCGN>" << std::endl ;
1805 // std::cout << "PixelFEDCard::WriteXML()\tNbaseln:" << Nbaseln << std::endl ;
1806 // std::cout << "PixelFEDCard::WriteXML()\tNbaseln:" << std::hex << Nbaseln << std::dec << std::endl ;
1807  *fedstream << " <NORTH_BADJ>" << Nbaseln << "</NORTH_BADJ>" << std::endl ;
1808  *fedstream << " <NORTHCENTER_BADJ>" << NCbaseln << "</NORTHCENTER_BADJ>" << std::endl ;
1809  *fedstream << " <SOUTHCENTER_BADJ>" << SCbaseln << "</SOUTHCENTER_BADJ>" << std::endl ;
1810  *fedstream << " <SOUTH_BADJ>" << Sbaseln << "</SOUTH_BADJ>" << std::endl ;
1811  *fedstream << " <NORTH_TBMMASK>" << N_TBMmask << "</NORTH_TBMMASK>" << std::endl ;
1812  *fedstream << " <NORTHCENTER_TBMMASK>" << NC_TBMmask << "</NORTHCENTER_TBMMASK>" << std::endl ;
1813  *fedstream << " <SOUTHCENTER_TBMMASK>" << SC_TBMmask << "</SOUTHCENTER_TBMMASK>" << std::endl ;
1814  *fedstream << " <SOUTH_TBMMASK>" << S_TBMmask << "</SOUTH_TBMMASK>" << std::endl ;
1815  *fedstream << " <NORTH_PWORD>" << N_Pword << "</NORTH_PWORD>" << std::endl ;
1816  *fedstream << " <NORTHCENTER_PWORD>" << NC_Pword << "</NORTHCENTER_PWORD>" << std::endl ;
1817  *fedstream << " <SOUTHCENTER_PWORD>" << SC_Pword << "</SOUTHCENTER_PWORD>" << std::endl ;
1818  *fedstream << " <SOUTH_PWORD>" << S_Pword << "</SOUTH_PWORD>" << std::endl ;
1819  *fedstream << " <SPECDAC>" << SpecialDac << "</SPECDAC>" << std::endl ;
1820  *fedstream << " <OOS_LVL>" << Ooslvl << "</OOS_LVL>" << std::endl ;
1821  *fedstream << " <ERR_LVL>" << Errlvl << "</ERR_LVL>" << std::endl ;
1822  *fedstream << " <NORTH_FIFO1_BZ_LVL>" << Nfifo1Bzlvl << "</NORTH_FIFO1_BZ_LVL>" << std::endl ;
1823  *fedstream << " <NORTHCENTER_FIFO1_BZ_LVL>" << NCfifo1Bzlvl << "</NORTHCENTER_FIFO1_BZ_LVL>" << std::endl ;
1824  *fedstream << " <SOUTHCENTER_FIFO1_BZ_LVL>" << SCfifo1Bzlvl << "</SOUTHCENTER_FIFO1_BZ_LVL>" << std::endl ;
1825  *fedstream << " <SOUTH_FIFO1_BZ_LVL>" << Sfifo1Bzlvl << "</SOUTH_FIFO1_BZ_LVL>" << std::endl ;
1826  *fedstream << " <FIFO3_WRN_LVL>" << fifo3Wrnlvl << "</FIFO3_WRN_LVL>" << std::endl ;
1827  *fedstream << " <FED_MASTER_DELAY>" << FedTTCDelay << "</FED_MASTER_DELAY>" << std::endl ;
1828  *fedstream << " <NO_HITLIMIT>" << N_hitlimit << "</NO_HITLIMIT>" << std::endl ;
1829  *fedstream << " <NC_HITLIMIT>" << NC_hitlimit << "</NC_HITLIMIT>" << std::endl ;
1830  *fedstream << " <SC_HITLIMIT>" << SC_hitlimit << "</SC_HITLIMIT>" << std::endl ;
1831  *fedstream << " <SO_HITLIMIT>" << S_hitlimit << "</SO_HITLIMIT>" << std::endl ;
1832  *fedstream << " <NO_TESTREG>" << N_testreg << "</NO_TESTREG>" << std::endl ;
1833  *fedstream << " <NC_TESTREG>" << NC_testreg << "</NC_TESTREG>" << std::endl ;
1834  *fedstream << " <SC_TESTREG>" << SC_testreg << "</SC_TESTREG>" << std::endl ;
1835  *fedstream << " <SO_TESTREG>" << S_testreg << "</SO_TESTREG>" << std::endl ;
1836  *fedstream << " <BUSYWHENBEHIND>" << BusyWhenBehind << "</BUSYWHENBEHIND>" << std::endl ;
1837  *fedstream << " <BUSYHOLDMIN>" << BusyHoldMin << "</BUSYHOLDMIN>" << std::endl ;
1838  *fedstream << " <FEATUREREGISTER>" << FeatureRegister << "</FEATUREREGISTER>" << std::endl ;
1839  *fedstream << " <FIFO2LIMIT>" << FIFO2Limit << "</FIFO2LIMIT>" << std::endl ;
1840  *fedstream << " <LASTDACOFF>" << LastDacOff << "</LASTDACOFF>" << std::endl ;
1841  *fedstream << " <SIMHITSPERROC>" << SimHitsPerRoc << "</SIMHITSPERROC>" << std::endl ;
1842  *fedstream << " <TIMEOUTOROOSLIMIT>" << TimeoutOROOSLimit << "</TIMEOUTOROOSLIMIT>" << std::endl ;
1843  *fedstream << " <TRIGGERHOLDOFF>" << TriggerHoldoff << "</TRIGGERHOLDOFF>" << std::endl ;
1844  *fedstream << " <SPARE1>" << SPARE1 << "</SPARE1>" << std::endl ;
1845  *fedstream << " <SPARE2>" << SPARE2 << "</SPARE2>" << std::endl ;
1846  *fedstream << " <SPARE3>" << SPARE3 << "</SPARE3>" << std::endl ;
1847  *fedstream << " <SPARE4>" << SPARE4 << "</SPARE4>" << std::endl ;
1848  *fedstream << " <SPARE5>" << SPARE5 << "</SPARE5>" << std::endl ;
1849  *fedstream << " <SPARE6>" << SPARE6 << "</SPARE6>" << std::endl ;
1850  *fedstream << " <SPARE7>" << SPARE7 << "</SPARE7>" << std::endl ;
1851  *fedstream << " <SPARE8>" << SPARE8 << "</SPARE8>" << std::endl ;
1852  *fedstream << " <SPARE9>" << SPARE9 << "</SPARE9>" << std::endl ;
1853  *fedstream << " <SPARE10>" << SPARE10 << "</SPARE10>" << std::endl ;
1854  *fedstream << " " << std::endl ;
1855  *fedstream << " </DATA>" << std::endl ;
1856  *fedstream << " " << std::endl ;
1857  }
1858 
1859  //ROC & TBM LEVELS
1860  for(int i=0;i<36;i++)
1861  {
1862  for(int j=0;j<NRocs[i];j++)
1863  {
1864  *rocstream << "" << std::endl ;
1865  *rocstream << " <DATA>" << std::endl ;
1866  *rocstream << " <PIXEL_FED>" << fedNumber << "</PIXEL_FED>" << std::endl ;
1867  *rocstream << " <FED_CHAN>" << i+1 << "</FED_CHAN>" << std::endl ;
1868  *rocstream << " <FED_ROC_NUM>" << j << "</FED_ROC_NUM>" << std::endl ;
1869  *rocstream << " <ROC_L0>" << ROC_L0[i][j] << "</ROC_L0>" << std::endl ;
1870  *rocstream << " <ROC_L1>" << ROC_L1[i][j] << "</ROC_L1>" << std::endl ;
1871  *rocstream << " <ROC_L2>" << ROC_L2[i][j] << "</ROC_L2>" << std::endl ;
1872  *rocstream << " <ROC_L3>" << ROC_L3[i][j] << "</ROC_L3>" << std::endl ;
1873  *rocstream << " <ROC_L4>" << ROC_L4[i][j] << "</ROC_L4>" << std::endl ;
1874  *rocstream << " </DATA>" << std::endl << std::endl ;
1875  *rocstream << " " << std::endl ;
1876  }
1877 
1878  *tbmstream << "" << std::endl ;
1879  *tbmstream << " <DATA>" << std::endl ;
1880  *tbmstream << " <PIXEL_FED>" << fedNumber << "</PIXEL_FED>" << std::endl ;
1881  *tbmstream << " <FED_CHAN>" << i+1 << "</FED_CHAN>" << std::endl ;
1882  *tbmstream << " <TBMA_HEAD_L0>" << TBM_L0[i] << "</TBMA_HEAD_L0>" << std::endl ;
1883  *tbmstream << " <TBMA_HEAD_L1>" << TBM_L1[i] << "</TBMA_HEAD_L1>" << std::endl ;
1884  *tbmstream << " <TBMA_HEAD_L2>" << TBM_L2[i] << "</TBMA_HEAD_L2>" << std::endl ;
1885  *tbmstream << " <TBMA_HEAD_L3>" << TBM_L3[i] << "</TBMA_HEAD_L3>" << std::endl ;
1886  *tbmstream << " <TBMA_HEAD_L4>" << TBM_L4[i] << "</TBMA_HEAD_L4>" << std::endl ;
1887  *tbmstream << " <TBMA_TRAIL_L0>" << TRL_L0[i] << "</TBMA_TRAIL_L0>" << std::endl ;
1888  *tbmstream << " <TBMA_TRAIL_L1>" << TRL_L1[i] << "</TBMA_TRAIL_L1>" << std::endl ;
1889  *tbmstream << " <TBMA_TRAIL_L2>" << TRL_L2[i] << "</TBMA_TRAIL_L2>" << std::endl ;
1890  *tbmstream << " <TBMA_TRAIL_L3>" << TRL_L3[i] << "</TBMA_TRAIL_L3>" << std::endl ;
1891  *tbmstream << " <TBMA_TRAIL_L4>" << TRL_L4[i] << "</TBMA_TRAIL_L4>" << std::endl ;
1892  *tbmstream << " </DATA>" << std::endl << std::endl ;
1893  *tbmstream << "" << std::endl ;
1894  }
1895 }
1896 
1897 //=============================================================================================
1898 void PixelFEDCard::writeXMLTrailer(std::ofstream *fedstream,
1899  std::ofstream *rocstream,
1900  std::ofstream *tbmstream ) const
1901 {
1902  std::string mthn = "[PixelFEDCard::writeXMLTrailer()]\t\t\t " ;
1903 
1904  // Main FED
1905  *fedstream << " </DATA_SET>" << std::endl ;
1906  *fedstream << "</ROOT>" << std::endl ;
1907 
1908  fedstream->close() ;
1909  std::cout << __LINE__ << "]\t" << mthn << "Data written for main fed" << std::endl ;
1910 
1911  // ROC LVLS
1912  *rocstream << " </DATA_SET>" << std::endl ;
1913  *rocstream << "</ROOT>" << std::endl ;
1914 
1915  rocstream->close() ;
1916  std::cout << __LINE__ << "]\t" << mthn << "Data written for roc analog levels" << std::endl ;
1917 
1918  // TBM LVLS
1919  *tbmstream << " </DATA_SET>" << std::endl ;
1920  *tbmstream << "</ROOT>" << std::endl ;
1921 
1922  tbmstream->close() ;
1923  std::cout << __LINE__ << "]\t" << mthn << "Data written for tbm analog levels" << std::endl ;
1924 }
1925 
1926 //=============================================================================================
1927 void PixelFEDCard::writeXMLTrailer(std::ofstream *out) const {
1928  std::string mthn = "[PixelFEDCard::writeXMLTrailer()]\t\t\t " ;
1929 
1930  *out << " </DATA_SET>" << std::endl ;
1931  *out << "</ROOT>" << std::endl ;
1932 
1933  out->close() ;
1934  std::cout << __LINE__ << "]\t" << mthn << "Data written" << std::endl ;
1935 }
1936 
1937 //=============================================================================================
1938 void PixelFEDCard::writeXML(pos::PixelConfigKey key, int version, std::string path) const {
1939  std::string mthn = "[PixelFEDCard::writeXML()]\t\t\t " ;
1940  std::stringstream fullPath ;
1941 
1942  fullPath << path << "/fedcard.xml" ;
1943  std::cout << __LINE__ << "]\t" << mthn << "Writing to: |" << fullPath.str() << "|" << std::endl ;
1944 
1945  std::ofstream out(fullPath.str().c_str()) ;
1946 
1947  out << "<ROOT>" << std::endl ;
1948  out << "" << std::endl ;
1949  out << " <HEADER>" << std::endl ;
1950  out << " <TYPE>" << std::endl ;
1951  out << " <EXTENSION_TABLE_NAME>FED_CONFIGURATION</EXTENSION_TABLE_NAME>" << std::endl ;
1952  out << " <NAME>Pixel FED Configuration</NAME>" << std::endl ;
1953  out << " </TYPE>" << std::endl ;
1954  out << " <RUN>" << std::endl ;
1955  out << " <RUN_TYPE>Pixel FED Configuration</RUN_TYPE>" << std::endl ;
1956  out << " <RUN_NUMBER>1</RUN_NUMBER>" << std::endl ;
1957  out << " <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl ;
1958  out << " <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl ;
1959  out << " <LOCATION>CERN TAC</LOCATION>" << std::endl ;
1960  out << " <CREATED_BY_USER>Dario Menasce</CREATED_BY_USER>" << std::endl ;
1961  out << " </RUN>" << std::endl ;
1962  out << " </HEADER>" << std::endl ;
1963  out << "" << std::endl ;
1964  out << " <DATA_SET>" << std::endl ;
1965  out << "" << std::endl ;
1966  out << " <VERSION>T_E_S_T</VERSION>" << std::endl ;
1967  out << " <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl ;
1968  out << "" << std::endl ;
1969  out << " <PART>" << std::endl ;
1970  out << " <NAME_LABEL>CMS-PIXEL-ROOT</NAME_LABEL>" << std::endl ;
1971  out << " <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl ;
1972  out << " </PART>" << std::endl ;
1973  out << "" << std::endl ;
1974  out << " <DATA>" << std::endl ;
1975  out << " <PXLFED_NAME>PxlFED_32</PXLFED_NAME>" << std::endl ;
1976  out << " <CRATE_NUMBER>1</CRATE_NUMBER>" << std::endl ;
1977  out << " <SLOT_NUMBER>5</SLOT_NUMBER> " << std::endl ;
1978  out << " <VME_ADDRESS>268435456</VME_ADDRESS>" << std::endl ;
1979  out << " <CRATE_LABEL>S1G03e</CRATE_LABEL>" << std::endl ;
1980  out << "" << std::endl ;
1981  out << " <CHANNEL_ID>1</CHANNEL_ID>" << std::endl ;
1982  out << " <NUMBER_OF_ROCS>21</NUMBER_OF_ROCS>" << std::endl ;
1983  out << " <CHANNEL_OFFSET_DAC_SETTINGS>0</CHANNEL_OFFSET_DAC_SETTINGS>" << std::endl ;
1984  out << " <CHANNEL_DELAY_SETTINGS>3</CHANNEL_DELAY_SETTINGS>" << std::endl ;
1985  out << " <CHANNEL_BLACK_HIGH>400</CHANNEL_BLACK_HIGH>" << std::endl ;
1986  out << " <CHANNEL_BLACK_LOW>150</CHANNEL_BLACK_LOW>" << std::endl ;
1987  out << " <CHANNEL_ULTRA_BLACK>120</CHANNEL_ULTRA_BLACK>" << std::endl ;
1988  out << "" << std::endl ;
1989  out << " <OPT1_CAP>0</OPT1_CAP>" << std::endl ;
1990  out << " <OPT2_CAP>0</OPT2_CAP>" << std::endl ;
1991  out << " <OPT3_CAP>0</OPT3_CAP>" << std::endl ;
1992  out << " <OPT1_INP>0</OPT1_INP>" << std::endl ;
1993  out << " <OPT2_INP>0</OPT2_INP>" << std::endl ;
1994  out << " <OPT3_INP>0</OPT3_INP>" << std::endl ;
1995  out << " <OPT1_OUT>0</OPT1_OUT>" << std::endl ;
1996  out << " <OPT2_OUT>0</OPT2_OUT>" << std::endl ;
1997  out << " <OPT3_OUT>0</OPT3_OUT>" << std::endl ;
1998  out << " <NORTH_CLKPHB>511</NORTH_CLKPHB>" << std::endl ;
1999  out << " <NORTHCENTER_CLKPHB>511</NORTHCENTER_CLKPHB>" << std::endl ;
2000  out << " <SOUTHCENTER_CLKPHB>511</SOUTHCENTER_CLKPHB>" << std::endl ;
2001  out << " <SOUTH_CLKPHB>511</SOUTH_CLKPHB>" << std::endl ;
2002  out << " <NORTH_CTRL>0</NORTH_CTRL> " << std::endl ;
2003  out << " <NORTHCENTER_CTRL>0</NORTHCENTER_CTRL>" << std::endl ;
2004  out << " <SOUTHCENTER_CTRL>0</SOUTHCENTER_CTRL>" << std::endl ;
2005  out << " <SOUTH_CTRL>0</SOUTH_CTRL>" << std::endl ;
2006  out << " <REG1_TTCRX_FDLA>5</REG1_TTCRX_FDLA>" << std::endl ;
2007  out << " <REG2_TTCRX_CDLA>0</REG2_TTCRX_CDLA>" << std::endl ;
2008  out << " <REG3_TTCRX_CLKD2>155</REG3_TTCRX_CLKD2>" << std::endl ;
2009  out << " <CENTER_CTRL>0</CENTER_CTRL>" << std::endl ;
2010  out << " <CENTER_MODE>0</CENTER_MODE>" << std::endl ;
2011  out << " <B1_ADCGN>0</B1_ADCGN>" << std::endl ;
2012  out << " <B2_ADCGN>0</B2_ADCGN>" << std::endl ;
2013  out << " <B3_ADCGN>0</B3_ADCGN>" << std::endl ;
2014  out << " <B4_ADCGN>0</B4_ADCGN>" << std::endl ;
2015  out << " <NORTH_BADJ>330</NORTH_BADJ>" << std::endl ;
2016  out << " <NORTHCENTER_BADJ>330</NORTHCENTER_BADJ>" << std::endl ;
2017  out << " <SOUTHCENTER_BADJ>330</SOUTHCENTER_BADJ>" << std::endl ;
2018  out << " <SOUTH_BADJ>330</SOUTH_BADJ>" << std::endl ;
2019  out << " <NORTH_TBMMASK>2</NORTH_TBMMASK>" << std::endl ;
2020  out << " <NORTHCENTER_TBMMASK>2</NORTHCENTER_TBMMASK>" << std::endl ;
2021  out << " <SOUTHCENTER_TBMMASK>2</SOUTHCENTER_TBMMASK>" << std::endl ;
2022  out << " <SOUTH_TBMMASK>2</SOUTH_TBMMASK>" << std::endl ;
2023  out << " <NORTH_PWORD>177</NORTH_PWORD>" << std::endl ;
2024  out << " <NORTHCENTER_PWORD>178</NORTHCENTER_PWORD>" << std::endl ;
2025  out << " <SOUTHCENTER_PWORD>179</SOUTHCENTER_PWORD>" << std::endl ;
2026  out << " <SOUTH_PWORD>180</SOUTH_PWORD>" << std::endl ;
2027  out << " <SPECDAC>0</SPECDAC>" << std::endl ;
2028  out << " <OOS_LVL>0</OOS_LVL>" << std::endl ;
2029  out << " <ERR_LVL>0</ERR_LVL>" << std::endl ;
2030  out << " <NORTH_FIFO1_BZ_LVL>900</NORTH_FIFO1_BZ_LVL>" << std::endl ;
2031  out << " <NORTHCENTER_FIFO1_BZ_LVL>900</NORTHCENTER_FIFO1_BZ_LVL>" << std::endl ;
2032  out << " <SOUTHCENTER_FIFO1_BZ_LVL>900</SOUTHCENTER_FIFO1_BZ_LVL>" << std::endl ;
2033  out << " <SOUTH_FIFO1_BZ_LVL>900</SOUTH_FIFO1_BZ_LVL>" << std::endl ;
2034  out << " <FIFO3_WRN_LVL>7680</FIFO3_WRN_LVL> " << std::endl ;
2035  out << " <FED_MASTER_DELAY>0</FED_MASTER_DELAY>" << std::endl ;
2036  out << " <NO_HITLIMIT>0</NO_HITLIMIT>" << std::endl ;
2037  out << " <NC_HITLIMIT>0</NC_HITLIMIT>" << std::endl ;
2038  out << " <SC_HITLIMIT>0</SC_HITLIMIT>" << std::endl ;
2039  out << " <SO_HITLIMIT>0</SO_HITLIMIT>" << std::endl ;
2040  out << " <NO_TESTREG>0</NO_TESTREG>" << std::endl ;
2041  out << " <NC_TESTREG>0</NC_TESTREG>" << std::endl ;
2042  out << " <SC_TESTREG>0</SC_TESTREG>" << std::endl ;
2043  out << " <SO_TESTREG>0</SO_TESTREG>" << std::endl ;
2044  out << " <BUSYWHENBEHIND>4</BUSYWHENBEHIND>" << std::endl ;
2045  out << " <FEATUREREGISTER>0X1234</FEATUREREGISTER>" << std::endl ;
2046  out << " <FIFO2LIMIT>0X1C00</FIFO2LIMIT>" << std::endl ;
2047  out << " <TIMEOUTOROOSLIMIT>0</TIMEOUTOROOSLIMIT>" << std::endl ;
2048  out << " <LASTDACOFF>0</LASTDACOFF>" << std::endl ;
2049  out << " <SIMHITSPERROC>0</SIMHITSPERROC>" << std::endl ;
2050  out << " <BUSYHOLDMIN>0</BUSYHOLDMIN>" << std::endl ;
2051  out << " <SPARE1>0</SPARE1>" << std::endl ;
2052  out << " <SPARE2>0</SPARE2>" << std::endl ;
2053  out << " <SPARE3>0</SPARE3>" << std::endl ;
2054  out << " <SPARE4>0</SPARE4>" << std::endl ;
2055  out << " <SPARE5>0</SPARE5>" << std::endl ;
2056  out << " <SPARE6>0</SPARE6>" << std::endl ;
2057  out << " <SPARE7>0</SPARE7>" << std::endl ;
2058  out << " <SPARE8>0</SPARE8>" << std::endl ;
2059  out << " <SPARE9>0</SPARE9>" << std::endl ;
2060  out << " <SPARE10>0</SPARE10>" << std::endl ;
2061  out << " </DATA>" << std::endl ;
2062 /*
2063  out<< " <DATA>
2064  <OPT1_CAP>0</OPT1_CAP>
2065  <OPT2_CAP>0</OPT2_CAP>
2066  <OPT3_CAP>0</OPT3_CAP>
2067  <OPT1_INP>0</OPT1_INP>
2068  <OPT2_INP>0</OPT2_INP>
2069  <OPT3_INP>0</OPT3_INP>
2070  <OPT1_OUT>0</OPT1_OUT>
2071  <OPT2_OUT>0</OPT2_OUT>
2072  <OPT3_OUT>0</OPT3_OUT>
2073  <NORTH_CLKPHB>511</NORTH_CLKPHB>
2074  <NORTHCENTER_CLKPHB>511</NORTHCENTER_CLKPHB>
2075  <SOUTHCENTER_CLKPHB>511</SOUTHCENTER_CLKPHB>
2076  <SOUTH_CLKPHB>511</SOUTH_CLKPHB>
2077  <NORTH_CTRL>0</NORTH_CTRL>
2078  <NORTHCENTER_CTRL>0</NORTHCENTER_CTRL>
2079  <SOUTHCENTER_CTRL>0</SOUTHCENTER_CTRL>
2080  <SOUTH_CTRL>0</SOUTH_CTRL>
2081  <REG1_TTCRX_FDLA>5</REG1_TTCRX_FDLA>
2082  <REG2_TTCRX_CDLA>0</REG2_TTCRX_CDLA>
2083  <REG3_TTCRX_CLKD2>155</REG3_TTCRX_CLKD2>
2084  <CENTER_CTRL>0</CENTER_CTRL>
2085  <CENTER_MODE>0</CENTER_MODE>
2086  <B1_ADCGN>0</B1_ADCGN>
2087  <B2_ADCGN>0</B2_ADCGN>
2088  <B3_ADCGN>0</B3_ADCGN>
2089  <B4_ADCGN>0</B4_ADCGN>
2090  <NORTH_BADJ>330</NORTH_BADJ>
2091  <NORTHCENTER_BADJ>330</NORTHCENTER_BADJ>
2092  <SOUTHCENTER_BADJ>330</SOUTHCENTER_BADJ>
2093  <SOUTH_BADJ>330</SOUTH_BADJ>
2094  <NORTH_TBMMASK>2</NORTH_TBMMASK>
2095  <NORTHCENTER_TBMMASK>2</NORTHCENTER_TBMMASK>
2096  <SOUTHCENTER_TBMMASK>2</SOUTHCENTER_TBMMASK>
2097  <SOUTH_TBMMASK>2</SOUTH_TBMMASK>
2098  <NORTH_PWORD>177</NORTH_PWORD>
2099  <NORTHCENTER_PWORD>178</NORTHCENTER_PWORD>
2100  <SOUTHCENTER_PWORD>179</SOUTHCENTER_PWORD>
2101  <SOUTH_PWORD>180</SOUTH_PWORD>
2102  <SPECDAC>0</SPECDAC>
2103  <OOS_LVL>0</OOS_LVL>
2104  <ERR_LVL>0</ERR_LVL>
2105  <NORTH_FIFO1_BZ_LVL>900</NORTH_FIFO1_BZ_LVL>
2106  <NORTHCENTER_FIFO1_BZ_LVL>900</NORTHCENTER_FIFO1_BZ_LVL>
2107  <SOUTHCENTER_FIFO1_BZ_LVL>900</SOUTHCENTER_FIFO1_BZ_LVL>
2108  <SOUTH_FIFO1_BZ_LVL>900</SOUTH_FIFO1_BZ_LVL>
2109  <FIFO3_WRN_LVL>7680</FIFO3_WRN_LVL>
2110  </DATA>
2111 
2112  </DATA_SET>
2113  out << " </DATA_SET>" << std::endl ;
2114  out << "</ROOT>" << std::endl ;
2115 
2116  out.close() ;
2117 */
2118  std::cout << __LINE__ << "]\t" << mthn << "Data written" << std::endl ;
2119 }
2120 
2121 //=============================================================================================
2122 uint64_t PixelFEDCard::enabledChannels() {
2123  uint64_t channels=0;
2124 // return a 64-bit word with low 36 bits set if a channel is enabled
2125 // if bits are set in the control registers, transfer of data from
2126 // fifo1 to fifo 2 is not done, meaning the channel is disabled.
2127  channels = (Ncntrl & 0x1ffLL); // Add LL for SLC4, d.k. 12/07
2128  channels += (NCcntrl & 0x1ffLL) << 9;
2129  channels += (SCcntrl & 0x1ffLL) << 18;
2130  channels += (Scntrl & 0x1ffLL) << 27;
2131  return ~channels; //bitwise complement to get enabled channels
2132 }
2133 
2134 bool PixelFEDCard::useChannel(unsigned int iChannel){
2135  assert(iChannel>0&&iChannel<37);
2136  return (enabledChannels()>>(iChannel-1))&0x1LL;
2137 }
2138 
2139 void PixelFEDCard::setChannel(unsigned int iChannel, bool mode){
2140  assert(iChannel>0&&iChannel<37);
2141  long long mask=enabledChannels();
2142  long long bit=0x1LL<<(iChannel-1);
2143  if (mode) {
2144  mask=mask|bit;
2145  }
2146  else{
2147  bit=~bit;
2148  mask=mask&bit;
2149  }
2150  mask=~mask;
2151  Ncntrl=(Ncntrl& 0xffff0000LL) | (mask& 0x1ffLL);
2152  mask=mask>>9;
2153  NCcntrl=(NCcntrl& 0xffff0000LL) | (mask& 0x1ffLL);
2154  mask=mask>>9;
2155  SCcntrl=(SCcntrl& 0xffff0000LL) | (mask& 0x1ffLL);
2156  mask=mask>>9;
2157  Scntrl=(Scntrl& 0xffff0000LL) | (mask& 0x1ffLL);
2158 
2159 }
2160 
2161 void PixelFEDCard::restoreBaselinAndChannelMasks(){
2162 
2163  Ncntrl=Ncntrl_original;
2164  NCcntrl=NCcntrl_original;
2165  SCcntrl=SCcntrl_original;
2166  Scntrl=Scntrl_original;
2167 
2168  Nbaseln=Nbaseln_original;
2169  NCbaseln=NCbaseln_original;
2170  SCbaseln=SCbaseln_original;
2171  Sbaseln=Sbaseln_original;
2172 
2173 
2174 }
2175 
2176 
2177 void PixelFEDCard::restoreControlAndModeRegister(){
2178 
2179  Ccntrl=Ccntrl_original;
2180  modeRegister=modeRegister_original;
2181 
2182 }
2183 
2184 /* Emacs specific customization
2185  ;;; Local Variables: ***
2186  ;;; indent-tabs-mode:nil ***
2187  ;;; c-set-style:gnu ***
2188  ;;; End: ***
2189 */
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Definition: findQualityFiles.py:442
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Definition: PixelFEDCard.h:156
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Definition: PixelConfigBase.h:33
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Definition: PixelFEDCard.h:115
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Definition: PixelFEDCard.h:108
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Definition: PixelFEDCard.cc:2161
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Definition: PixelFEDCard.h:130
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Definition: PixelFEDCard.cc:1927
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Definition: PixelFEDCard.cc:1620
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