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CSCCFEBStatusDigi.cc
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1 
8 #include <iostream>
9 #include <stdint.h>
10 
12 int CSCCFEBStatusDigi::ShiftSel(int nmb,int nshift,int nsel) const {
13  int tmp=nmb;
14  tmp=tmp>>nshift;
15  return tmp= tmp & nsel;
16 }
18 std::vector<uint16_t> CSCCFEBStatusDigi::getSCAFullCond() const {
19  /* std::vector<int> vec(4,0);
20  vec[0]=ShiftSel(SCAFullCond_,0,15); // 4-bit FIFO1 word count
21  vec[1]=ShiftSel(SCAFullCond_,4,15); // 4-bit Block Number if Error Code=1
22  // (CFEB: SCA Capacitors Full)
23  // 4-bit FIFO3 word count if Error Code=2
24  // (CFEB: FPGA FIFO full)
25  vec[2]=ShiftSel(SCAFullCond_,9,7); // Error Code
26  vec[3]=ShiftSel(SCAFullCond_,12,15); // DDU Code, should be 0xB
27  return vec;*/
28  return bWords_;
29 }
31 std::vector<int> CSCCFEBStatusDigi::getTS_FLAG() const {
32  std::vector<int> vec(contrWords_.size(),0);
33  int nmb;
34  for(unsigned int i=0;i<vec.size();i++) {
35  nmb=contrWords_[i];
36  vec[i]=ShiftSel(nmb,15,1);
37  }
38  return vec;
39 }
40 
42 std::vector<int> CSCCFEBStatusDigi::getSCA_FULL() const {
43  std::vector<int> vec(contrWords_.size(),0);
44  int nmb;
45  for(unsigned int i=0;i<vec.size();i++) {
46  nmb=contrWords_[i];
47  vec[i]=ShiftSel(nmb,14,1);
48  }
49  return vec;
50 }
51 
53 std::vector<int> CSCCFEBStatusDigi::getLCT_PHASE() const {
54  std::vector<int> vec(contrWords_.size(),0);
55  int nmb;
56  for(unsigned int i=0;i<vec.size();i++) {
57  nmb=contrWords_[i];
58  vec[i]=ShiftSel(nmb,13,1);
59  }
60  return vec;
61 }
62 
64 std::vector<int> CSCCFEBStatusDigi::getL1A_PHASE() const {
65  std::vector<int> vec(contrWords_.size(),0);
66  int nmb;
67  for(unsigned int i=0;i<vec.size();i++) {
68  nmb=contrWords_[i];
69  vec[i]=ShiftSel(nmb,12,1);
70  }
71  return vec;
72 }
73 
75 std::vector<int> CSCCFEBStatusDigi::getSCA_BLK() const {
76  std::vector<int> vec(contrWords_.size(),0);
77  int nmb;
78  for(unsigned int i=0;i<vec.size();i++) {
79  nmb=contrWords_[i];
80  vec[i]=ShiftSel(nmb,8,15);
81  }
82  return vec;
83 }
84 
86 std::vector<int> CSCCFEBStatusDigi::getTRIG_TIME() const {
87  std::vector<int> vec(contrWords_.size(),0);
88  int nmb;
89  for(unsigned int i=0;i<vec.size();i++) {
90  nmb=contrWords_[i];
91  vec[i]=ShiftSel(nmb,0,255);
92  }
93  return vec;
94 }
95 
98  edm::LogVerbatim("CSCDigi") << "CSC CFEB # : " << getCFEBNmb();
99 
100  std::ostringstream ost;
101  ost << " SCAFullCond: ";
102  if(getSCAFullCond().size()!=0){
103  for (size_t i = 0; i<4; ++i ){ ost << " " <<(getSCAFullCond())[i]; }
104  }
105  else {
106  ost << " " <<"BWORD is not valid";
107  }
108  edm::LogVerbatim("CSCDigi") << ost.str();
109 
110  ost.clear();
111  ost << " CRC: ";
112  for (size_t i = 0; i<getCRC().size(); ++i ){ ost << " " <<(getCRC())[i]; }
113  edm::LogVerbatim("CSCDigi") << ost.str();
114 
115  ost.clear();
116  ost << " TS_FLAG: ";
117  for (size_t i = 0; i<getTS_FLAG().size(); ++i ){ ost << " " <<(getTS_FLAG())[i]; }
118  edm::LogVerbatim("CSCDigi") << ost.str();
119 
120  ost.clear();
121  ost << " SCA_FULL: ";
122  for (size_t i = 0; i<getSCA_FULL().size(); ++i ){ ost << " " <<(getSCA_FULL())[i]; }
123  edm::LogVerbatim("CSCDigi") << ost.str();
124 
125  ost.clear();
126  ost << " LCT_PHASE: ";
127  for (size_t i = 0; i<getLCT_PHASE().size(); ++i ){ ost << " " <<(getLCT_PHASE())[i]; }
128  edm::LogVerbatim("CSCDigi") << ost.str();
129 
130  ost.clear();
131  ost << " L1A_PHASE: ";
132  for (size_t i = 0; i<getL1A_PHASE().size(); ++i ){ ost << " " <<(getL1A_PHASE())[i]; }
133  edm::LogVerbatim("CSCDigi") << ost.str();
134 
135  ost.clear();
136  ost << " SCA_BLK: ";
137  for (size_t i = 0; i<getSCA_BLK().size(); ++i ){ ost << " " <<(getSCA_BLK())[i]; }
138  edm::LogVerbatim("CSCDigi") << ost.str();
139 
140  ost.clear();
141  ost << " TRIG_TIME: ";
142  for (size_t i = 0; i<getTRIG_TIME().size(); ++i ){ ost << " " <<(getTRIG_TIME())[i]; }
143  edm::LogVerbatim("CSCDigi") << ost.str();
144 }
145 
146 std::ostream & operator<<(std::ostream & o, const CSCCFEBStatusDigi& digi) {
147  o << " " << digi.getCFEBNmb()<<"\n";
148  for (size_t i = 0; i<4; ++i ){
149  o <<" " <<(digi.getSCAFullCond())[i]; }
150  o <<"\n";
151  for (size_t i = 0; i<digi.getCRC().size(); ++i ){
152  o <<" " <<(digi.getCRC())[i]; }
153  o<<"\n";
154  for (size_t i = 0; i<digi.getTS_FLAG().size(); ++i ){
155  o <<" " <<(digi.getTS_FLAG())[i]; }
156  o<<"\n";
157  for (size_t i = 0; i<digi.getSCA_FULL().size(); ++i ){
158  o <<" " <<(digi.getSCA_FULL())[i]; }
159  o<<"\n";
160  for (size_t i = 0; i<digi.getLCT_PHASE().size(); ++i ){
161  o <<" " <<(digi.getLCT_PHASE())[i]; }
162  o<<"\n";
163  for (size_t i = 0; i<digi.getL1A_PHASE().size(); ++i ){
164  o <<" " <<(digi.getL1A_PHASE())[i]; }
165  o<<"\n";
166  for (size_t i = 0; i<digi.getSCA_BLK().size(); ++i ){
167  o <<" " <<(digi.getSCA_BLK())[i]; }
168  o<<"\n";
169  for (size_t i = 0; i<digi.getTRIG_TIME().size(); ++i ){
170  o <<" " <<(digi.getTRIG_TIME())[i]; }
171  o<<"\n";
172 
173  return o;
174 }
175 
size
Write out results.
std::vector< int > getTS_FLAG() const
Get TS_FLAG bit from SCA Controller data per each time slice.
std::vector< int > getSCA_BLK() const
Get SCA_BLK 4 bit word from SCA Controller data per each time slice.
std::vector< int > getL1A_PHASE() const
Get L1A_PHASE bit from SCA Controller data per each time slice.
std::vector< int > getLCT_PHASE() const
Get LCT_PHASE bit from SCA Controller data per each time slice.
int getCFEBNmb() const
Get the CFEB number.
std::vector< uint16_t > getSCAFullCond() const
Get SCA Full Condition.
std::vector< int > getSCA_FULL() const
Get SCA_FULL bit from SCA Controller data per each time slice.
std::ostream & operator<<(std::ostream &o, const CSCCFEBStatusDigi &digi)
std::vector< uint16_t > getCRC() const
Get CRC per each time sample.
int ShiftSel(int nmb, int nshift, int nsel) const
Shift and select.
std::vector< std::vector< double > > tmp
Definition: MVATrainer.cc:100
std::vector< int > getTRIG_TIME() const
Get TRIG_TIME 8 bit word from SCA Controller data per each time slice.
std::vector< uint16_t > contrWords_
std::vector< uint16_t > bWords_
void print() const
Print content of digi.