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SiStripFecCabling Class Reference

#include <SiStripFecCabling.h>

Public Member Functions

void addDevices (const FedChannelConnection &conn)
 
void buildFecCabling (const SiStripFedCabling &)
 
void connections (std::vector< FedChannelConnection > &) const
 
NumberOfDevices countDevices () const
 
const std::vector< SiStripFecCrate > & crates () const
 
std::vector< SiStripFecCrate > & crates ()
 
void dcuId (const FedChannelConnection &conn)
 
void detId (const FedChannelConnection &conn)
 
const std::vector< SiStripFec > & fecs () const
 
const SiStripModulemodule (const FedChannelConnection &conn) const
 
SiStripModulemodule (const FedChannelConnection &conn)
 
const SiStripModulemodule (const uint32_t &dcu_id) const
 
void nApvPairs (const FedChannelConnection &conn)
 
void print (std::stringstream &) const
 
 SiStripFecCabling (const SiStripFedCabling &)
 
 SiStripFecCabling ()
 
void terse (std::stringstream &) const
 
 ~SiStripFecCabling ()
 

Private Attributes

std::vector< SiStripFecCratecrates_
 

Detailed Description

Definition at line 24 of file SiStripFecCabling.h.

Constructor & Destructor Documentation

SiStripFecCabling::SiStripFecCabling ( const SiStripFedCabling fed_cabling)

Definition at line 13 of file SiStripFecCabling.cc.

References buildFecCabling(), crates_, LogTrace, and sistrip::mlCabling_.

14  : crates_()
15 {
17  << "[SiStripFecCabling::" << __func__ << "]"
18  << " Constructing object...";
19  crates_.reserve(4);
20  buildFecCabling( fed_cabling );
21 }
std::vector< SiStripFecCrate > crates_
static const char mlCabling_[]
void buildFecCabling(const SiStripFedCabling &)
#define LogTrace(id)
SiStripFecCabling::SiStripFecCabling ( )
inline

Definition at line 33 of file SiStripFecCabling.h.

33 {;}
SiStripFecCabling::~SiStripFecCabling ( )
inline

Definition at line 35 of file SiStripFecCabling.h.

References addDevices(), buildFecCabling(), connections(), countDevices(), crates(), dcuId(), detId(), fecs(), module(), nApvPairs(), print(), and terse().

35 {;} //@@ needs implementation!!

Member Function Documentation

void SiStripFecCabling::addDevices ( const FedChannelConnection conn)

Definition at line 63 of file SiStripFecCabling.cc.

References crates_, and FedChannelConnection::fecCrate().

Referenced by buildFecCabling(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDetIds(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices(), SiStripFedCablingBuilderFromDb::buildFecCablingFromFedConnections(), SiStripFedCablingFakeESSource::make(), and ~SiStripFecCabling().

63  {
64  auto icrate = crates_.begin();
65  while ( icrate != crates_.end() && (*icrate).fecCrate() != conn.fecCrate() ) { icrate++; }
66  if ( icrate == crates_.end() ) {
67  crates_.push_back( SiStripFecCrate( conn ) );
68  } else {
69  icrate->addDevices( conn );
70  }
71 }
const uint16_t & fecCrate() const
std::vector< SiStripFecCrate > crates_
void SiStripFecCabling::buildFecCabling ( const SiStripFedCabling fed_cabling)

Definition at line 25 of file SiStripFecCabling.cc.

References addDevices(), begin, crates(), SiStripFedCabling::fedConnections(), SiStripFedCabling::fedIds(), sistrip::invalid_, LogTrace, and sistrip::mlCabling_.

Referenced by SiStripFedCablingBuilderFromDb::getFecCabling(), SiStripFecCabling(), and ~SiStripFecCabling().

25  {
27  << "[SiStripFecCabling::" << __func__ << "]"
28  << " Building FEC cabling...";
29 
30  // Retrieve and iterate through FED ids
31  auto feds = fed_cabling.fedIds();
32  for ( auto ifed = feds.begin(); ifed != feds.end(); ifed++ ) {
33 
34  // Retrieve and iterate through FED channel connections
35  auto conns = fed_cabling.fedConnections( *ifed );
36  for ( auto iconn = conns.begin(); iconn != conns.end(); iconn++ ) {
37 
38  // Check that FED id is not invalid and add devices
39  if ( iconn->fedId() != sistrip::invalid_ ) { addDevices( *iconn ); }
40 
41  }
42  }
43 
44  // Consistency checks
45  for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); ++icrate ) {
46  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec ) {
47  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); ++iring ) {
48  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); ++iccu ) {
49  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); ++imod ) {
50  //@@ need consistency checks here!
51  }
52  }
53  }
54  }
55  }
57  << "[SiStripFecCabling::" << __func__ << "]"
58  << " Finished building FEC cabling";
59 }
void addDevices(const FedChannelConnection &conn)
const std::vector< SiStripFecCrate > & crates() const
static const char mlCabling_[]
FedsConstIterRange fedIds() const
#define LogTrace(id)
static const uint16_t invalid_
Definition: Constants.h:16
ConnsConstIterRange fedConnections(uint16_t fed_id) const
#define begin
Definition: vmac.h:30
void SiStripFecCabling::connections ( std::vector< FedChannelConnection > &  conns) const

Definition at line 75 of file SiStripFecCabling.cc.

References begin, FedChannelConnection::ccuAddr(), FedChannelConnection::ccuChan(), crates(), FedChannelConnection::fecCrate(), FedChannelConnection::fecRing(), fecs(), FedChannelConnection::fecSlot(), plotBeamSpotDB::first, LogTrace, sistrip::mlCabling_, ErrorSummaryFilter_cfi::modules, and edm::second().

Referenced by SiStripFedCablingBuilderFromDb::getFedCabling(), SiStripFedCablingFakeESSource::make(), and ~SiStripFecCabling().

75  {
77  << "[SiStripFecCabling::" << __func__ << "]"
78  << " Building vector of FedChannelConnection objects...";
79  conns.clear();
80  for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); ++icrate ) {
81  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec ) {
82  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); ++iring ) {
83  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); ++iccu ) {
84  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); ++imod ) {
85  for ( uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++ ) {
86  conns.push_back( FedChannelConnection( icrate->fecCrate(),
87  ifec->fecSlot(),
88  iring->fecRing(),
89  iccu->ccuAddr(),
90  imod->ccuChan(),
91  imod->activeApvPair( imod->lldChannel(ipair) ).first,
92  imod->activeApvPair( imod->lldChannel(ipair) ).second,
93  imod->dcuId(),
94  imod->detId(),
95  imod->nApvPairs(),
96  imod->fedCh(ipair).fedId_,
97  imod->fedCh(ipair).fedCh_,
98  imod->length(),
99  imod->dcu(),
100  imod->pll(),
101  imod->mux(),
102  imod->lld() ) );
103  uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
104  uint16_t fed_slot = imod->fedCh(ipair).fedSlot_;
105  conns.back().fedCrate( fed_crate );
106  conns.back().fedSlot( fed_slot );
107  }
108  }
109  }
110  }
111  }
112  }
113 }
const std::vector< SiStripFecCrate > & crates() const
U second(std::pair< T, U > const &p)
static const char mlCabling_[]
Class containning control, module, detector and connection information, at the level of a FED channel...
#define LogTrace(id)
#define begin
Definition: vmac.h:30
NumberOfDevices SiStripFecCabling::countDevices ( ) const

Definition at line 200 of file SiStripFecCabling.cc.

References begin, crates(), spr::find(), NumberOfDevices::nApvPairs0_, NumberOfDevices::nApvPairs1_, NumberOfDevices::nApvPairs2_, NumberOfDevices::nApvPairs3_, NumberOfDevices::nApvPairs_, NumberOfDevices::nApvPairsX_, NumberOfDevices::nApvs_, NumberOfDevices::nCcuAddrs_, NumberOfDevices::nCcuChans_, NumberOfDevices::nDcuIds_, NumberOfDevices::nDcus_, NumberOfDevices::nDetIds_, NumberOfDevices::nFecCrates_, NumberOfDevices::nFecRings_, NumberOfDevices::nFecSlots_, NumberOfDevices::nFedChans_, NumberOfDevices::nFedCrates_, NumberOfDevices::nFedIds_, NumberOfDevices::nFedSlots_, NumberOfDevices::nLlds_, NumberOfDevices::nMuxes_, and NumberOfDevices::nPlls_.

Referenced by SiStripFedCablingBuilderFromDb::buildFecCabling(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices(), SiStripFedCablingFakeESSource::make(), and ~SiStripFecCabling().

200  {
201 
202  NumberOfDevices num_of_devices; // simple container class used for counting
203 
204  std::vector<uint16_t> fed_crates;
205  std::vector<uint16_t> fed_slots;
206  std::vector<uint16_t> fed_ids;
207  for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); ++icrate ) {
208  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec ) {
209  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); ++iring ) {
210  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); ++iccu ) {
211  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); ++imod ) {
212 
213  // APVs
214  if ( imod->activeApv(32) ) { num_of_devices.nApvs_++; }
215  if ( imod->activeApv(33) ) { num_of_devices.nApvs_++; }
216  if ( imod->activeApv(34) ) { num_of_devices.nApvs_++; }
217  if ( imod->activeApv(35) ) { num_of_devices.nApvs_++; }
218  if ( imod->activeApv(36) ) { num_of_devices.nApvs_++; }
219  if ( imod->activeApv(37) ) { num_of_devices.nApvs_++; }
220  if ( imod->dcuId() ) { num_of_devices.nDcuIds_++; }
221  if ( imod->detId() ) { num_of_devices.nDetIds_++; }
222 
223  // APV pairs
224  num_of_devices.nApvPairs_ += imod->nApvPairs();
225  if ( imod->nApvPairs() == 0 ) { num_of_devices.nApvPairs0_++; }
226  else if ( imod->nApvPairs() == 1 ) { num_of_devices.nApvPairs1_++; }
227  else if ( imod->nApvPairs() == 2 ) { num_of_devices.nApvPairs2_++; }
228  else if ( imod->nApvPairs() == 3 ) { num_of_devices.nApvPairs3_++; }
229  else { num_of_devices.nApvPairsX_++; }
230 
231  // FED crates, slots, ids, channels
232  for ( uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++ ) {
233 
234  uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
235  uint16_t fed_slot = imod->fedCh(ipair).fedSlot_;
236  uint16_t fed_id = imod->fedCh(ipair).fedId_;
237 
238  if ( fed_id ) {
239 
240  num_of_devices.nFedChans_++;
241 
242  std::vector<uint16_t>::iterator icrate = find( fed_crates.begin(), fed_crates.end(), fed_crate );
243  if ( icrate == fed_crates.end() ) {
244  num_of_devices.nFedCrates_++;
245  fed_crates.push_back(fed_crate);
246  }
247 
248  std::vector<uint16_t>::iterator islot = find( fed_slots.begin(), fed_slots.end(), fed_slot );
249  if ( islot == fed_slots.end() ) {
250  num_of_devices.nFedSlots_++;
251  fed_slots.push_back(fed_slot);
252  }
253 
254  std::vector<uint16_t>::iterator ifed = find( fed_ids.begin(), fed_ids.end(), fed_id );
255  if ( ifed == fed_ids.end() ) {
256  num_of_devices.nFedIds_++;
257  fed_ids.push_back(fed_id);
258  }
259 
260  }
261 
262  }
263 
264  // FE devices
265  if ( imod->dcu() ) { num_of_devices.nDcus_++; }
266  if ( imod->mux() ) { num_of_devices.nMuxes_++; }
267  if ( imod->pll() ) { num_of_devices.nPlls_++; }
268  if ( imod->lld() ) { num_of_devices.nLlds_++; }
269 
270  // FE modules
271  num_of_devices.nCcuChans_++;
272  }
273  num_of_devices.nCcuAddrs_++;
274  }
275  num_of_devices.nFecRings_++;
276  }
277  num_of_devices.nFecSlots_++;
278  }
279  num_of_devices.nFecCrates_++;
280  }
281 
282  return num_of_devices;
283 
284 }
uint32_t nFecCrates_
const std::vector< SiStripFecCrate > & crates() const
void find(edm::Handle< EcalRecHitCollection > &hits, DetId thisDet, std::vector< EcalRecHitCollection::const_iterator > &hit, bool debug=false)
Definition: FindCaloHit.cc:20
uint32_t nApvPairs3_
uint32_t nApvPairsX_
uint32_t nApvPairs0_
Simple container class for counting devices.
uint32_t nApvPairs2_
#define begin
Definition: vmac.h:30
uint32_t nApvPairs1_
uint32_t nFedCrates_
const std::vector< SiStripFecCrate > & SiStripFecCabling::crates ( ) const
inline
std::vector< SiStripFecCrate > & SiStripFecCabling::crates ( )
inline

Definition at line 81 of file SiStripFecCabling.h.

References crates_.

81 { return crates_; }
std::vector< SiStripFecCrate > crates_
void SiStripFecCabling::dcuId ( const FedChannelConnection conn)
inline

Definition at line 90 of file SiStripFecCabling.h.

References FedChannelConnection::dcuId(), funct::m, and module().

Referenced by SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices(), and ~SiStripFecCabling().

90  {
91  auto m = module(conn);
92  if(m) {m->dcuId(conn.dcuId());}
93 }
const SiStripModule & module(const FedChannelConnection &conn) const
const uint32_t & dcuId() const
void SiStripFecCabling::detId ( const FedChannelConnection conn)
inline

Definition at line 95 of file SiStripFecCabling.h.

References FedChannelConnection::detId(), funct::m, and module().

Referenced by ~SiStripFecCabling().

95  {
96  auto m = module(conn);
97  if(m) { m->detId(conn.detId()); }
98 }
const SiStripModule & module(const FedChannelConnection &conn) const
const uint32_t & detId() const
const std::vector< SiStripFec > & SiStripFecCabling::fecs ( ) const
inline

Definition at line 84 of file SiStripFecCabling.h.

References crates_.

Referenced by connections(), and ~SiStripFecCabling().

84  {
85  const static std::vector<SiStripFec> my_fecs;
86  if ( !crates_.empty() ) { return crates_[0].fecs(); }
87  else { return my_fecs; }
88 }
std::vector< SiStripFecCrate > crates_
const SiStripModule & SiStripFecCabling::module ( const FedChannelConnection conn) const

Definition at line 165 of file SiStripFecCabling.cc.

References crates().

Referenced by dcuId(), detId(), SiStripCommissioningSource::fillCablingHistos(), module(), nApvPairs(), and ~SiStripFecCabling().

165  {
166  auto module = moduleFrom(crates(), conn);
167  if(module) {
168  return *module;
169  }
170 
171  static const SiStripModule s_module{FedChannelConnection{}};
172  return s_module;
173 }
Device and connection information at the level of a front-end module.
Definition: SiStripModule.h:24
const SiStripModule & module(const FedChannelConnection &conn) const
const std::vector< SiStripFecCrate > & crates() const
Class containning control, module, detector and connection information, at the level of a FED channel...
Definition: vlib.h:208
SiStripModule * SiStripFecCabling::module ( const FedChannelConnection conn)

Definition at line 175 of file SiStripFecCabling.cc.

References crates().

175  {
176  return moduleFrom(crates(), conn);
177 }
const std::vector< SiStripFecCrate > & crates() const
const SiStripModule & SiStripFecCabling::module ( const uint32_t &  dcu_id) const

Definition at line 182 of file SiStripFecCabling.cc.

References begin, crates(), and module().

182  {
183  for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); ++icrate ) {
184  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec ) {
185  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); ++iring ) {
186  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); ++iccu ) {
187  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); ++imod ) {
188  if ( (*imod).dcuId() == dcu_id ) { return *imod; }
189  }
190  }
191  }
192  }
193  }
194  static const SiStripModule module{FedChannelConnection{}};
195  return module;
196 }
Device and connection information at the level of a front-end module.
Definition: SiStripModule.h:24
const SiStripModule & module(const FedChannelConnection &conn) const
const std::vector< SiStripFecCrate > & crates() const
Class containning control, module, detector and connection information, at the level of a FED channel...
#define begin
Definition: vmac.h:30
Definition: vlib.h:208
void SiStripFecCabling::nApvPairs ( const FedChannelConnection conn)
inline

Definition at line 100 of file SiStripFecCabling.h.

References funct::m, module(), and FedChannelConnection::nApvPairs().

Referenced by ~SiStripFecCabling().

100  {
101  auto m = module(conn);
102  if(m) { m->nApvPairs(conn.nApvPairs()); }
103 }
const SiStripModule & module(const FedChannelConnection &conn) const
const uint16_t & nApvPairs() const
void SiStripFecCabling::print ( std::stringstream &  ss) const

Definition at line 288 of file SiStripFecCabling.cc.

References begin, crates(), cuy::ii, sistrip::invalid_, findQualityFiles::jj, and pileupDistInMC::total.

Referenced by SiStripFedCablingBuilder::beginRun(), SiStripFedCablingReader::beginRun(), operator<<(), and ~SiStripFecCabling().

288  {
289  uint32_t valid = 0;
290  uint32_t total = 0;
291  ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
292  ss << "Printing cabling for " << crates().size() << " crates" << std::endl;
293  for ( std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); ++icrate ) {
294  ss << "Printing cabling for " << icrate->fecs().size() << " FECs for crate " << icrate->fecCrate() << std::endl;
295  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec ) {
296  ss << "Printing cabling for " << ifec->rings().size() << " rings for FEC " << ifec->fecSlot() << std::endl;
297  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); ++iring ) {
298  ss << "Printing cabling for " << iring->ccus().size() << " CCUs for ring " << iring->fecRing() << std::endl;
299  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); ++iccu ) {
300  ss << "Printing cabling for " << iccu->modules().size() << " modules for CCU " << iccu->ccuAddr() << std::endl;
301  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); ++imod ) {
302 
303  SiStripModule::FedCabling conns = imod->fedChannels();
304  SiStripModule::FedCabling::const_iterator ii = conns.begin();
305  SiStripModule::FedCabling::const_iterator jj = conns.end();
306  for ( ; ii != jj; ++ii ) {
307  if ( ii->second.fedId_ != sistrip::invalid_ &&
308  ii->second.fedCh_ != sistrip::invalid_ ) { valid++; }
309  total++;
310  }
311  ss << *imod << std::endl;
312  }
313  }
314  }
315  }
316  }
317  ss << "Number of connected: " << valid << std::endl
318  << "Number of connections: " << total << std::endl;
319 }
const std::vector< SiStripFecCrate > & crates() const
ii
Definition: cuy.py:588
static const uint16_t invalid_
Definition: Constants.h:16
#define begin
Definition: vmac.h:30
std::map< uint16_t, FedChannel > FedCabling
Definition: SiStripModule.h:59
void SiStripFecCabling::terse ( std::stringstream &  ss) const

Definition at line 323 of file SiStripFecCabling.cc.

References begin, and crates().

Referenced by ~SiStripFecCabling().

323  {
324  ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
325  for ( std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); ++icrate ) {
326  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec ) {
327  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); ++iring ) {
328  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); ++iccu ) {
329  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); ++imod ) {
330  imod->terse(ss);
331  ss << std::endl;
332  }
333  }
334  }
335  }
336  }
337 }
const std::vector< SiStripFecCrate > & crates() const
#define begin
Definition: vmac.h:30

Member Data Documentation

std::vector<SiStripFecCrate> SiStripFecCabling::crates_
private

Definition at line 74 of file SiStripFecCabling.h.

Referenced by addDevices(), crates(), fecs(), and SiStripFecCabling().