zone_best3.h

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// This C++ header file was automatically generated
// by VPPC from a Verilog HDL project.
// VPPC web-page: http://www.phys.ufl.edu/~madorsky/vppc/

// Author    : madorsky
// Timestamp : Thu Mar 12 14:54:01 2015

#ifndef __zone_best3_h_file__
#define __zone_best3_h_file__
#include "vppc_sim_lib.h"
#include "zone_best.h"

class zone_best3
{
 public:
    zone_best3(){built = false; glbl_gsr = true; defparam();}
    void defparam();
    void build();
    bool built;
    bool glbl_gsr;
        unsigned station;
        unsigned cscid;
        // segments per chamber
    unsigned seg_ch;
        // bit widths of ph and th outputs, reduced precision
// have to be derived from pattern width on top level
    unsigned bw_ph;
        unsigned bw_th;
        // bit widths of ph and th, full precision
    unsigned bw_fph;
        unsigned bw_fth;
        // wiregroup input bit width (0..111)
    unsigned bw_wg;
        // bit width of dblstrip input (max 80 for ME234/1 with double-width strips)
    unsigned bw_ds;
        // width of halfstrip input
    unsigned bw_hs;
        // pattern half-width for stations 3,4
    unsigned pat_w_st3; //4;
        // pattern half-width for station 1
    unsigned pat_w_st1;
        // number of input bits for stations 3,4
    unsigned full_pat_w_st3;
        // number of input bits for st 1
    unsigned full_pat_w_st1;
        // width of zero padding for station copies
    unsigned padding_w_st1;
        unsigned padding_w_st3;
        // full pattern widths (aka reduced pattern)
    unsigned red_pat_w_st3;
        unsigned red_pat_w_st1;
        // number of folds for pattern detectors, do not set to 1
    unsigned fold;
        // number of th outputs for ME1/1
    unsigned th_ch11;
        unsigned bw_q;
        unsigned bw_addr;
        // strips per section, calculated so ph pattern would cover +/- 8 deg in st 1
    unsigned ph_raw_w; // kludge to fix synth error, need to understand
        unsigned th_raw_w;
        // max possible drifttime
    unsigned max_drift;
        // bit widths of precise phi and eta outputs
    unsigned bw_phi;
        unsigned bw_eta;
        // width of ph raw hits, max coverage +8 to cover possible chamber displacement 
    unsigned ph_hit_w; //80 + 8;
        // for 20 deg chambers
    unsigned ph_hit_w20;
        // for 10 deg chambers
    unsigned ph_hit_w10; //40 + 8;  
        // width of th raw hits, max coverage +8 to cover possible chamber displacement 
    unsigned th_hit_w;
        unsigned endcap;
        unsigned n_strips;
        unsigned n_wg;
        // theta range (take +1 because th_coverage contains max th value starting from 0)
    unsigned th_coverage;
        // phi range
    unsigned ph_coverage; //80 : 40;
        // number of th outputs takes ME1/1 th duplication into account
    unsigned th_ch;
        // is this chamber mounted in reverse direction?
    unsigned ph_reverse;
        unsigned th_mem_sz;
        unsigned th_corr_mem_sz;
        // multiplier bit width (phi + factor)
    unsigned mult_bw;
        // ph zone boundaries for chambers that cover more than one zone
// hardcoded boundaries must match boundaries in ph_th_match module
    unsigned ph_zone_bnd1;
        unsigned ph_zone_bnd2;
        unsigned zone_overlap;
        // sorter parameters
    unsigned bwr; // rank width
        unsigned bpow; // (1 << bpow) is count of input ranks
        unsigned cnr; // internal rank count
        unsigned cnrex; // actual input rank count, must be even
    
        signal_ rank_ex; // input ranks
        signal_ clk_nx; // fast clock
        signal_ winner; // winners
        signal_ wini; // winner indexes one bit longer than in internal sorters
            // delay lines for early winners
signal_storage winnerd__storage;  signal_ winnerd;
        signal_storage winid__storage;  signal_ winid;
        signal_storage winnerw__storage;  signal_ winnerw;
        signal_storage winiw__storage;  signal_ winiw;
        signal_storage valid__storage;  signal_ valid; // valid flags
    
        signal_storage rankr__storage;  signal_ rankr; // rank connections between stages
    
        unsigned j;
        unsigned i;
    
    void init ();
    void operator()
    (
    signal_& rank_ex__io,
    signal_& winner__io,
    signal_& wini__io,
    signal_& clk_nx__io
    );
    class gb__class
    {
     public:
        class zone_best_loop__class
        {
         public:
            zone_best zb;

            void init();
        };
        map <ull, zone_best_loop__class> zone_best_loop;

        void init();
    };
    gb__class gb;
};
#endif