11 union {
float flt; uint32_t i32; }
conv;
20 union {
float flt; uint32_t i32; }
conv;
26 union {
float flt; uint32_t i32; }
conv;
30 uint16_t
base2 = (
conv.i32&0x007fffff)>>12;
31 uint16_t
base = base2 >> 1;
32 if (((base2 & 1) != 0) && (base < 1023)) base++;
41 static_assert(
bits <= 23,
"max mantissa size is 23 bits");
43 union {
float flt; uint32_t i32; }
conv;
49 inline static float max() {
50 union {
float flt; uint32_t i32; }
conv;
51 conv.i32 = 0x477fe000;
57 union {
float flt; uint32_t i32; }
conv;
60 conv.i32 = (0x8f<<23) - 1;
64 inline static float min() {
65 union {
float flt; uint32_t i32; }
conv;
66 conv.i32 = 0x38800000;
72 union {
float flt; uint32_t i32; }
conv;
75 conv.i32 = (0x71<<23);
80 union {
float flt; uint32_t i32; }
conv;
81 conv.i32 = 0x33800000;
87 return ((h >> 10) & 0x1f) == 0 && (h & 0x3ff) != 0;
static uint16_t float32to16crop(float x)
Fast implementation, but it crops the number so it biases low.
static float min32RoundedToMin16()
FWCore Framework interface EventSetupRecordImplementation h
Helper function to determine trigger accepts.
static uint16_t offsettable[64]
static HepMC::IO_HEPEVT conv
How EventSelector::AcceptEvent() decides whether to accept an event for output otherwise it is excluding the probing of A single or multiple positive and the trigger will pass if any such matching triggers are PASS or EXCEPTION[A criterion thatmatches no triggers at all is detected and causes a throw.] A single negative with an expectation of appropriate bit checking in the decision bits
static float float16to32(uint16_t h)
static uint16_t basetable[512]
static float denorm_min()
static uint8_t shifttable[512]
static uint16_t float32to16(float x)
static uint32_t mantissatable[2048]
static bool isdenorm(uint16_t h)
static float max32RoundedToMax16()
static unsigned int const shift
static uint16_t float32to16round(float x)
Slower implementation, but it rounds to avoid biases.
static float reduceMantissaToNbits(const float &f)
static uint32_t exponenttable[64]