Histogram-based analysis for connection loop. More...

#include <FedCablingAlgorithm.h>

Inheritance diagram for FedCablingAlgorithm:

Public Member Functions
	FedCablingAlgorithm (const edm::ParameterSet &pset, FedCablingAnalysis *const )

const Histo &	hFedCh () const

const Histo &	hFedId () const

virtual	~FedCablingAlgorithm ()

Public Member Functions inherited from CommissioningAlgorithm
void	analysis (const std::vector< TH1 * > &)

	CommissioningAlgorithm (CommissioningAnalysis *const )

	CommissioningAlgorithm ()

virtual	~CommissioningAlgorithm ()

Private Member Functions
void	analyse ()

void	extract (const std::vector< TH1 * > &)

	FedCablingAlgorithm ()

Private Attributes
Histo	hFedCh_

Histo	hFedId_

Additional Inherited Members
Public Types inherited from CommissioningAlgorithm
typedef std::pair< TH1 *, std::string >	Histo

Protected Member Functions inherited from CommissioningAlgorithm
CommissioningAnalysis *const	anal () const

uint32_t	extractFedKey (const TH1 *const )

Detailed Description

Histogram-based analysis for connection loop.

Author: R.Bainbridge

Definition at line 16 of file FedCablingAlgorithm.h.

Constructor & Destructor Documentation

FedCablingAlgorithm::FedCablingAlgorithm	(	const edm::ParameterSet &	pset,
		FedCablingAnalysis * const	anal
	)

Definition at line 17 of file FedCablingAlgorithm.cc.

   : CommissioningAlgorithm(anal),
     hFedId_(0,""),
     hFedCh_(0,"")
 {;}

virtual FedCablingAlgorithm::~FedCablingAlgorithm ( )

inlinevirtual

Definition at line 24 of file FedCablingAlgorithm.h.

24 {;}

FedCablingAlgorithm::FedCablingAlgorithm ( )

inlineprivate

Definition at line 34 of file FedCablingAlgorithm.h.

34 {;}

Member Function Documentation

void FedCablingAlgorithm::analyse ( )

privatevirtual

Performs histogram anaysis.

Implements CommissioningAlgorithm.

Definition at line 73 of file FedCablingAlgorithm.cc.

References FedCablingAnalysis::adcLevel_, CommissioningAnalysis::addErrorCode(), CommissioningAlgorithm::anal(), FedCablingAnalysis::candidates_, SiStripFedKey::feChan(), FedCablingAnalysis::fedCh_, FedCablingAnalysis::fedId_, SiStripFedKey::feUnit(), hFedCh_, hFedId_, sistrip::invalid_, SiStripKey::key(), relval_steps::key, bookConverter::max, sistrip::mlCommissioning_, sistrip::noCandidates_, sistrip::nullPtr_, FedCablingAnalysis::threshold_, tmp, and puppiForMET_cff::weight.

                                   { 
 
   if ( !anal() ) {
     edm::LogWarning(mlCommissioning_)
       << "[FedCablingAlgorithm::" << __func__ << "]"
       << " NULL pointer to base Analysis object!";
     return; 
   }
 
   CommissioningAnalysis* tmp = const_cast<CommissioningAnalysis*>( anal() );
   FedCablingAnalysis* anal = dynamic_cast<FedCablingAnalysis*>( tmp );
   if ( !anal ) {
     edm::LogWarning(mlCommissioning_)
       << "[FedCablingAlgorithm::" << __func__ << "]"
       << " NULL pointer to derived Analysis object!";
     return; 
   }
 
   if ( !hFedId_.first ) {
     anal->addErrorCode(sistrip::nullPtr_);
     return;
   }
 
   if ( !hFedCh_.first ) {
     anal->addErrorCode(sistrip::nullPtr_);
     return;
   }
 
   TProfile* fedid_histo = dynamic_cast<TProfile*>(hFedId_.first);
   if ( !fedid_histo ) {
     anal->addErrorCode(sistrip::nullPtr_);
     return;
   }
 
   TProfile* fedch_histo = dynamic_cast<TProfile*>(hFedCh_.first);
   if ( !fedch_histo ) {
     anal->addErrorCode(sistrip::nullPtr_);
     return;
   }
 
   // Some initialization
   anal->candidates_.clear();
   float max       = -1.;
   float weight    = -1.;
   uint16_t id_val = sistrip::invalid_;
   uint16_t ch_val = sistrip::invalid_;
   
   // FED id
   max = 0.;
   for ( uint16_t ifed = 0; ifed < fedid_histo->GetNbinsX(); ifed++ ) {
     if ( fedid_histo->GetBinEntries(ifed+1) ) {
       if ( fedid_histo->GetBinContent(ifed+1) > max &&
        fedid_histo->GetBinContent(ifed+1) > FedCablingAnalysis::threshold_ ) { 
     id_val = ifed; 
     max = fedid_histo->GetBinContent(ifed+1);
       }
     }
   }
   weight = max;
 
   // FED ch
   max = 0.;
   for ( uint16_t ichan = 0; ichan < fedch_histo->GetNbinsX(); ichan++ ) {
     if ( fedch_histo->GetBinEntries(ichan+1) ) {
       if ( fedch_histo->GetBinContent(ichan+1) > max &&
        fedch_histo->GetBinContent(ichan+1) > FedCablingAnalysis::threshold_ ) { 
     ch_val = ichan; 
     max = fedch_histo->GetBinContent(ichan+1);
       }
     }
   }
   if ( max > weight ) { weight = max; }
 
   // Set "best" candidate and ADC level
   if  ( id_val != sistrip::invalid_ &&
     ch_val != sistrip::invalid_ ) {
     uint32_t key = SiStripFedKey( id_val, 
                   SiStripFedKey::feUnit(ch_val),
                   SiStripFedKey::feChan(ch_val) ).key();
     anal->candidates_[key] = static_cast<uint16_t>(weight);
     anal->fedId_ = id_val;
     anal->fedCh_ = ch_val;
     anal->adcLevel_ = weight;
   } else {
     anal->addErrorCode(sistrip::noCandidates_);
   }
 
 }

void FedCablingAlgorithm::extract ( const std::vector< TH1 * > & histos )

privatevirtual

Extracts and organises histograms.

Implements CommissioningAlgorithm.

Definition at line 25 of file FedCablingAlgorithm.cc.

References CommissioningAnalysis::addErrorCode(), CommissioningAlgorithm::anal(), CommissioningAlgorithm::extractFedKey(), sistrip::FED_CABLING, sistrip::fedChannel_, CommissioningAnalysis::fedKey(), sistrip::feDriver_, hFedCh_, hFedId_, sistrip::mlCommissioning_, sistrip::numberOfHistos_, indexGen::title, sistrip::unexpectedExtraInfo_, and sistrip::unexpectedTask_.

Referenced by BeautifulSoup.PageElement::_invert(), and BeautifulSoup.Tag::decompose().

                                                                  { 
 
   if ( !anal() ) {
     edm::LogWarning(mlCommissioning_)
       << "[FedCablingAlgorithm::" << __func__ << "]"
       << " NULL pointer to Analysis object!";
     return; 
   }
 
   // Check number of histograms
   if ( histos.size() != 2 ) {
     anal()->addErrorCode(sistrip::numberOfHistos_);
   }
 
   // Extract FED key from histo title
   if ( !histos.empty() ) { anal()->fedKey( extractFedKey( histos.front() ) ); }
 
   // Extract histograms
   std::vector<TH1*>::const_iterator ihis = histos.begin();
   for ( ; ihis != histos.end(); ihis++ ) {
     
     // Check for NULL pointer
     if ( !(*ihis) ) { continue; }
 
     // Check name
     SiStripHistoTitle title( (*ihis)->GetName() );
     if ( title.runType() != sistrip::FED_CABLING ) {
       anal()->addErrorCode(sistrip::unexpectedTask_);
       continue;
     }
     
     // Extract FED id and channel histos
     if ( title.extraInfo().find(sistrip::feDriver_) != std::string::npos ) {
       hFedId_.first = *ihis;
       hFedId_.second = (*ihis)->GetName();
     } else if ( title.extraInfo().find(sistrip::fedChannel_) != std::string::npos ) {
       hFedCh_.first = *ihis;
       hFedCh_.second = (*ihis)->GetName();
     } else { 
       anal()->addErrorCode(sistrip::unexpectedExtraInfo_);
     }
     
   }
   
 }