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L1GtHwValidation.cc
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1 
16 // this class header
17 #include "DQM/L1TMonitor/interface/L1GtHwValidation.h"
18 
19 // system include files
20 #include <memory>
21 #include <iostream>
22 #include <iomanip>
23 
24 // user include files
25 #include "DataFormats/L1GlobalTrigger/interface/L1GlobalTriggerReadoutSetup.h"
26 #include "DataFormats/L1GlobalTrigger/interface/L1GlobalTriggerReadoutRecord.h"
27 #include "DataFormats/L1GlobalTrigger/interface/L1GlobalTriggerEvmReadoutRecord.h"
28 
29 #include "FWCore/MessageLogger/interface/MessageLogger.h"
30 #include "FWCore/ServiceRegistry/interface/Service.h"
31 
32 #include "FWCore/Framework/interface/EventSetup.h"
33 #include "FWCore/Framework/interface/ESHandle.h"
34 #include "FWCore/Framework/interface/Run.h"
35 
36 #include "CondFormats/L1TObjects/interface/L1GtTriggerMenu.h"
37 #include "CondFormats/DataRecord/interface/L1GtTriggerMenuRcd.h"
38 
39 #include "CondFormats/L1TObjects/interface/L1GtPrescaleFactors.h"
40 #include "CondFormats/DataRecord/interface/L1GtPrescaleFactorsAlgoTrigRcd.h"
41 #include "CondFormats/DataRecord/interface/L1GtPrescaleFactorsTechTrigRcd.h"
42 
43 #include "CondFormats/L1TObjects/interface/L1GtTriggerMask.h"
44 #include "CondFormats/DataRecord/interface/L1GtTriggerMaskAlgoTrigRcd.h"
45 #include "CondFormats/DataRecord/interface/L1GtTriggerMaskTechTrigRcd.h"
46 
47 #include "TH1.h"
48 #include "TH2.h"
49 #include "TTree.h"
50 
51 // constructor(s)
52 L1GtHwValidation::L1GtHwValidation(const edm::ParameterSet& paramSet) :
53  //
54  // input tag for the L1 GT hardware DAQ record
55  m_l1GtDataDaqInputTag(paramSet.getParameter<edm::InputTag>(
56  "L1GtDataDaqInputTag")),
57  // input tag for the L1 GT hardware EVM record
58  m_l1GtDataEvmInputTag(paramSet.getParameter<edm::InputTag>(
59  "L1GtDataEvmInputTag")),
60  // input tag for the L1 GT emulator DAQ record
61  m_l1GtEmulDaqInputTag(paramSet.getParameter<edm::InputTag>(
62  "L1GtEmulDaqInputTag")),
63  // input tag for the L1 GT emulator EVM record
64  m_l1GtEmulEvmInputTag(paramSet.getParameter<edm::InputTag>(
65  "L1GtEmulEvmInputTag")),
66  // input tag for the L1 GCT hardware record
67  m_l1GctDataInputTag(paramSet.getParameter<edm::InputTag>(
68  "L1GctDataInputTag")),
69  //
70  m_dirName(paramSet.getUntrackedParameter("DirName", std::string(
71  "L1TEMU/GTexpert"))),
72  //
73  m_excludeCondCategTypeObject(paramSet.getParameter<std::vector<edm::ParameterSet> >(
74  "ExcludeCondCategTypeObject")),
75  //
76  m_excludeAlgoTrigByName(paramSet.getParameter<std::vector<std::string> >(
77  "ExcludeAlgoTrigByName")),
78  //
79  m_excludeAlgoTrigByBit(paramSet.getParameter<std::vector<int> >(
80  "ExcludeAlgoTrigByBit")),
81  //
82  // initialize counters
83  m_nrDataEventError(0),
84  m_nrEmulEventError(0),
85  // cache
86  m_l1GtMenuCacheID(0ULL), m_l1GtPfAlgoCacheID(0ULL),
87  m_l1GtPfTechCacheID(0ULL), m_l1GtTmAlgoCacheID(0ULL),
88  m_l1GtTmTechCacheID(0ULL),
89  //
90  m_agree(true),
91  m_dataOnly(false),
92  m_emulOnly(false),
93  m_dataOnlyMask(false),
94  m_emulOnlyMask(false),
95  //
96  m_nrEvJob(0), m_nrEvRun(0) {
97 
98 
99  for (std::vector<edm::ParameterSet>::const_iterator
100  itExclud = m_excludeCondCategTypeObject.begin();
101  itExclud != m_excludeCondCategTypeObject.end();
102  ++itExclud) {
103 
104  if (!(itExclud->getParameter<std::string> ("ExcludedCondCategory")).empty()) {
105 
106  m_excludedCondCategory.push_back(l1GtConditionCategoryStringToEnum(
107  itExclud->getParameter<std::string>("ExcludedCondCategory")));
108 
109  } else {
110  m_excludedCondCategory.push_back(CondNull);
111  }
112 
113  if (!(itExclud->getParameter<std::string>("ExcludedCondType")).empty() ) {
114 
115  m_excludedCondType.push_back(l1GtConditionTypeStringToEnum(
116  itExclud->getParameter<std::string> ("ExcludedCondType")));
117 
118  } else {
119  m_excludedCondType.push_back(TypeNull);
120  }
121 
122  if (!(itExclud->getParameter<std::string>("ExcludedL1GtObject")).empty() ) {
123 
124  m_excludedL1GtObject.push_back(l1GtObjectStringToEnum(
125  itExclud->getParameter<std::string> ("ExcludedL1GtObject")));
126 
127  } else {
128  m_excludedL1GtObject.push_back(ObjNull);
129  }
130  }
131 
132 
133  LogDebug("L1GtHwValidation")
134  << "\nInput tag for the L1 GT DAQ hardware record: "
135  << m_l1GtDataDaqInputTag
136  << "\nInput tag for the L1 GT EVM hardware record: "
137  << m_l1GtDataEvmInputTag
138  << "\nInput tag for the L1 GT DAQ emulator records: "
139  << m_l1GtEmulDaqInputTag
140  << "\nInput tag for the L1 GT EVM emulator records: "
141  << m_l1GtEmulEvmInputTag
142  << "\nInput tag for the L1 GCT hardware record: "
143  << m_l1GctDataInputTag << std::endl;
144 
145  // FIXME print in debug mode ExcludeCondCategTypeObject, ExcludeAlgoTrigByName, etc
146 
147  //set Token(-s)
148  m_l1GtDataDaqInputToken_ = consumes<L1GlobalTriggerReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtDataDaqInputTag"));
149  m_l1GtEmulDaqInputToken_ = consumes<L1GlobalTriggerReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtEmulDaqInputTag"));
150  m_l1GtDataEvmInputToken_ = consumes<L1GlobalTriggerEvmReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtDataEvmInputTag"));
151  m_l1GtEmulEvmInputToken_ = consumes<L1GlobalTriggerEvmReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtEmulEvmInputTag"));
152 }
153 
154 // destructor
155 L1GtHwValidation::~L1GtHwValidation() {
156  // empty
157 }
158 
159 // member functions
160 
161 void L1GtHwValidation::dqmBeginRun(const edm::Run& iRun, const edm::EventSetup& evSetup){
162 }
163 
164 void L1GtHwValidation::beginLuminosityBlock(const edm::LuminosityBlock& l, const edm::EventSetup& evSetup){
165  //lumisecId_->Fill(l.id().luminosityBlock());
166 }
167 
168 void L1GtHwValidation::bookHistograms(DQMStore::IBooker &ibooker, const edm::Run& iRun, const edm::EventSetup& evSetup) {
169 
170  ibooker.setCurrentFolder(m_dirName);
171 
172  // histograms
173 
174  const unsigned int numberTechTriggers = L1GlobalTriggerReadoutSetup::NumberTechnicalTriggers;
175 
176  const unsigned int numberAlgoTriggers = L1GlobalTriggerReadoutSetup::NumberPhysTriggers;
177 
178  for (int iRec = 0; iRec < NumberOfGtRecords; ++iRec) {
179 
180  std::string recString;
181  if (iRec == 0) {
182  recString = "Daq_";
183  ibooker.setCurrentFolder(m_dirName + "/DAQ/");
184 
185  } else {
186  recString = "Evm_";
187  ibooker.setCurrentFolder(m_dirName + "/EVM/");
188  }
189 
190  std::string hName;
191  const char* histName;
192 
193  hName = recString + "gtfeDataEmul";
194  histName = hName.c_str();
195 
196  // GTFE histograms
197  m_gtfeDataEmul[iRec] = ibooker.book1D(histName, "GTFE data vs emul mismatch", 8, 0., 7.);
198  m_gtfeDataEmul[iRec]->setBinLabel(1, "BoardId", 1);
199  m_gtfeDataEmul[iRec]->setBinLabel(2, "RecordLength1", 1);
200  m_gtfeDataEmul[iRec]->setBinLabel(3, "RecordLength0", 1);
201  m_gtfeDataEmul[iRec]->setBinLabel(4, "BxNr", 1);
202  m_gtfeDataEmul[iRec]->setBinLabel(5, "SetupVersion", 1);
203  m_gtfeDataEmul[iRec]->setBinLabel(6, "DaqActiveBoards", 1);
204  m_gtfeDataEmul[iRec]->setBinLabel(7, "AltNrBxBoard", 1);
205  m_gtfeDataEmul[iRec]->setBinLabel(8, "TotalTriggerNr", 1);
206 
207  // FDL histograms
208 
209  for (int iHist = 0; iHist < TotalBxInEvent; ++iHist) {
210 
211  // convert [0, TotalBxInEvent] to [-X, +X] and add to histogram name
212  int iIndex = iHist - ((TotalBxInEvent + 1) / 2 - 1);
213  int hIndex = (iIndex + 16) % 16;
214 
215  std::stringstream ss;
216  std::string str;
217  ss << std::uppercase << std::hex << hIndex;
218  ss >> str;
219 
220  if (iRec == 0) {
221  ibooker.setCurrentFolder(m_dirName + "/DAQ/BxInEvent_" + str);
222 
223  } else {
224  ibooker.setCurrentFolder(m_dirName + "/EVM/BxInEvent_" + str);
225  }
226 
227  hName = recString + "FdlDataEmul_" + str;
228  histName = hName.c_str();
229 
230  std::string hTitle = "FDL data vs emul mismatch for BxInEvent = " + str;
231  const char* histTitle = hTitle.c_str();
232 
233  //
234 
235  m_fdlDataEmul[iHist][iRec] = ibooker.book1D(histName, histTitle, 13, 0., 13.);
236  m_fdlDataEmul[iHist][iRec]->setBinLabel(1, "BoardId", 1);
237  m_fdlDataEmul[iHist][iRec]->setBinLabel(2, "BxInEvent", 1);
238  m_fdlDataEmul[iHist][iRec]->setBinLabel(3, "BxNr", 1);
239  m_fdlDataEmul[iHist][iRec]->setBinLabel(4, "EventNr", 1);
240  m_fdlDataEmul[iHist][iRec]->setBinLabel(5, "TechTrigger", 1);
241  m_fdlDataEmul[iHist][iRec]->setBinLabel(6, "TechTriggerMask", 1);
242  m_fdlDataEmul[iHist][iRec]->setBinLabel(7, "AlgoTrigger", 1);
243  m_fdlDataEmul[iHist][iRec]->setBinLabel(8, "AlgoTriggerMask", 1);
244  m_fdlDataEmul[iHist][iRec]->setBinLabel(9, "AlgoExtend", 1);
245  m_fdlDataEmul[iHist][iRec]->setBinLabel(10, "NoAlgo", 1);
246  m_fdlDataEmul[iHist][iRec]->setBinLabel(11, "FinalORAllParts", 1);
247  m_fdlDataEmul[iHist][iRec]->setBinLabel(12, "FinalORPhysPart", 1);
248  m_fdlDataEmul[iHist][iRec]->setBinLabel(13, "LocalBxNr", 1);
249 
250  // algorithm decision
251  // data
252  hName = recString + "Data_AlgoDecision_" + str;
253  histName = hName.c_str();
254 
255  hTitle = "Data: algorithm decision word for BxInEvent = " + str;
256  histTitle = hTitle.c_str();
257 
258  m_fdlDataAlgoDecision[iHist][iRec] = ibooker.book1D(histName,histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
259 
260  // emul
261  hName = recString + "Emul_AlgoDecision_" + str;
262  histName = hName.c_str();
263 
264  hTitle = "Emul: algorithm decision word for BxInEvent = " + str;
265  histTitle = hTitle.c_str();
266 
267  m_fdlEmulAlgoDecision[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
268 
269  // algorithm decision for prescaled algorithms
270  // data
271  hName = recString + "Data_AlgoDecision_Prescaled_" + str;
272  histName = hName.c_str();
273 
274  hTitle = "Data: prescaled algorithms: algorithm decision for BxInEvent = " + str;
275  histTitle = hTitle.c_str();
276 
277  m_fdlDataAlgoDecisionPrescaled[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
278 
279  // emul
280  hName = recString + "Emul_AlgoDecision_Prescaled_" + str;
281  histName = hName.c_str();
282 
283  hTitle
284  = "Emul: prescaled algorithms: algorithm decision for BxInEvent = "
285  + str;
286  histTitle = hTitle.c_str();
287 
288  m_fdlEmulAlgoDecisionPrescaled[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0.,numberAlgoTriggers);
289 
290  // algorithm decision for unprescaled algorithms
291  // data
292  hName = recString + "Data_AlgoDecision_Unprescaled_" + str;
293  histName = hName.c_str();
294 
295  hTitle
296  = "Data: unprescaled algorithms: algorithm decision for BxInEvent = "
297  + str;
298  histTitle = hTitle.c_str();
299 
300  m_fdlDataAlgoDecisionUnprescaled[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
301 
302  // emul
303  hName = recString + "Emul_AlgoDecision_Unprescaled_" + str;
304  histName = hName.c_str();
305 
306  hTitle = "Emul: unprescaled algorithms: algorithm decision for BxInEvent = " + str;
307  histTitle = hTitle.c_str();
308 
309  m_fdlEmulAlgoDecisionUnprescaled[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
310 
311  // algorithm decision after masking (partition physics)
312  // data
313  hName = recString + "Data_AlgoDecisionAfterMask_" + str;
314  histName = hName.c_str();
315 
316  hTitle = "Data, physics partition: algorithm decision word after mask for BxInEvent = " + str;
317  histTitle = hTitle.c_str();
318 
319  m_fdlDataAlgoDecisionMask[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
320 
321  // emul
322  hName = recString + "Emul_AlgoDecisionAfterMask_" + str;
323  histName = hName.c_str();
324 
325  hTitle = "Emul, physics partition: algorithm decision word after mask for BxInEvent = " + str;
326  histTitle = hTitle.c_str();
327 
328  m_fdlEmulAlgoDecisionMask[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
329 
330  //
331  hName = recString + "DataEmul_AlgoDecision_" + str;
332  histName = hName.c_str();
333 
334  hTitle = "Data vs emul: non-matching algorithm decision word for BxInEvent = " + str;
335  histTitle = hTitle.c_str();
336 
337  m_fdlDataEmulAlgoDecision[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
338 
339  //
340  hName = recString + "DataEmul_AlgoDecision_Prescaled_" + str;
341  histName = hName.c_str();
342 
343  hTitle = "Data vs emul: prescaled algorithms with non-matching decision for BxInEvent = " + str;
344  histTitle = hTitle.c_str();
345 
346  m_fdlDataEmulAlgoDecisionPrescaled[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
347 
348  //
349  hName = recString + "DataEmul_AlgoDecision_Unprescaled_" + str;
350  histName = hName.c_str();
351 
352  hTitle = "Data vs emul: unprescaled algorithms with non-matching decision for BxInEvent = " + str;
353  histTitle = hTitle.c_str();
354 
355  m_fdlDataEmulAlgoDecisionUnprescaled[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
356 
357  //
358  hName = recString + "DataEmul_AlgoDecision_Unprescaled_Allowed_" + str;
359  histName = hName.c_str();
360 
361  hTitle = "Data vs emul: unprescaled algorithms not excluded with non-matching decision for BxInEvent = " + str;
362  histTitle = hTitle.c_str();
363 
364  m_fdlDataEmulAlgoDecisionUnprescaledAllowed[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
365 
366  //
367  hName = recString + "Data_AlgoDecision_NoMatch_" + str;
368  histName = hName.c_str();
369 
370  hTitle = "Data: algorithm decision for non-matching cases for BxInEvent = " + str;
371  histTitle = hTitle.c_str();
372 
373  m_fdlDataAlgoDecision_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
374 
375  //
376  hName = recString + "Emul_AlgoDecision_NoMatch_" + str;
377  histName = hName.c_str();
378 
379  hTitle
380  = "Emul: algorithm decision for non-matching cases for BxInEvent = "
381  + str;
382  histTitle = hTitle.c_str();
383 
384  m_fdlEmulAlgoDecision_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
385 
386  // prescaled algorithms
387  hName = recString + "Data_AlgoDecision_Prescaled_NoMatch_" + str;
388  histName = hName.c_str();
389 
390  hTitle = "Data: prescaled algorithms: non-matching algorithm decision for BxInEvent = " + str;
391  histTitle = hTitle.c_str();
392 
393  m_fdlDataAlgoDecisionPrescaled_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
394 
395  //
396  hName = recString + "Emul_AlgoDecision_Prescaled_NoMatch_" + str;
397  histName = hName.c_str();
398 
399  hTitle = "Emul: prescaled algorithms: non-matching algorithm decision for BxInEvent = " + str;
400  histTitle = hTitle.c_str();
401 
402  m_fdlEmulAlgoDecisionPrescaled_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
403 
404 
405  // unprescaled algorithms - non-matching
406  hName = recString + "Data_AlgoDecision_Unprescaled_NoMatch_" + str;
407  histName = hName.c_str();
408 
409  hTitle = "Data: unprescaled algorithms: non-matching algorithm decision for BxInEvent = " + str;
410  histTitle = hTitle.c_str();
411 
412  m_fdlDataAlgoDecisionUnprescaled_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
413 
414  //
415  hName = recString + "Emul_AlgoDecision_Unprescaled_NoMatch_" + str;
416  histName = hName.c_str();
417 
418  hTitle = "Emul: unprescaled algorithms: non-matching algorithm decision for BxInEvent = " + str;
419  histTitle = hTitle.c_str();
420 
421  m_fdlEmulAlgoDecisionUnprescaled_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
422 
423 
424 
425  //
426  hName = recString + "Data_AlgoDecisionMask_NoMatch_" + str;
427  histName = hName.c_str();
428 
429  hTitle = "Data: algorithm decision for non-matching cases after mask for BxInEvent = " + str;
430  histTitle = hTitle.c_str();
431 
432  m_fdlDataAlgoDecisionMask_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
433 
434  //
435  hName = recString + "Emul_AlgoDecisionMask_NoMatch_" + str;
436  histName = hName.c_str();
437 
438  hTitle = "Emul: algorithm decision for non-matching cases after mask for BxInEvent = " + str;
439  histTitle = hTitle.c_str();
440 
441  m_fdlEmulAlgoDecisionMask_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
442 
443  // prescaled algorithms
444  hName = recString + "Data_AlgoDecisionMask_Prescaled_NoMatch_" + str;
445  histName = hName.c_str();
446 
447  hTitle = "Data: prescaled algorithms: non-matching algorithm decision after mask for BxInEvent = " + str;
448  histTitle = hTitle.c_str();
449 
450  m_fdlDataAlgoDecisionPrescaledMask_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
451 
452  //
453  hName = recString + "Emul_AlgoDecision_PrescaledMask_NoMatch_" + str;
454  histName = hName.c_str();
455 
456  hTitle = "Emul: prescaled algorithms: non-matching algorithm decision after mask for BxInEvent = " + str;
457  histTitle = hTitle.c_str();
458 
459  m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
460 
461 
462  // unprescaled algorithms - non-matching
463  hName = recString + "Data_AlgoDecision_UnprescaledMask_NoMatch_" + str;
464  histName = hName.c_str();
465 
466  hTitle = "Data: unprescaled algorithms: non-matching algorithm decision after mask for BxInEvent = " + str;
467  histTitle = hTitle.c_str();
468 
469  m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
470 
471  //
472  hName = recString + "Emul_AlgoDecision_UnprescaledMask_NoMatch_" + str;
473  histName = hName.c_str();
474 
475  hTitle
476  = "Emul: unprescaled algorithms: non-matching algorithm decision after mask for BxInEvent = "
477  + str;
478  histTitle = hTitle.c_str();
479 
480  m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
481 
482 
483 
484  //
485  hName = recString + "DataEmul_AlgoDecisionAfterMask_" + str;
486  histName = hName.c_str();
487 
488  hTitle = "Data vs emul, physics partition: non-matching algorithm decision word after mask for BxInEvent = " + str;
489  histTitle = hTitle.c_str();
490 
491  m_fdlDataEmulAlgoDecisionMask[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
492 
493  // technical trigger decision
494  // data
495  hName = recString + "Data_TechDecision_" + str;
496  histName = hName.c_str();
497 
498  hTitle = "Data technical trigger decision word for BxInEvent = " + str;
499  histTitle = hTitle.c_str();
500 
501  m_fdlDataTechDecision[iHist][iRec] = ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
502 
503  // emul
504  hName = recString + "Emul_TechDecision_" + str;
505  histName = hName.c_str();
506 
507  hTitle = "Emul: technical trigger decision word for BxInEvent = " + str;
508  histTitle = hTitle.c_str();
509 
510  m_fdlEmulTechDecision[iHist][iRec] = ibooker.book1D(histName,histTitle, numberTechTriggers, 0., numberTechTriggers);
511 
512  // technical trigger decision after masking (partition physics)
513  hName = recString + "Data_TechDecisionAfterMask_" + str;
514  histName = hName.c_str();
515 
516  hTitle = "Data technical trigger decision word after mask for BxInEvent = " + str;
517  histTitle = hTitle.c_str();
518 
519  m_fdlDataTechDecisionMask[iHist][iRec] = ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
520 
521  //
522  hName = recString + "Emul_TechDecisionAfterMask_" + str;
523  histName = hName.c_str();
524 
525  hTitle
526  = "Emul: technical trigger decision word after mask for BxInEvent = "
527  + str;
528  histTitle = hTitle.c_str();
529 
530  m_fdlEmulTechDecisionMask[iHist][iRec] = ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
531 
532  //
533  hName = recString + "DataEmul_TechDecision_" + str;
534  histName = hName.c_str();
535 
536  hTitle = "Data vs emul: non-matching technical trigger decision word for BxInEvent = " + str;
537  histTitle = hTitle.c_str();
538 
539  m_fdlDataEmulTechDecision[iHist][iRec] = ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
540 
541  hName = recString + "DataEmul_TechDecisionAfterMask_" + str;
542  histName = hName.c_str();
543 
544  hTitle = "Data vs emul: non-matching technical trigger decision word after mask for BxInEvent = " + str;
545  histTitle = hTitle.c_str();
546 
547  m_fdlDataEmulTechDecisionMask[iHist][iRec] = ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
548 
549  }
550 
551  if (iRec == 0) {
552  ibooker.setCurrentFolder(m_dirName + "/DAQ/");
553 
554  } else {
555  ibooker.setCurrentFolder(m_dirName + "/EVM/");
556  }
557 
558  hName = recString + "FdlDataEmul_Err";
559  histName = hName.c_str();
560 
561  m_fdlDataEmul_Err[iRec] = ibooker.book1D(histName, "FDL data vs emul mismatch for non-matching BxInEvent in FDL payload", 13, 0., 13.);
562  m_fdlDataEmul_Err[iRec]->setBinLabel(1, "BoardId", 1);
563  m_fdlDataEmul_Err[iRec]->setBinLabel(2, "BxInEvent", 1);
564  m_fdlDataEmul_Err[iRec]->setBinLabel(3, "BxNr", 1);
565  m_fdlDataEmul_Err[iRec]->setBinLabel(4, "EventNr", 1);
566  m_fdlDataEmul_Err[iRec]->setBinLabel(5, "TechTrigger", 1);
567  m_fdlDataEmul_Err[iRec]->setBinLabel(6, "TechTriggerMask", 1);
568  m_fdlDataEmul_Err[iRec]->setBinLabel(7, "AlgoTrigger", 1);
569  m_fdlDataEmul_Err[iRec]->setBinLabel(8, "AlgoTriggerMask", 1);
570  m_fdlDataEmul_Err[iRec]->setBinLabel(9, "AlgoExtend", 1);
571  m_fdlDataEmul_Err[iRec]->setBinLabel(10, "NoAlgo", 1);
572  m_fdlDataEmul_Err[iRec]->setBinLabel(11, "FinalORAllParts", 1);
573  m_fdlDataEmul_Err[iRec]->setBinLabel(12, "FinalORPhysPart", 1);
574  m_fdlDataEmul_Err[iRec]->setBinLabel(13, "LocalBxNr", 1);
575 
576  hName = recString + "FdlDataAlgoDecision_Err";
577  histName = hName.c_str();
578 
579  m_fdlDataAlgoDecision_Err[iRec] = ibooker.book1D(histName, "Data: algorithm trigger decision word, non-matching BxInEvent", numberAlgoTriggers, 0., numberAlgoTriggers);
580 
581  //
582  hName = recString + "Emul_AlgoDecision_Err";
583  histName = hName.c_str();
584 
585  m_fdlEmulAlgoDecision_Err[iRec] = ibooker.book1D(histName, "Emul: algorithm trigger decision word, non-matching BxInEvent", numberAlgoTriggers, 0., numberAlgoTriggers);
586 
587  hName = recString + "DataEmul_AlgoDecision_Err";
588  histName = hName.c_str();
589 
590  m_fdlDataEmulAlgoDecision_Err[iRec] = ibooker.book1D(histName, "Data vs emul: algorithm trigger decision word, non-matching BxInEvent", numberAlgoTriggers, 0., numberAlgoTriggers);
591 
592  //
593  hName = recString + "Data_TechDecision_Err";
594  histName = hName.c_str();
595 
596  m_fdlDataTechDecision_Err[iRec] = ibooker.book1D(histName, "Data: technical trigger decision word, non-matching BxInEvent", numberTechTriggers, 0., numberTechTriggers);
597 
598  hName = recString + "Emul_TechDecision_Err";
599  histName = hName.c_str();
600 
601  m_fdlEmulTechDecision_Err[iRec] = ibooker.book1D(histName, "Emul: technical trigger decision word, non-matching BxInEvent", numberTechTriggers, 0., numberTechTriggers);
602 
603  hName = recString + "DataEmul_TechDecision_Err";
604  histName = hName.c_str();
605 
606  m_fdlDataEmulTechDecision_Err[iRec] = ibooker.book1D(histName, "Data vs emul: technical trigger decision word, non-matching BxInEvent", numberTechTriggers, 0., numberTechTriggers);
607 
608  }
609 
610  ibooker.setCurrentFolder(m_dirName);
611 
612  //
613  m_excludedAlgorithmsAgreement = ibooker.book1D("ExcludedAlgorithmsFromAgreement", "Algorithms excluded from data versus emulator agreement flag", numberAlgoTriggers, 0., numberAlgoTriggers);
614 
615  //
616 
617  m_gtErrorFlag = ibooker.book1D("GTErrorFlag", "L1 GT error flag for data versus emulator comparison", 5, 0., 5);
618 
619  m_gtErrorFlag->setBinLabel(1, "Agree", 1);
620  m_gtErrorFlag->setBinLabel(2, "", 1);
621  m_gtErrorFlag->setBinLabel(3, "", 1);
622  m_gtErrorFlag->setBinLabel(4, "Data only", 1);
623  m_gtErrorFlag->setBinLabel(5, "Emul only", 1);
624 
625 
626  m_nrEvRun = 0;
627 
628  // get / update the trigger menu from the EventSetup
629  // local cache & check on cacheIdentifier
630 
631  unsigned long long l1GtMenuCacheID =
632  evSetup.get<L1GtTriggerMenuRcd>().cacheIdentifier();
633 
634  if (m_l1GtMenuCacheID != l1GtMenuCacheID) {
635 
636  edm::ESHandle<L1GtTriggerMenu> l1GtMenu;
637  evSetup.get<L1GtTriggerMenuRcd>().get(l1GtMenu);
638  m_l1GtMenu = l1GtMenu.product();
639 
640  // compute the list of algorithms excluded from the computing of the agreement flag
641  m_excludedAlgoList.clear();
642  excludedAlgoList();
643 
644  m_l1GtMenuCacheID = l1GtMenuCacheID;
645 
646  }
647 
648 
649 
650  // FIXME when the menu changes, make a copy of histograms, and clear the old one
651  // otherwise the labels are wrong
652 
653  LogDebug("L1GtHwValidation") << "\nUsing L1 menu: \n "
654  << m_l1GtMenu->gtTriggerMenuImplementation() << "\n"
655  << std::endl;
656 
657  const AlgorithmMap& algorithmMap = m_l1GtMenu->gtAlgorithmMap();
658 
659  for (CItAlgo itAlgo = algorithmMap.begin(); itAlgo != algorithmMap.end(); itAlgo++) {
660 
661  const int algBitNumber = (itAlgo->second).algoBitNumber();
662 
663  std::stringstream ss;
664  std::string algBitString;
665  ss << std::uppercase << algBitNumber;
666  ss >> algBitString;
667 
668  const std::string& aName = algBitString + " " + itAlgo->first;
669  const char* algName = aName.c_str();
670 
671  for (int iRec = 0; iRec < NumberOfGtRecords; ++iRec) {
672  for (int iBxInEvent = 0; iBxInEvent < TotalBxInEvent; ++iBxInEvent) {
673 
674 
675  // convert [0, TotalBxInEvent] to [-X, +X]
676  int iIndex = iBxInEvent - ((TotalBxInEvent + 1) / 2 - 1);
677  int hIndex = (iIndex + 16) % 16;
678 
679  std::stringstream ss;
680  std::string str;
681  ss << std::uppercase << std::hex << hIndex;
682  ss >> str;
683 
684  if (iRec == 0) {
685  //if (m_dbe) {
686  ibooker.setCurrentFolder(m_dirName + "/DAQ/BxInEvent_" + str);
687  //}
688 
689  } else {
690  //if (m_dbe) {
691  ibooker.setCurrentFolder(m_dirName + "/EVM/BxInEvent_" + str);
692  //}
693  }
694 
695 
696  m_fdlDataAlgoDecision[iBxInEvent][iRec]->setBinLabel(
697  algBitNumber + 1, algName, 1);
698  m_fdlDataAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(
699  algBitNumber + 1, algName, 1);
700  m_fdlDataAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(
701  algBitNumber + 1, algName, 1);
702  m_fdlDataAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(
703  algBitNumber + 1, algName, 1);
704  m_fdlDataAlgoDecision_NoMatch[iBxInEvent][iRec]->setBinLabel(
705  algBitNumber + 1, algName, 1);
706 
707  m_fdlEmulAlgoDecision[iBxInEvent][iRec]->setBinLabel(
708  algBitNumber + 1, algName, 1);
709  m_fdlEmulAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(
710  algBitNumber + 1, algName, 1);
711  m_fdlEmulAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(
712  algBitNumber + 1, algName, 1);
713  m_fdlEmulAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(
714  algBitNumber + 1, algName, 1);
715  m_fdlEmulAlgoDecision_NoMatch[iBxInEvent][iRec]->setBinLabel(
716  algBitNumber + 1, algName, 1);
717 
718  m_fdlDataEmulAlgoDecision[iBxInEvent][iRec]->setBinLabel(
719  algBitNumber + 1, algName, 1);
720  m_fdlDataEmulAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(
721  algBitNumber + 1, algName, 1);
722  m_fdlDataEmulAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(
723  algBitNumber + 1, algName, 1);
724  m_fdlDataEmulAlgoDecisionUnprescaledAllowed[iBxInEvent][iRec]->setBinLabel(
725  algBitNumber + 1, algName, 1);
726  m_fdlDataEmulAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(
727  algBitNumber + 1, algName, 1);
728  }
729 
730 
731  if (iRec == 0) {
732  ibooker.setCurrentFolder(m_dirName + "/DAQ/");
733 
734  } else {
735  ibooker.setCurrentFolder(m_dirName + "/EVM/");
736  }
737 
738 
739  m_fdlDataAlgoDecision_Err[iRec]->setBinLabel(algBitNumber + 1, algName, 1);
740 
741  m_fdlEmulAlgoDecision_Err[iRec]->setBinLabel(algBitNumber + 1, algName, 1);
742 
743  m_fdlDataEmulAlgoDecision_Err[iRec]->setBinLabel(algBitNumber + 1, algName, 1);
744  }
745 
746  //
747  for (std::vector<int>::const_iterator itAlgo = m_excludedAlgoList.begin(); itAlgo!= m_excludedAlgoList.end(); ++itAlgo) {
748 
749  if (algBitNumber == *itAlgo) {
750  m_excludedAlgorithmsAgreement->setBinLabel(algBitNumber + 1, algName, 1);
751  }
752  }
753 
754 
755  }
756 
757  // get / update the prescale factors from the EventSetup
758  // local cache & check on cacheIdentifier
759 
760  unsigned long long l1GtPfAlgoCacheID = evSetup.get<
761  L1GtPrescaleFactorsAlgoTrigRcd>().cacheIdentifier();
762 
763  if (m_l1GtPfAlgoCacheID != l1GtPfAlgoCacheID) {
764 
765  edm::ESHandle<L1GtPrescaleFactors> l1GtPfAlgo;
766  evSetup.get<L1GtPrescaleFactorsAlgoTrigRcd>().get(l1GtPfAlgo);
767  m_l1GtPfAlgo = l1GtPfAlgo.product();
768 
769  m_prescaleFactorsAlgoTrig = &(m_l1GtPfAlgo->gtPrescaleFactors());
770 
771  m_l1GtPfAlgoCacheID = l1GtPfAlgoCacheID;
772 
773  }
774 
775  unsigned long long l1GtPfTechCacheID = evSetup.get<
776  L1GtPrescaleFactorsTechTrigRcd>().cacheIdentifier();
777 
778  if (m_l1GtPfTechCacheID != l1GtPfTechCacheID) {
779 
780  edm::ESHandle<L1GtPrescaleFactors> l1GtPfTech;
781  evSetup.get<L1GtPrescaleFactorsTechTrigRcd>().get(l1GtPfTech);
782  m_l1GtPfTech = l1GtPfTech.product();
783 
784  m_prescaleFactorsTechTrig = &(m_l1GtPfTech->gtPrescaleFactors());
785 
786  m_l1GtPfTechCacheID = l1GtPfTechCacheID;
787 
788  }
789 
790  // get / update the trigger mask from the EventSetup
791  // local cache & check on cacheIdentifier
792 
793  unsigned long long l1GtTmAlgoCacheID = evSetup.get<
794  L1GtTriggerMaskAlgoTrigRcd>().cacheIdentifier();
795 
796  if (m_l1GtTmAlgoCacheID != l1GtTmAlgoCacheID) {
797 
798  edm::ESHandle<L1GtTriggerMask> l1GtTmAlgo;
799  evSetup.get<L1GtTriggerMaskAlgoTrigRcd>().get(l1GtTmAlgo);
800  m_l1GtTmAlgo = l1GtTmAlgo.product();
801 
802  m_triggerMaskAlgoTrig = m_l1GtTmAlgo->gtTriggerMask();
803 
804  m_l1GtTmAlgoCacheID = l1GtTmAlgoCacheID;
805 
806  }
807 
808  unsigned long long l1GtTmTechCacheID = evSetup.get<
809  L1GtTriggerMaskTechTrigRcd>().cacheIdentifier();
810 
811  if (m_l1GtTmTechCacheID != l1GtTmTechCacheID) {
812 
813  edm::ESHandle<L1GtTriggerMask> l1GtTmTech;
814  evSetup.get<L1GtTriggerMaskTechTrigRcd>().get(l1GtTmTech);
815  m_l1GtTmTech = l1GtTmTech.product();
816 
817  m_triggerMaskTechTrig = m_l1GtTmTech->gtTriggerMask();
818 
819  m_l1GtTmTechCacheID = l1GtTmTechCacheID;
820 
821  }
822 
823 }
824 
825 //compare the GTFE board
826 void L1GtHwValidation::compareGTFE(const edm::Event& iEvent,
827  const edm::EventSetup& evSetup, const L1GtfeWord& gtfeBlockData,
828  const L1GtfeWord& gtfeBlockEmul, const int iRec) {
829 
830  std::string recString;
831  if (gtfeBlockData == gtfeBlockEmul) {
832  m_myCoutStream << "\n" << recString
833  << " Data and emulated GTFE blocks: identical.\n";
834  gtfeBlockData.print(m_myCoutStream);
835  } else {
836  m_myCoutStream << "\n" << recString
837  << " Data and emulated GTFE blocks: different.\n";
838 
839  m_myCoutStream << "\nData: GTFE block\n";
840  gtfeBlockData.print(m_myCoutStream);
841 
842  m_myCoutStream << "\nEmul: GTFE block\n";
843  gtfeBlockEmul.print(m_myCoutStream);
844 
845  }
846 
847  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
848 
849  m_myCoutStream.str("");
850  m_myCoutStream.clear();
851 
852  // get BoardId value
853  const boost::uint16_t boardIdData = gtfeBlockData.boardId();
854  const boost::uint16_t boardIdEmul = gtfeBlockEmul.boardId();
855 
856  if (boardIdData == boardIdEmul) {
857  m_myCoutStream << "\n" << recString
858  << " Data and emulated GTFE boardId identical.";
859  m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4)
860  << std::setfill('0') << boardIdData << std::setfill(' ')
861  << std::dec;
862  m_myCoutStream << "\n";
863 
864  } else {
865  m_myCoutStream << "\n" << recString
866  << " Data and emulated GTFE boardId different.";
867  m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x"
868  << std::setw(4) << std::setfill('0') << boardIdData
869  << std::setfill(' ') << std::dec;
870  m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x"
871  << std::setw(4) << std::setfill('0') << boardIdEmul
872  << std::setfill(' ') << std::dec;
873  m_myCoutStream << "\n";
874  m_gtfeDataEmul[iRec]->Fill(0);
875 
876  }
877 
879  const boost::uint16_t recordLength1Data = gtfeBlockData.recordLength1();
880  const boost::uint16_t recordLength1Emul = gtfeBlockEmul.recordLength1();
881 
882  if (recordLength1Data == recordLength1Emul) {
883  m_myCoutStream << "\n" << recString
884  << " Data and emulated GTFE recordLength for alternative 1 identical.";
885  m_myCoutStream << "\n recordLength1() = " << recordLength1Data;
886  m_myCoutStream << "\n";
887 
888  } else {
889  m_myCoutStream << "\n" << recString
890  << " Data and emulated GTFE recordLength for alternative 1 different.";
891  m_myCoutStream << "\n Data: recordLength1() = " << recordLength1Data;
892  m_myCoutStream << "\n Emul: recordLength1() = " << recordLength1Emul;
893  m_myCoutStream << "\n";
894  m_gtfeDataEmul[iRec]->Fill(1);
895 
896  }
897 
899  const boost::uint16_t recordLengthData = gtfeBlockData.recordLength();
900  const boost::uint16_t recordLengthEmul = gtfeBlockEmul.recordLength();
901 
902  if (recordLengthData == recordLengthEmul) {
903  m_myCoutStream << "\n" << recString
904  << " Data and emulated GTFE recordLength for alternative 0 identical.";
905  m_myCoutStream << "\n recordLength() = " << recordLengthData;
906  m_myCoutStream << "\n";
907 
908  } else {
909  m_myCoutStream << "\n" << recString
910  << " Data and emulated GTFE recordLength for alternative 1 different.";
911  m_myCoutStream << "\n Data: recordLength() = " << recordLengthData;
912  m_myCoutStream << "\n Emul: recordLength() = " << recordLengthEmul;
913  m_myCoutStream << "\n";
914  m_gtfeDataEmul[iRec]->Fill(2);
915 
916  }
917 
919  const boost::uint16_t bxNrData = gtfeBlockData.bxNr();
920  const boost::uint16_t bxNrEmul = gtfeBlockEmul.bxNr();
921 
922  if (bxNrData == bxNrEmul) {
923  m_myCoutStream << "\n" << recString
924  << " Data and emulated GTFE bxNr identical.";
925  m_myCoutStream << "\n bxNr() = " << bxNrData;
926  m_myCoutStream << "\n";
927 
928  } else {
929  m_myCoutStream << "\n" << recString
930  << " Data and emulated GTFE bxNr different.";
931  m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
932  m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
933  m_myCoutStream << "\n";
934  m_gtfeDataEmul[iRec]->Fill(3);
935 
936  }
937 
939  const boost::uint32_t setupVersionData = gtfeBlockData.setupVersion();
940  const boost::uint32_t setupVersionEmul = gtfeBlockEmul.setupVersion();
941 
942  if (setupVersionData == setupVersionEmul) {
943  m_myCoutStream << "\n" << recString
944  << " Data and emulated GTFE setupVersion identical.";
945  m_myCoutStream << "\n setupVersion() = " << setupVersionData;
946  m_myCoutStream << "\n";
947 
948  } else {
949  m_myCoutStream << "\n" << recString
950  << " Data and emulated GTFE setupVersion different.";
951  m_myCoutStream << "\n Data: setupVersion() = " << setupVersionData;
952  m_myCoutStream << "\n Emul: setupVersion() = " << setupVersionEmul;
953  m_myCoutStream << "\n";
954  m_gtfeDataEmul[iRec]->Fill(4);
955 
956  }
957 
959  const boost::uint16_t activeBoardsData = gtfeBlockData.activeBoards();
960  const boost::uint16_t activeBoardsEmul = gtfeBlockEmul.activeBoards();
961 
962  if (activeBoardsData == activeBoardsEmul) {
963  m_myCoutStream << "\n" << recString
964  << " Data and emulated GTFE activeBoards identical.";
965  m_myCoutStream << "\n activeBoards() = " << std::hex << "0x"
966  << std::setw(4) << std::setfill('0') << activeBoardsData
967  << std::setfill(' ') << std::dec;
968  m_myCoutStream << "\n";
969 
970  } else {
971  m_myCoutStream << "\n" << recString
972  << " Data and emulated GTFE activeBoards different.";
973  m_myCoutStream << "\n Data: activeBoards() = " << std::hex << "0x"
974  << std::setw(4) << std::setfill('0') << activeBoardsData
975  << std::setfill(' ') << std::dec;
976  m_myCoutStream << "\n Emul: activeBoards() = " << std::hex << "0x"
977  << std::setw(4) << std::setfill('0') << activeBoardsEmul
978  << std::setfill(' ') << std::dec;
979  m_myCoutStream << "\n";
980  m_gtfeDataEmul[iRec]->Fill(5);
981 
982  }
987  const boost::uint16_t altNrBxBoardData = gtfeBlockData.altNrBxBoard();
988  const boost::uint16_t altNrBxBoardEmul = gtfeBlockEmul.altNrBxBoard();
989 
990  if (altNrBxBoardData == altNrBxBoardEmul) {
991  m_myCoutStream << "\n" << recString
992  << " Data and emulated GTFE altNrBxBoard identical.";
993  m_myCoutStream << "\n altNrBxBoard() = " << altNrBxBoardData;
994  m_myCoutStream << "\n";
995 
996  } else {
997  m_myCoutStream << "\n" << recString
998  << " Data and emulated GTFE altNrBxBoard different.";
999  m_myCoutStream << "\n Data: altNrBxBoard() = " << altNrBxBoardData;
1000  m_myCoutStream << "\n Emul: altNrBxBoard() = " << altNrBxBoardEmul;
1001  m_myCoutStream << "\n";
1002  m_gtfeDataEmul[iRec]->Fill(6);
1003 
1004  }
1005 
1007  const boost::uint32_t totalTriggerNrData = gtfeBlockData.totalTriggerNr();
1008  const boost::uint32_t totalTriggerNrEmul = gtfeBlockEmul.totalTriggerNr();
1009 
1010  if (totalTriggerNrData == totalTriggerNrEmul) {
1011  m_myCoutStream << "\n" << recString
1012  << " Data and emulated GTFE totalTriggerNr identical.";
1013  m_myCoutStream << "\n totalTriggerNr() = " << totalTriggerNrData;
1014  m_myCoutStream << "\n";
1015 
1016  } else {
1017  m_myCoutStream << "\n" << recString
1018  << " Data and emulated GTFE totalTriggerNr different.";
1019  m_myCoutStream << "\n Data: totalTriggerNr() = " << totalTriggerNrData;
1020  m_myCoutStream << "\n Emul: totalTriggerNr() = " << totalTriggerNrEmul;
1021  m_myCoutStream << "\n";
1022  m_gtfeDataEmul[iRec]->Fill(7);
1023 
1024  }
1025 
1026  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1027  m_myCoutStream.str("");
1028  m_myCoutStream.clear();
1029 
1030 }
1031 
1032 //compare the FDL board
1033 void L1GtHwValidation::compareFDL(const edm::Event& iEvent,
1034  const edm::EventSetup& evSetup, const L1GtFdlWord& fdlBlockData,
1035  const L1GtFdlWord& fdlBlockEmul, const int iRec) {
1036 
1037  // index of physics partition
1038  int PhysicsPartition = 0;
1039 
1040  //
1041  std::string recString;
1042 
1043  if (fdlBlockData == fdlBlockEmul) {
1044  m_myCoutStream << "\n" << recString
1045  << " Data and emulated FDL blocks: identical.\n";
1046  fdlBlockData.print(m_myCoutStream);
1047 
1048  } else {
1049  m_myCoutStream << "\n" << recString
1050  << " Data and emulated FDL blocks: different.\n";
1051 
1052  m_myCoutStream << "\nData: FDL block\n";
1053  fdlBlockData.print(m_myCoutStream);
1054 
1055  m_myCoutStream << "\nEmul: FDL block\n";
1056  fdlBlockEmul.print(m_myCoutStream);
1057 
1058  }
1059 
1060  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1061 
1062  m_myCoutStream.str("");
1063  m_myCoutStream.clear();
1064 
1065  // get bunch cross in the GT event record -
1066  // move it first as histograms are BxInEvent dependent
1067  const int bxInEventData = fdlBlockData.bxInEvent();
1068  const int bxInEventEmul = fdlBlockEmul.bxInEvent();
1069 
1070  bool matchBxInEvent = false;
1071 
1072  if (bxInEventData == bxInEventEmul) {
1073  m_myCoutStream << "\n" << recString
1074  << " Data and emulated FDL bxInEvent identical.";
1075  m_myCoutStream << "\n bxInEvent() = " << bxInEventData;
1076  m_myCoutStream << "\n";
1077  matchBxInEvent = true;
1078 
1079  } else {
1080  m_myCoutStream << "\n" << recString
1081  << " Data and emulated FDL bxInEvent different.";
1082  m_myCoutStream << "\n Data: bxInEvent() = " << bxInEventData;
1083  m_myCoutStream << "\n Emul: bxInEvent() = " << bxInEventEmul;
1084  m_myCoutStream << "\n";
1085 
1086  m_fdlDataEmul_Err[iRec]->Fill(1);
1087 
1088  if (iRec == 0) {
1089  m_agree = false;
1090 
1091  m_myCoutStream << "\nDisagreement data versus emulator: "
1092  << "\n Data and emulated FDL bxInEvent different \n";
1093  }
1094 
1095  }
1096 
1097  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1098  m_myCoutStream.str("");
1099  m_myCoutStream.clear();
1100 
1101  // symmetrize
1102  bool validBxInEvent = false;
1103  int histIndex = bxInEventData + (TotalBxInEvent + 1) / 2 - 1;
1104  LogDebug("L1GtHwValidation") << "\n Convert bxInEvent = " << bxInEventData
1105  << " to histIndex = " << histIndex << std::endl;
1106  if ((histIndex <= TotalBxInEvent) && (histIndex >= 0)) {
1107  validBxInEvent = true;
1108  }
1109 
1110  // loop over algorithms and increase the corresponding counters
1111 
1112  // get BoardId value
1113  const boost::uint16_t boardIdData = fdlBlockData.boardId();
1114  const boost::uint16_t boardIdEmul = fdlBlockEmul.boardId();
1115 
1116  if (boardIdData == boardIdEmul) {
1117  m_myCoutStream << "\n" << recString
1118  << " Data and emulated FDL boardId identical.";
1119  m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4)
1120  << std::setfill('0') << boardIdData << std::setfill(' ')
1121  << std::dec;
1122  m_myCoutStream << "\n";
1123 
1124  } else {
1125  m_myCoutStream << "\n" << recString
1126  << " Data and emulated FDL boardId different.";
1127  m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x"
1128  << std::setw(4) << std::setfill('0') << boardIdData
1129  << std::setfill(' ') << std::dec;
1130  m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x"
1131  << std::setw(4) << std::setfill('0') << boardIdEmul
1132  << std::setfill(' ') << std::dec;
1133  m_myCoutStream << "\n";
1134 
1135  if (matchBxInEvent && validBxInEvent) {
1136  m_fdlDataEmul[histIndex][iRec]->Fill(0);
1137  } else {
1138  m_fdlDataEmul_Err[iRec]->Fill(0);
1139  }
1140 
1141  }
1142 
1143  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1144  m_myCoutStream.str("");
1145  m_myCoutStream.clear();
1146 
1147  // get BxNr - bunch cross number of the actual bx
1148  const boost::uint16_t bxNrData = fdlBlockData.bxNr();
1149  const boost::uint16_t bxNrEmul = fdlBlockEmul.bxNr();
1150 
1151  if (bxNrData == bxNrEmul) {
1152  m_myCoutStream << "\n" << recString
1153  << " Data and emulated FDL bxNr identical.";
1154  m_myCoutStream << "\n bxNr() = " << bxNrData;
1155  m_myCoutStream << "\n";
1156 
1157  } else {
1158  m_myCoutStream << "\n" << recString
1159  << " Data and emulated FDL bxNr different.";
1160  m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
1161  m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
1162  m_myCoutStream << "\n";
1163 
1164  if (matchBxInEvent && validBxInEvent) {
1165  m_fdlDataEmul[histIndex][iRec]->Fill(2);
1166  } else {
1167  m_fdlDataEmul_Err[iRec]->Fill(2);
1168  }
1169  }
1170 
1171  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1172  m_myCoutStream.str("");
1173  m_myCoutStream.clear();
1174 
1175  // get event number since last L1 reset generated in FDL
1176  const boost::uint32_t eventNrData = fdlBlockData.eventNr();
1177  const boost::uint32_t eventNrEmul = fdlBlockEmul.eventNr();
1178 
1179  if (eventNrData == eventNrEmul) {
1180  m_myCoutStream << "\n" << recString
1181  << " Data and emulated FDL eventNr identical.";
1182  m_myCoutStream << "\n eventNr() = " << eventNrData;
1183  m_myCoutStream << "\n";
1184 
1185  } else {
1186  m_myCoutStream << "\n" << recString
1187  << " Data and emulated FDL eventNr different.";
1188  m_myCoutStream << "\n Data: eventNr() = " << eventNrData;
1189  m_myCoutStream << "\n Emul: eventNr() = " << eventNrEmul;
1190  m_myCoutStream << "\n";
1191 
1192  if (matchBxInEvent && validBxInEvent) {
1193  m_fdlDataEmul[histIndex][iRec]->Fill(3);
1194  } else {
1195  m_fdlDataEmul_Err[iRec]->Fill(3);
1196  }
1197 
1198  }
1199 
1200  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1201  m_myCoutStream.str("");
1202  m_myCoutStream.clear();
1203 
1204  // get technical trigger bits
1205  const TechnicalTriggerWord& gtTechnicalTriggerWordData =
1206  fdlBlockData.gtTechnicalTriggerWord();
1207  const TechnicalTriggerWord& gtTechnicalTriggerWordEmul =
1208  fdlBlockEmul.gtTechnicalTriggerWord();
1209 
1210  int nTechBits = gtTechnicalTriggerWordData.size();
1211 
1212  TechnicalTriggerWord gtTechnicalTriggerWordDataMask(nTechBits);
1213  TechnicalTriggerWord gtTechnicalTriggerWordEmulMask(nTechBits);
1214 
1215  unsigned int bitValue = 0;
1216 
1217  if (matchBxInEvent && validBxInEvent) {
1218  for (int iBit = 0; iBit < nTechBits; ++iBit) {
1219 
1220  unsigned int triggerMask = (m_triggerMaskTechTrig.at(iBit)) & (1
1221  << PhysicsPartition);
1222 
1223  if (gtTechnicalTriggerWordData[iBit]) {
1224  m_fdlDataTechDecision[histIndex][iRec]->Fill(iBit);
1225 
1226  bitValue = (triggerMask) ? 0 : 1;
1227  gtTechnicalTriggerWordDataMask[iBit] = bitValue;
1228  if (bitValue) {
1229  m_fdlDataTechDecisionMask[histIndex][iRec]->Fill(iBit);
1230  }
1231  }
1232 
1233  if (gtTechnicalTriggerWordEmul.at(iBit)) {
1234  m_fdlEmulTechDecision[histIndex][iRec]->Fill(iBit);
1235 
1236  bitValue = (triggerMask) ? 0 : 1;
1237  gtTechnicalTriggerWordEmulMask[iBit] = bitValue;
1238  if (bitValue) {
1239  m_fdlEmulTechDecisionMask[histIndex][iRec]->Fill(iBit);
1240  }
1241  }
1242  }
1243  } else {
1244  for (int iBit = 0; iBit < nTechBits; ++iBit) {
1245 
1246  if (gtTechnicalTriggerWordData[iBit]) {
1247  m_fdlDataTechDecision_Err[iRec]->Fill(iBit);
1248  }
1249 
1250  if (gtTechnicalTriggerWordEmul.at(iBit)) {
1251  m_fdlEmulTechDecision_Err[iRec]->Fill(iBit);
1252  }
1253  }
1254  }
1255 
1256  if (gtTechnicalTriggerWordData == gtTechnicalTriggerWordEmul) {
1257  m_myCoutStream << "\n" << recString
1258  << " Data and emulated FDL gtTechnicalTriggerWord identical.\n";
1259  fdlBlockData.printGtTechnicalTriggerWord(m_myCoutStream);
1260  m_myCoutStream << "\n";
1261 
1262  } else {
1263  m_myCoutStream << "\n" << recString
1264  << " Data and emulated FDL gtTechnicalTriggerWord different.";
1265  m_myCoutStream << "\n Data: ";
1266  fdlBlockData.printGtTechnicalTriggerWord(m_myCoutStream);
1267  m_myCoutStream << "\n Emul: ";
1268  fdlBlockEmul.printGtTechnicalTriggerWord(m_myCoutStream);
1269  m_myCoutStream << "\n";
1270 
1271  if (matchBxInEvent && validBxInEvent) {
1272  m_fdlDataEmul[histIndex][iRec]->Fill(4);
1273  } else {
1274  m_fdlDataEmul_Err[iRec]->Fill(4);
1275  }
1276 
1277  if (matchBxInEvent && validBxInEvent) {
1278  for (int iBit = 0; iBit < nTechBits; ++iBit) {
1279  if (gtTechnicalTriggerWordData[iBit]
1280  != gtTechnicalTriggerWordEmul.at(iBit)) {
1281  m_fdlDataEmulTechDecision[histIndex][iRec]->Fill(iBit);
1282  }
1283  }
1284  } else {
1285  for (int iBit = 0; iBit < nTechBits; ++iBit) {
1286  if (gtTechnicalTriggerWordData[iBit]
1287  != gtTechnicalTriggerWordEmul.at(iBit)) {
1288  m_fdlDataEmulTechDecision_Err[iRec]->Fill(iBit);
1289  }
1290  }
1291  }
1292  }
1293 
1294  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1295  m_myCoutStream.str("");
1296  m_myCoutStream.clear();
1297 
1298  if (gtTechnicalTriggerWordDataMask == gtTechnicalTriggerWordEmulMask) {
1299  m_myCoutStream << "\n" << recString
1300  << " Data and emulated FDL gtTechnicalTriggerWord after mask identical.\n";
1301  m_myCoutStream << "\n";
1302 
1303  } else {
1304  m_myCoutStream << "\n" << recString
1305  << " Data and emulated FDL gtTechnicalTriggerWord after mask different.";
1306  m_myCoutStream << "\n Data: ";
1307  m_myCoutStream << "\n Emul: ";
1308  m_myCoutStream << "\n";
1309 
1310  if (matchBxInEvent && validBxInEvent) {
1311  m_fdlDataEmul[histIndex][iRec]->Fill(5);
1312  } else {
1313  m_fdlDataEmul_Err[iRec]->Fill(5);
1314  }
1315 
1316  if (matchBxInEvent && validBxInEvent) {
1317  for (int iBit = 0; iBit < nTechBits; ++iBit) {
1318  if (gtTechnicalTriggerWordData[iBit]
1319  != gtTechnicalTriggerWordEmul.at(iBit)) {
1320  m_fdlDataEmulTechDecisionMask[histIndex][iRec]->Fill(iBit);
1321  }
1322  }
1323  }
1324  }
1325 
1326  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1327  m_myCoutStream.str("");
1328  m_myCoutStream.clear();
1329 
1330  // get algorithms bits (decision word)
1331  const DecisionWord& gtDecisionWordData = fdlBlockData.gtDecisionWord();
1332  const DecisionWord& gtDecisionWordEmul = fdlBlockEmul.gtDecisionWord();
1333 
1334  int nAlgoBits = gtDecisionWordData.size();
1335 
1336  DecisionWord gtDecisionWordDataMask(nAlgoBits);
1337  DecisionWord gtDecisionWordEmulMask(nAlgoBits);
1338 
1339  // get the index of the prescale factor set from data
1340  int iPfSet = fdlBlockData.gtPrescaleFactorIndexAlgo();
1341 
1342  // check that the prescale factor is not out of range for the prescale factor
1343  // record retrieved from event setup
1344  size_t pfSetsSize = (*m_prescaleFactorsAlgoTrig).size();
1345 
1346  if (iPfSet < 0) {
1347 
1348  LogDebug("L1GtHwValidation")
1349  << "\nError: index of prescale factor set retrieved from the data \n"
1350  << "less than zero."
1351  << "\n Value of index retrieved from data = " << iPfSet
1352  << std::endl;
1353 
1354  // FIXME add a histogram to be used for a quality test
1355 
1356  return;
1357 
1358  } else if (iPfSet >= (static_cast<int>(pfSetsSize))) {
1359 
1360  LogDebug("L1GtHwValidation")
1361  << "\nError: index of prescale factor set retrieved from the data \n"
1362  << "greater than the size of the vector of prescale factor sets."
1363  << "\n Value of index retrieved from data = " << iPfSet
1364  << "\n Vector size = " << pfSetsSize << std::endl;
1365 
1366  // FIXME add a histogram to be used for a quality test
1367 
1368  return;
1369 
1370  }
1371 
1372  const std::vector<int>& prescaleFactorsAlgoTrig =
1373  (*m_prescaleFactorsAlgoTrig).at(iPfSet);
1374 
1375 
1376  if (matchBxInEvent && validBxInEvent) {
1377 
1378  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1379 
1380  unsigned int triggerMask = (m_triggerMaskAlgoTrig.at(iBit)) & (1
1381  << PhysicsPartition);
1382 
1383  int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
1384 
1385  LogTrace("L1GtHwValidation") << "Bit " << iBit
1386  << ": prescale factor = " << prescaleFactor
1387  << " trigger mask = " << triggerMask << std::endl;
1388 
1389  if (gtDecisionWordData[iBit]) {
1390  m_fdlDataAlgoDecision[histIndex][iRec]->Fill(iBit);
1391 
1392  if (prescaleFactor == 1) {
1393  m_fdlDataAlgoDecisionUnprescaled[histIndex][iRec]->Fill(
1394  iBit);
1395  } else {
1396  m_fdlDataAlgoDecisionPrescaled[histIndex][iRec]->Fill(iBit);
1397  }
1398 
1399  bitValue = (triggerMask) ? 0 : 1;
1400  gtDecisionWordDataMask[iBit] = bitValue;
1401  if (bitValue) {
1402  m_fdlDataAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
1403  }
1404  }
1405 
1406  if (gtDecisionWordEmul.at(iBit)) {
1407  m_fdlEmulAlgoDecision[histIndex][iRec]->Fill(iBit);
1408 
1409  bitValue = (triggerMask) ? 0 : 1;
1410  gtDecisionWordEmulMask[iBit] = bitValue;
1411  if (bitValue) {
1412  m_fdlEmulAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
1413  }
1414  }
1415  }
1416  } else {
1417  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1418  if (gtDecisionWordData[iBit]) {
1419  m_fdlDataAlgoDecision_Err[iRec]->Fill(iBit);
1420  }
1421  }
1422 
1423  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1424  if (gtDecisionWordEmul.at(iBit)) {
1425  m_fdlEmulAlgoDecision_Err[iRec]->Fill(iBit);
1426  }
1427  }
1428 
1429  if (iRec == 0) {
1430  m_agree = false;
1431 
1432  m_myCoutStream << "\nDisagreement data versus emulator: "
1433  << "\n matchBxInEvent && validBxInEvent false \n";
1434  }
1435 
1436  }
1437 
1438  if (gtDecisionWordData == gtDecisionWordEmul) {
1439  m_myCoutStream << "\n" << recString
1440  << " Data and emulated FDL gtDecisionWord identical.";
1441  fdlBlockData.printGtDecisionWord(m_myCoutStream);
1442  m_myCoutStream << "\n";
1443 
1444  } else {
1445  m_myCoutStream << "\n" << recString
1446  << " Data and emulated FDL gtDecisionWord different.";
1447  m_myCoutStream << "\n Data: ";
1448  fdlBlockData.printGtDecisionWord(m_myCoutStream);
1449  m_myCoutStream << "\n Emul: ";
1450  fdlBlockEmul.printGtDecisionWord(m_myCoutStream);
1451  m_myCoutStream << "\n";
1452 
1453  if (matchBxInEvent && validBxInEvent) {
1454  m_fdlDataEmul[histIndex][iRec]->Fill(6);
1455  } else {
1456  m_fdlDataEmul_Err[iRec]->Fill(6);
1457  }
1458 
1459  if (matchBxInEvent && validBxInEvent) {
1460  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1461 
1462  int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
1463 
1464  if (gtDecisionWordData[iBit] != gtDecisionWordEmul.at(iBit)) {
1465 
1466  m_fdlDataEmulAlgoDecision[histIndex][iRec]->Fill(iBit);
1467 
1468  // for excluded algorithms, fill mismatch for BxInEvent = 0 and DAQ record only
1469  if (excludedAlgo(iBit) && (bxInEventData == 0) && (iRec
1470  == 0)) {
1471  m_excludedAlgorithmsAgreement->Fill(iBit);
1472  }
1473 
1474  if (prescaleFactor == 1) {
1475  m_fdlDataEmulAlgoDecisionUnprescaled[histIndex][iRec]->Fill(
1476  iBit);
1477 
1478  // fill a histogram for allowed algorithm triggers only
1479  if (!excludedAlgo(iBit)) {
1480  m_fdlDataEmulAlgoDecisionUnprescaledAllowed[histIndex][iRec]->Fill(
1481  iBit);
1482  }
1483 
1484  } else {
1485  m_fdlDataEmulAlgoDecisionPrescaled[histIndex][iRec]->Fill(
1486  iBit);
1487  }
1488 
1489  if (gtDecisionWordData[iBit]) {
1490  m_fdlDataAlgoDecision_NoMatch[histIndex][iRec]->Fill(
1491  iBit);
1492 
1493  if (prescaleFactor == 1) {
1494  m_fdlDataAlgoDecisionUnprescaled_NoMatch[histIndex][iRec]->Fill(
1495  iBit);
1496 
1497  // compare for agreement only unprescaled algorithms and algorithms which
1498  // are not excluded from comparison
1499  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1500  && (iRec == 0)) {
1501  m_agree = false;
1502  m_dataOnly = true;
1503 
1504  m_myCoutStream
1505  << "\nDisagreement data versus emulator: "
1506  << "result before mask for algorithm with bit number "
1507  << iBit
1508  << "\n Data: true, emulator: false \n";
1509  }
1510 
1511  } else {
1512  m_fdlDataAlgoDecisionPrescaled_NoMatch[histIndex][iRec]->Fill(
1513  iBit);
1514  }
1515 
1516  } else {
1517  m_fdlEmulAlgoDecision_NoMatch[histIndex][iRec]->Fill(
1518  iBit);
1519 
1520  if (prescaleFactor == 1) {
1521  m_fdlEmulAlgoDecisionUnprescaled_NoMatch[histIndex][iRec]->Fill(
1522  iBit);
1523 
1524  // compare for agreement only unprescaled algorithms and algorithms which
1525  // are not excluded from comparison
1526  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1527  && (iRec == 0)) {
1528  m_agree = false;
1529  m_emulOnly = true;
1530 
1531  m_myCoutStream
1532  << "\nDisagreement data versus emulator: "
1533  << "result before mask for algorithm with bit number "
1534  << iBit
1535  << "\n Data: false, emulator: true \n";
1536  }
1537 
1538  } else {
1539  m_fdlEmulAlgoDecisionPrescaled_NoMatch[histIndex][iRec]->Fill(
1540  iBit);
1541  }
1542  }
1543  }
1544  }
1545  } else {
1546  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1547  if (gtDecisionWordData[iBit] != gtDecisionWordEmul.at(iBit)) {
1548  m_fdlDataEmulAlgoDecision_Err[iRec]->Fill(iBit);
1549  }
1550  }
1551 
1552  if (iRec == 0) {
1553  m_agree = false;
1554 
1555  m_myCoutStream << "\nDisagreement data versus emulator: "
1556  << "\n matchBxInEvent && validBxInEvent false \n";
1557  }
1558  }
1559 
1560  }
1561 
1562  if (gtDecisionWordDataMask == gtDecisionWordEmulMask) {
1563  m_myCoutStream << "\n" << recString
1564  << " Data and emulated FDL gtDecisionWord after mask identical.";
1565  m_myCoutStream << "\n";
1566 
1567  } else {
1568  m_myCoutStream << "\n" << recString
1569  << " Data and emulated FDL gtDecisionWord after mask different.";
1570  m_myCoutStream << "\n Data: ";
1571  m_myCoutStream << "\n Emul: ";
1572  m_myCoutStream << "\n";
1573 
1574  if (matchBxInEvent && validBxInEvent) {
1575  m_fdlDataEmul[histIndex][iRec]->Fill(7);
1576  } else {
1577  m_fdlDataEmul_Err[iRec]->Fill(7);
1578  }
1579 
1580  if (matchBxInEvent && validBxInEvent) {
1581  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1582  if (gtDecisionWordDataMask[iBit] != gtDecisionWordEmulMask.at(
1583  iBit)) {
1584  m_fdlDataEmulAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
1585 
1586 
1587  int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
1588 
1589  if (gtDecisionWordDataMask[iBit]) {
1590  m_fdlDataAlgoDecisionMask_NoMatch[histIndex][iRec]->Fill(
1591  iBit);
1592 
1593  if (prescaleFactor == 1) {
1594  m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[histIndex][iRec]->Fill(
1595  iBit);
1596 
1597  // compare for agreement only unprescaled algorithms and algorithms which
1598  // are not excluded from comparison
1599  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1600  && (iRec == 0)) {
1601  m_agree = false;
1602  m_dataOnlyMask = true;
1603 
1604  m_myCoutStream
1605  << "\nDisagreement data versus emulator: "
1606  << "result after mask for algorithm with bit number "
1607  << iBit
1608  << " different in data versus emulator "
1609  << "\n Data: true, emulator: false \n";
1610  }
1611 
1612  } else {
1613  m_fdlDataAlgoDecisionPrescaledMask_NoMatch[histIndex][iRec]->Fill(
1614  iBit);
1615  }
1616 
1617  } else {
1618  m_fdlEmulAlgoDecisionMask_NoMatch[histIndex][iRec]->Fill(
1619  iBit);
1620 
1621  if (prescaleFactor == 1) {
1622  m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[histIndex][iRec]->Fill(
1623  iBit);
1624 
1625  // compare for agreement only unprescaled algorithms and algorithms which
1626  // are not excluded from comparison
1627  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1628  && (iRec == 0)) {
1629  m_agree = false;
1630  m_emulOnlyMask = true;
1631 
1632  m_myCoutStream
1633  << "\nDisagreement data versus emulator: "
1634  << "result after mask for algorithm with bit number "
1635  << iBit
1636  << " different in data versus emulator "
1637  << "\n Data: false, emulator: true \n";
1638  }
1639 
1640  } else {
1641  m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[histIndex][iRec]->Fill(
1642  iBit);
1643  }
1644  }
1645 
1646 
1647  }
1648  }
1649  }
1650 
1651  }
1652 
1653  // get extended algorithms bits (extended decision word)
1654  const DecisionWordExtended gtDecisionWordExtendedData =
1655  fdlBlockData.gtDecisionWordExtended();
1656  const DecisionWordExtended gtDecisionWordExtendedEmul =
1657  fdlBlockEmul.gtDecisionWordExtended();
1658 
1659  if (gtDecisionWordExtendedData == gtDecisionWordExtendedEmul) {
1660  m_myCoutStream << "\n" << recString
1661  << " Data and emulated FDL gtDecisionWordExtended identical.\n";
1662  fdlBlockData.printGtDecisionWordExtended(m_myCoutStream);
1663  m_myCoutStream << "\n";
1664 
1665  } else {
1666  m_myCoutStream << "\n" << recString
1667  << " Data and emulated FDL gtDecisionWordExtended different.\n";
1668  m_myCoutStream << "\n Data: ";
1669  fdlBlockData.printGtDecisionWordExtended(m_myCoutStream);
1670  m_myCoutStream << "\n Emul: ";
1671  fdlBlockEmul.printGtDecisionWordExtended(m_myCoutStream);
1672  m_myCoutStream << "\n";
1673 
1674  if (matchBxInEvent && validBxInEvent) {
1675  m_fdlDataEmul[histIndex][iRec]->Fill(8);
1676  } else {
1677  m_fdlDataEmul_Err[iRec]->Fill(8);
1678  }
1679 
1680  }
1681 
1682  // get NoAlgo
1683  const boost::uint16_t noAlgoData = fdlBlockData.noAlgo();
1684  const boost::uint16_t noAlgoEmul = fdlBlockEmul.noAlgo();
1685 
1686  if (noAlgoData == noAlgoEmul) {
1687  m_myCoutStream << "\n" << recString
1688  << " Data and emulated FDL noAlgo identical.";
1689  m_myCoutStream << "\n noAlgo() = " << noAlgoData;
1690  m_myCoutStream << "\n";
1691 
1692  } else {
1693  m_myCoutStream << "\n" << recString
1694  << " Data and emulated FDL noAlgo different.";
1695  m_myCoutStream << "\n Data: noAlgo() = " << noAlgoData;
1696  m_myCoutStream << "\n Emul: noAlgo() = " << noAlgoEmul;
1697  m_myCoutStream << "\n";
1698 
1699  if (matchBxInEvent && validBxInEvent) {
1700  m_fdlDataEmul[histIndex][iRec]->Fill(9);
1701  } else {
1702  m_fdlDataEmul_Err[iRec]->Fill(9);
1703  }
1704 
1705  }
1706 
1707  // get "Final OR" bits
1708  const boost::uint16_t finalORData = fdlBlockData.finalOR();
1709  const boost::uint16_t finalOREmul = fdlBlockEmul.finalOR();
1710 
1711  if (finalORData == finalOREmul) {
1712  m_myCoutStream << "\n" << recString
1713  << " Data and emulated FDL finalOR identical.";
1714  m_myCoutStream << "\n finalOR() = " << std::hex << "0x" << std::setw(2)
1715  << std::setfill('0') << finalORData << std::setfill(' ')
1716  << std::dec;
1717  m_myCoutStream << "\n";
1718 
1719  } else {
1720  m_myCoutStream << "\n" << recString
1721  << " Data and emulated FDL finalOR different.";
1722  m_myCoutStream << "\n Data: finalOR() = " << std::hex << "0x"
1723  << std::setw(2) << std::setfill('0') << finalORData
1724  << std::setfill(' ') << std::dec;
1725  m_myCoutStream << "\n Emul: finalOR() = " << std::hex << "0x"
1726  << std::setw(2) << std::setfill('0') << finalOREmul
1727  << std::setfill(' ') << std::dec;
1728  m_myCoutStream << "\n";
1729 
1730  if (matchBxInEvent && validBxInEvent) {
1731  m_fdlDataEmul[histIndex][iRec]->Fill(10);
1732  } else {
1733  m_fdlDataEmul_Err[iRec]->Fill(10);
1734  }
1735 
1736  }
1737 
1738  // get "Final OR" for physics partition
1739  const int finalORPhysData = finalORData & (1 << PhysicsPartition);
1740  const int finalORPhysEmul = finalOREmul & (1 << PhysicsPartition);
1741 
1742  if (finalORPhysData == finalORPhysEmul) {
1743  m_myCoutStream << "\n" << recString
1744  << " Data and emulated FDL finalOR for the physics partition identical.";
1745  m_myCoutStream << "\n finalOR() = " << finalORPhysData;
1746  m_myCoutStream << "\n";
1747 
1748  } else {
1749  m_myCoutStream << "\n" << recString
1750  << " Data and emulated FDL finalOR for the physics partition different.";
1751  m_myCoutStream << "\n Data: finalOR() = " << finalORPhysData;
1752  m_myCoutStream << "\n Emul: finalOR() = " << finalORPhysEmul;
1753  m_myCoutStream << "\n";
1754 
1755  if (matchBxInEvent && validBxInEvent) {
1756  m_fdlDataEmul[histIndex][iRec]->Fill(11);
1757  } else {
1758  m_fdlDataEmul_Err[iRec]->Fill(11);
1759  }
1760 
1761  }
1762 
1763  // get local bunch cross number of the actual bx
1764  const boost::uint16_t localBxNrData = fdlBlockData.localBxNr();
1765  const boost::uint16_t localBxNrEmul = fdlBlockEmul.localBxNr();
1766 
1767  if (localBxNrData == localBxNrEmul) {
1768  m_myCoutStream << "\n" << recString
1769  << " Data and emulated FDL localBxNr identical.";
1770  m_myCoutStream << "\n localBxNr() = " << localBxNrData;
1771  m_myCoutStream << "\n";
1772 
1773  } else {
1774  m_myCoutStream << "\n" << recString
1775  << " Data and emulated FDL localBxNr different.";
1776  m_myCoutStream << "\n Data: localBxNr() = " << localBxNrData;
1777  m_myCoutStream << "\n Emul: localBxNr() = " << localBxNrEmul;
1778  m_myCoutStream << "\n";
1779 
1780  if (matchBxInEvent && validBxInEvent) {
1781  m_fdlDataEmul[histIndex][iRec]->Fill(12);
1782  } else {
1783  m_fdlDataEmul_Err[iRec]->Fill(12);
1784  }
1785 
1786  }
1787 
1788  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1789  m_myCoutStream.str("");
1790  m_myCoutStream.clear();
1791 
1792 }
1793 
1794 //compare the PSB board
1795 void L1GtHwValidation::comparePSB(const edm::Event& iEvent,
1796  const edm::EventSetup& evSetup, const L1GtPsbWord& psbBlockData,
1797  const L1GtPsbWord& psbBlockEmul) {
1798 
1799  if (psbBlockData == psbBlockEmul) {
1800  m_myCoutStream << "\nData and emulated PSB blocks: identical.\n";
1801  psbBlockData.print(m_myCoutStream);
1802 
1803  } else {
1804  m_myCoutStream << "\nData and emulated PSB blocks: different.\n";
1805 
1806  m_myCoutStream << "\nData: PSB block\n";
1807  psbBlockData.print(m_myCoutStream);
1808 
1809  m_myCoutStream << "\nEmul: PSB block\n";
1810  psbBlockEmul.print(m_myCoutStream);
1811 
1812  }
1813 
1814  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1815 
1816  m_myCoutStream.str("");
1817  m_myCoutStream.clear();
1818 
1819  // get BoardId value
1820  const boost::uint16_t boardIdData = psbBlockData.boardId();
1821  const boost::uint16_t boardIdEmul = psbBlockEmul.boardId();
1822 
1823  if (boardIdData == boardIdEmul) {
1824  m_myCoutStream << "\nData and emulated PSB boardId identical.";
1825  m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4)
1826  << std::setfill('0') << boardIdData << std::setfill(' ')
1827  << std::dec;
1828  m_myCoutStream << "\n";
1829 
1830  } else {
1831  m_myCoutStream << "\nData and emulated PSB boardId different.";
1832  m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x"
1833  << std::setw(4) << std::setfill('0') << boardIdData
1834  << std::setfill(' ') << std::dec;
1835  m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x"
1836  << std::setw(4) << std::setfill('0') << boardIdEmul
1837  << std::setfill(' ') << std::dec;
1838  m_myCoutStream << "\n";
1839 
1840  }
1841 
1842  // get bunch cross in the GT event record
1843  const int bxInEventData = psbBlockData.bxInEvent();
1844  const int bxInEventEmul = psbBlockEmul.bxInEvent();
1845 
1846  if (bxInEventData == bxInEventEmul) {
1847  m_myCoutStream << "\nData and emulated PSB bxInEvent identical.";
1848  m_myCoutStream << "\n bxInEvent() = " << bxInEventData;
1849  m_myCoutStream << "\n";
1850 
1851  } else {
1852  m_myCoutStream << "\nData and emulated PSB bxInEvent different.";
1853  m_myCoutStream << "\n Data: bxInEvent() = " << bxInEventData;
1854  m_myCoutStream << "\n Emul: bxInEvent() = " << bxInEventEmul;
1855  m_myCoutStream << "\n";
1856 
1857  }
1858 
1859  // get BxNr - bunch cross number of the actual bx
1860  const boost::uint16_t bxNrData = psbBlockData.bxNr();
1861  const boost::uint16_t bxNrEmul = psbBlockEmul.bxNr();
1862 
1863  if (bxNrData == bxNrEmul) {
1864  m_myCoutStream << "\nData and emulated PSB bxNr identical.";
1865  m_myCoutStream << "\n bxNr() = " << bxNrData;
1866  m_myCoutStream << "\n";
1867 
1868  } else {
1869  m_myCoutStream << "\nData and emulated PSB bxNr different.";
1870  m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
1871  m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
1872  m_myCoutStream << "\n";
1873 
1874  }
1875 
1876  // get event number since last L1 reset generated in FDL
1877  const boost::uint32_t eventNrData = psbBlockData.eventNr();
1878  const boost::uint32_t eventNrEmul = psbBlockEmul.eventNr();
1879 
1880  if (eventNrData == eventNrEmul) {
1881  m_myCoutStream << "\nData and emulated PSB eventNr identical.";
1882  m_myCoutStream << "\n eventNr() = " << eventNrData;
1883  m_myCoutStream << "\n";
1884 
1885  } else {
1886  m_myCoutStream << "\nData and emulated PSB eventNr different.";
1887  m_myCoutStream << "\n Data: eventNr() = " << eventNrData;
1888  m_myCoutStream << "\n Emul: eventNr() = " << eventNrEmul;
1889  m_myCoutStream << "\n";
1890 
1891  }
1892 
1894  boost::uint16_t valData;
1895  boost::uint16_t valEmul;
1896 
1897  for (int iA = 0; iA < psbBlockData.NumberAData; ++iA) {
1898  valData = psbBlockData.aData(iA);
1899  valEmul = psbBlockEmul.aData(iA);
1900 
1901  if (valData == valEmul) {
1902  m_myCoutStream << "\nData and emulated PSB aData(" << iA
1903  << ") identical.";
1904  m_myCoutStream << "\n aData(iA) = " << std::hex << "0x"
1905  << std::setw(4) << std::setfill('0') << valData
1906  << std::setfill(' ') << std::dec;
1907  m_myCoutStream << "\n";
1908 
1909  } else {
1910  m_myCoutStream << "\nData and emulated PSB aData(" << iA
1911  << ") different.";
1912  m_myCoutStream << "\n Data: aData(iA) = " << std::hex << "0x"
1913  << std::setw(4) << std::setfill('0') << valData
1914  << std::setfill(' ') << std::dec;
1915  m_myCoutStream << "\n Emul: aData(iA) = " << std::hex << "0x"
1916  << std::setw(4) << std::setfill('0') << valEmul
1917  << std::setfill(' ') << std::dec;
1918  m_myCoutStream << "\n";
1919 
1920  }
1921 
1922  }
1923 
1925  for (int iB = 0; iB < psbBlockData.NumberBData; ++iB) {
1926  valData = psbBlockData.bData(iB);
1927  valEmul = psbBlockEmul.bData(iB);
1928 
1929  if (valData == valEmul) {
1930  m_myCoutStream << "\nData and emulated PSB bData(" << iB
1931  << ") identical.";
1932  m_myCoutStream << "\n bData(iA) = " << std::hex << "0x"
1933  << std::setw(4) << std::setfill('0') << valData
1934  << std::setfill(' ') << std::dec;
1935  m_myCoutStream << "\n";
1936 
1937  } else {
1938  m_myCoutStream << "\nData and emulated PSB bData(" << iB
1939  << ") different.";
1940  m_myCoutStream << "\n Data: bData(iA) = " << std::hex << "0x"
1941  << std::setw(4) << std::setfill('0') << valData
1942  << std::setfill(' ') << std::dec;
1943  m_myCoutStream << "\n Emul: bData(iA) = " << std::hex << "0x"
1944  << std::setw(4) << std::setfill('0') << valEmul
1945  << std::setfill(' ') << std::dec;
1946  m_myCoutStream << "\n";
1947 
1948  }
1949 
1950  }
1951 
1952  // get local bunch cross number of the actual bx
1953  const boost::uint16_t localBxNrData = psbBlockData.localBxNr();
1954  const boost::uint16_t localBxNrEmul = psbBlockEmul.localBxNr();
1955 
1956  if (localBxNrData == localBxNrEmul) {
1957  m_myCoutStream << "\nData and emulated PSB localBxNr identical.";
1958  m_myCoutStream << "\n localBxNr() = " << localBxNrData;
1959  m_myCoutStream << "\n";
1960 
1961  } else {
1962  m_myCoutStream << "\nData and emulated PSB localBxNr different.";
1963  m_myCoutStream << "\n Data: localBxNr() = " << localBxNrData;
1964  m_myCoutStream << "\n Emul: localBxNr() = " << localBxNrEmul;
1965  m_myCoutStream << "\n";
1966 
1967  }
1968 
1969  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1970  m_myCoutStream.str("");
1971  m_myCoutStream.clear();
1972 
1973 }
1974 
1975 //compare the TCS board
1976 void L1GtHwValidation::compareTCS(const edm::Event& iEvent,
1977  const edm::EventSetup& evSetup, const L1TcsWord&, const L1TcsWord&) {
1978  // empty
1979 }
1980 
1981 //L1 GT DAQ record comparison
1982 void L1GtHwValidation::compareDaqRecord(const edm::Event& iEvent, const edm::EventSetup& evSetup) {
1983 
1984  // formal index for DAQ record
1985  int iRec = 0;
1986 
1987  // reset the flags - they are used for DAQ recor only
1988  m_agree = true;
1989  m_dataOnly = false;
1990  m_emulOnly = false;
1991  m_dataOnlyMask = false;
1992  m_emulOnlyMask = false;
1993 
1994 
1995  // get the L1 GT hardware DAQ record L1GlobalTriggerReadoutRecord
1996  edm::Handle<L1GlobalTriggerReadoutRecord> gtReadoutRecordData;
1997  iEvent.getByToken(m_l1GtDataDaqInputToken_, gtReadoutRecordData);
1998 
1999  bool validData = false;
2000 
2001  if (!gtReadoutRecordData.isValid()) {
2002  m_nrDataEventError++;
2003  } else {
2004  validData = true;
2005  }
2006 
2007  // get the L1 GT emulator DAQ record L1GlobalTriggerReadoutRecord
2008  edm::Handle<L1GlobalTriggerReadoutRecord> gtReadoutRecordEmul;
2009  iEvent.getByToken(m_l1GtEmulDaqInputToken_, gtReadoutRecordEmul);
2010 
2011  bool validEmul = false;
2012 
2013  if (!gtReadoutRecordEmul.isValid()) {
2014  m_nrEmulEventError++;
2015  } else {
2016  validEmul = true;
2017  }
2018 
2019  if ((!validData) || (!validEmul)) {
2020  edm::LogWarning("L1GtHwValidation")
2021  << "\n No valid product found: DAQ L1GlobalTriggerReadoutRecord"
2022  << "\n Data validity [1 = true; 0 = false]: " << validData
2023  << "\n Emulator validity: [1 = true; 0 = false]: "
2024  << validEmul << "\n DAQ histograms will not be filled.\n"
2025  << std::endl;
2026 
2027  return;
2028  }
2029 
2030  // compare GTFE
2031  const L1GtfeWord& gtfeBlockData = gtReadoutRecordData->gtfeWord();
2032  const L1GtfeWord& gtfeBlockEmul = gtReadoutRecordEmul->gtfeWord();
2033 
2034  compareGTFE(iEvent, evSetup, gtfeBlockData, gtfeBlockEmul, iRec);
2035 
2036  // FDL comparison
2037  const std::vector<L1GtFdlWord>& gtFdlVectorData =
2038  gtReadoutRecordData->gtFdlVector();
2039  const std::vector<L1GtFdlWord>& gtFdlVectorEmul =
2040  gtReadoutRecordEmul->gtFdlVector();
2041 
2042  int gtFdlVectorDataSize = gtFdlVectorData.size();
2043  int gtFdlVectorEmulSize = gtFdlVectorEmul.size();
2044 
2045  if (gtFdlVectorDataSize == gtFdlVectorEmulSize) {
2046  m_myCoutStream << "\nData and emulated FDL vector size: identical.\n";
2047  m_myCoutStream << " Size: " << gtFdlVectorDataSize << std::endl;
2048 
2049  for (int iFdl = 0; iFdl < gtFdlVectorDataSize; ++iFdl) {
2050 
2051  const L1GtFdlWord& fdlBlockData = gtFdlVectorData[iFdl];
2052  const L1GtFdlWord& fdlBlockEmul = gtFdlVectorEmul[iFdl];
2053 
2054  compareFDL(iEvent, evSetup, fdlBlockData, fdlBlockEmul, iRec);
2055  }
2056  } else {
2057  m_myCoutStream << "\nData and emulated FDL vector size: different.\n";
2058  m_myCoutStream << " Data: size = " << gtFdlVectorDataSize << std::endl;
2059  m_myCoutStream << " Emul: size = " << gtFdlVectorEmulSize << std::endl;
2060 
2061  }
2062 
2063  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
2064 
2065  m_myCoutStream.str("");
2066  m_myCoutStream.clear();
2067 
2068  // PSB comparison
2069  const std::vector<L1GtPsbWord>& gtPsbVectorData =
2070  gtReadoutRecordData->gtPsbVector();
2071  const std::vector<L1GtPsbWord>& gtPsbVectorEmul =
2072  gtReadoutRecordEmul->gtPsbVector();
2073 
2074  int gtPsbVectorDataSize = gtPsbVectorData.size();
2075  int gtPsbVectorEmulSize = gtPsbVectorEmul.size();
2076 
2077  if (gtPsbVectorDataSize == gtPsbVectorEmulSize) {
2078  m_myCoutStream << "\nData and emulated PSB vector size: identical.\n";
2079  m_myCoutStream << " Size: " << gtPsbVectorDataSize << std::endl;
2080  } else {
2081  m_myCoutStream << "\nData and emulated PSB vector size: different.\n";
2082  m_myCoutStream << " Data: size = " << gtPsbVectorDataSize << std::endl;
2083  m_myCoutStream << " Emul: size = " << gtPsbVectorEmulSize << std::endl;
2084 
2085  }
2086 
2087  // the order of PSB block in the gtPsbVector is different in emulator and in data
2088  // in emulator: all active PSB in one BxInEvent, ordered L1A-1, L1A, L1A+1
2089  // in unpacker: every PSB in all BxInEvent
2090  for (int iPsb = 0; iPsb < gtPsbVectorDataSize; ++iPsb) {
2091 
2092  const L1GtPsbWord& psbBlockData = gtPsbVectorData[iPsb];
2093  const boost::uint16_t boardIdData = psbBlockData.boardId();
2094  const int bxInEventData = psbBlockData.bxInEvent();
2095 
2096  // search the corresponding PSB in the emulated record using the
2097  // BoardId and the BxInEvent
2098 
2099  bool foundPSB = false;
2100 
2101  for (int iPsbF = 0; iPsbF < gtPsbVectorEmulSize; ++iPsbF) {
2102 
2103  const L1GtPsbWord& psbBlockEmul = gtPsbVectorEmul[iPsbF];
2104  const boost::uint16_t boardIdEmul = psbBlockEmul.boardId();
2105  const int bxInEventEmul = psbBlockEmul.bxInEvent();
2106 
2107  if ((boardIdEmul == boardIdData)
2108  && (bxInEventData == bxInEventEmul)) {
2109 
2110  foundPSB = true;
2111 
2112  // compare the boards
2113  comparePSB(iEvent, evSetup, psbBlockData, psbBlockEmul);
2114  }
2115 
2116  }
2117 
2118  if (!foundPSB) {
2119  m_myCoutStream << "\nNo emulated PSB with boardId() = " << std::hex
2120  << "0x" << std::setw(4) << std::setfill('0') << boardIdData
2121  << std::setfill(' ') << std::dec << " and BxInEvent = "
2122  << bxInEventData << " was found";
2123 
2124  }
2125 
2126  }
2127 
2128  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
2129 
2130  m_myCoutStream.str("");
2131  m_myCoutStream.clear();
2132 
2133  // fill the m_gtErrorFlag histogram (only for L1 GT DAQ record)
2134 
2135  if (m_agree) {
2136  m_gtErrorFlag->Fill(0.0001);
2137  }
2138 
2139  if (m_dataOnly || m_dataOnlyMask) {
2140  m_gtErrorFlag->Fill(3.0001);
2141  }
2142 
2143  if (m_emulOnly || m_emulOnlyMask) {
2144  m_gtErrorFlag->Fill(4.0001);
2145  }
2146 
2147 }
2148 
2149 // L1 GT EVM record comparison
2150 void L1GtHwValidation::compareEvmRecord(const edm::Event& iEvent,
2151  const edm::EventSetup& evSetup) {
2152 
2153  // formal index for EVM record
2154  int iRec = 1;
2155 
2156  // get the L1 GT hardware EVM record L1GlobalTriggerEvmReadoutRecord
2157  edm::Handle<L1GlobalTriggerEvmReadoutRecord> gtReadoutRecordData;
2158  iEvent.getByToken(m_l1GtDataEvmInputToken_, gtReadoutRecordData);
2159 
2160  bool validData = false;
2161 
2162  if (!gtReadoutRecordData.isValid()) {
2163  m_nrDataEventError++;
2164  } else {
2165  validData = true;
2166  }
2167 
2168  // get the L1 GT emulator EVM record L1GlobalTriggerEvmReadoutRecord
2169  edm::Handle<L1GlobalTriggerEvmReadoutRecord> gtReadoutRecordEmul;
2170  iEvent.getByToken(m_l1GtEmulEvmInputToken_, gtReadoutRecordEmul);
2171 
2172  bool validEmul = false;
2173 
2174  if (!gtReadoutRecordEmul.isValid()) {
2175  m_nrEmulEventError++;
2176  } else {
2177  validEmul = true;
2178  }
2179 
2180  if ((!validData) || (!validEmul)) {
2181  edm::LogWarning("L1GtHwValidation")
2182  << "\n No valid product found: EVM L1GlobalTriggerEvmReadoutRecord"
2183  << "\n Data validity [1 = true; 0 = false]: " << validData
2184  << "\n Emulator validity: [1 = true; 0 = false]: "
2185  << validEmul << "\n EVM histograms will not be filled.\n"
2186  << std::endl;
2187 
2188  return;
2189  }
2190 
2191  // compare GTFE
2192  const L1GtfeWord& gtfeBlockData = gtReadoutRecordData->gtfeWord();
2193  const L1GtfeWord& gtfeBlockEmul = gtReadoutRecordEmul->gtfeWord();
2194 
2195  compareGTFE(iEvent, evSetup, gtfeBlockData, gtfeBlockEmul, iRec);
2196 
2197  // FDL comparison
2198  const std::vector<L1GtFdlWord>& gtFdlVectorData =
2199  gtReadoutRecordData->gtFdlVector();
2200  const std::vector<L1GtFdlWord>& gtFdlVectorEmul =
2201  gtReadoutRecordEmul->gtFdlVector();
2202 
2203  int gtFdlVectorDataSize = gtFdlVectorData.size();
2204  int gtFdlVectorEmulSize = gtFdlVectorEmul.size();
2205 
2206  if (gtFdlVectorDataSize == gtFdlVectorEmulSize) {
2207  m_myCoutStream << "\nData and emulated FDL vector size: identical.\n";
2208  m_myCoutStream << " Size: " << gtFdlVectorDataSize << std::endl;
2209 
2210  for (int iFdl = 0; iFdl < gtFdlVectorDataSize; ++iFdl) {
2211 
2212  const L1GtFdlWord& fdlBlockData = gtFdlVectorData[iFdl];
2213  const L1GtFdlWord& fdlBlockEmul = gtFdlVectorEmul[iFdl];
2214 
2215  compareFDL(iEvent, evSetup, fdlBlockData, fdlBlockEmul, iRec);
2216  }
2217  } else {
2218  m_myCoutStream << "\nData and emulated FDL vector size: different.\n";
2219  m_myCoutStream << " Data: size = " << gtFdlVectorDataSize << std::endl;
2220  m_myCoutStream << " Emul: size = " << gtFdlVectorEmulSize << std::endl;
2221 
2222  }
2223 
2224  // FIXME compare TCS
2225 
2226  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
2227 
2228  m_myCoutStream.str("");
2229  m_myCoutStream.clear();
2230 
2231  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
2232 
2233  m_myCoutStream.str("");
2234  m_myCoutStream.clear();
2235 
2236 }
2237 
2238 // compare the GCT collections obtained from L1 GT PSB with the input
2239 // GCT collections
2240 void L1GtHwValidation::compareGt_Gct(const edm::Event& iEvent,
2241  const edm::EventSetup&) {
2242 
2243  // FIXME
2244 
2245 }
2246 
2247 // analyze each event: event loop
2248 void L1GtHwValidation::analyze(const edm::Event& iEvent,
2249  const edm::EventSetup& evSetup) {
2250 
2251  ++m_nrEvJob;
2252  ++m_nrEvRun;
2253 
2254  // L1 GT DAQ record comparison
2255  compareDaqRecord(iEvent, evSetup);
2256 
2257  // L1 GT EVM record comparison
2258  compareEvmRecord(iEvent, evSetup);
2259 
2260  // GCT collections from L1 GT PSB versus unpacked GCT
2261  compareGt_Gct(iEvent, evSetup);
2262 
2263 }
2264 
2265 
2266 bool L1GtHwValidation::matchCondCategory(
2267  const L1GtConditionCategory& conditionCategory,
2268  const L1GtConditionCategory& excludedCategory) {
2269 
2270  bool matchValue = false;
2271 
2272  if (excludedCategory == CondNull) {
2273  matchValue = true;
2274  } else {
2275  if (conditionCategory == excludedCategory) {
2276  matchValue = true;
2277  }
2278  }
2279 
2280  return matchValue;
2281 }
2282 
2283 
2284 bool L1GtHwValidation::matchCondType(const L1GtConditionType& conditionType,
2285  const L1GtConditionType& excludedType) {
2286 
2287  bool matchValue = false;
2288 
2289  if (excludedType == TypeNull) {
2290  matchValue = true;
2291  } else {
2292  if (conditionType == excludedType) {
2293  matchValue = true;
2294  }
2295  }
2296 
2297  return matchValue;
2298 }
2299 
2300 
2301 bool L1GtHwValidation::matchCondL1GtObject(
2302  const std::vector<L1GtObject>& condObjects,
2303  const L1GtObject& excludedObject) {
2304 
2305  bool matchValue = false;
2306 
2307  if (excludedObject == ObjNull) {
2308 
2309  matchValue = true;
2310 
2311  } else {
2312 
2313  for (std::vector<L1GtObject>::const_iterator itCondObj =
2314  condObjects.begin(); itCondObj != condObjects.end(); ++itCondObj) {
2315 
2316  if ((*itCondObj) == excludedObject) {
2317 
2318  matchValue = true;
2319 
2320  }
2321  }
2322  }
2323 
2324  return matchValue;
2325 
2326 }
2327 
2328 
2329 void L1GtHwValidation::excludedAlgoList() {
2330 
2331 
2332  const AlgorithmMap& algorithmMap = m_l1GtMenu->gtAlgorithmMap();
2333  (const_cast<L1GtTriggerMenu*> (m_l1GtMenu))->buildGtConditionMap(); //...ugly
2334 
2335  for (CItAlgo itAlgo = algorithmMap.begin(); itAlgo != algorithmMap.end(); itAlgo++) {
2336 
2337  const std::string& algName = itAlgo->first;
2338  const int algBitNumber = (itAlgo->second).algoBitNumber();
2339  const int chipNr = (itAlgo->second).algoChipNumber();
2340 
2341  const ConditionMap& conditionMap = (m_l1GtMenu->gtConditionMap()).at(
2342  chipNr);
2343 
2344  const std::vector<L1GtLogicParser::TokenRPN>& aRpnVector =
2345  (itAlgo->second).algoRpnVector();
2346  size_t aRpnVectorSize = aRpnVector.size();
2347 
2348  bool algWithExcludedCondition = false;
2349  bool algWithConditionNotInMap = false;
2350 
2351  // loop over RpnVector and check each conditions against list of excluded conditions
2352  for (size_t opI = 0; opI < aRpnVectorSize; ++opI) {
2353 
2354  const std::string& cndName = (aRpnVector[opI]).operand;
2355 
2356  if (!cndName.empty()) {
2357  bool foundCond = false;
2358 
2359  CItCond itCond = conditionMap.find(cndName);
2360  if (itCond != conditionMap.end()) {
2361 
2362  const L1GtConditionCategory& cCateg = (itCond->second)->condCategory();
2363  const L1GtConditionType& cType = (itCond->second)->condType();
2364  const std::vector<L1GtObject>& objType = (itCond->second)->objectType();
2365 
2366  // condition index in the m_excludedCondCategory, m_excludedCondType, m_excludedL1GtObject vectors
2367  int iCond = -1;
2368 
2369  for (std::vector<L1GtConditionCategory>::const_iterator
2370  itCateg = m_excludedCondCategory.begin();
2371  itCateg != m_excludedCondCategory.end(); ++itCateg) {
2372 
2373  iCond++;
2374 
2375  bool matchCondCategoryValue = matchCondCategory(cCateg, (*itCateg));
2376  bool matchCondTypeValue = matchCondType(cType, m_excludedCondType.at(iCond));
2377  bool matchCondL1GtObjectValue = matchCondL1GtObject(objType, m_excludedL1GtObject.at(iCond));
2378 
2379  LogTrace("L1GtHwValidation")
2380  << "\n "
2381  << "Algorithm: " << algName
2382  << " Condition: " << cndName
2383  << "\n "
2384  << "Category: " << l1GtConditionCategoryEnumToString(cCateg)
2385  << "; excluded: " << l1GtConditionCategoryEnumToString((*itCateg))
2386  << "\n "
2387  << "Type: " << l1GtConditionTypeEnumToString(cType)
2388  << "; excluded: " << l1GtConditionTypeEnumToString(m_excludedCondType.at(iCond))
2389  << "\n "
2390  << "Object excluded: " << l1GtObjectEnumToString(m_excludedL1GtObject.at(iCond))
2391  << std::endl;
2392 
2393 
2394  if (matchCondCategoryValue && matchCondTypeValue && matchCondL1GtObjectValue) {
2395 
2396  algWithExcludedCondition = true;
2397 
2398  }
2399 
2400  }
2401 
2402  foundCond = true;
2403  }
2404 
2405  if (!foundCond) {
2406  // it should never be happen, all conditions are in the maps
2407 
2408  algWithConditionNotInMap = true;
2409 
2410  LogTrace("L1GtHwValidation") << "\n Error: condition "
2411  << cndName << " not found in condition map!"
2412  << "\n Add algorithm " << algName
2413  << " (bit number " << algBitNumber << ") "
2414  << "\n to list of algorithms excluded from comparison"
2415  << "\n data versus emulator." << std::endl;
2416  }
2417 
2418  }
2419  }
2420 
2421  if (algWithConditionNotInMap) {
2422  // it should never be happen, all conditions are in the maps
2423 
2424  m_excludedAlgoList.push_back(algBitNumber);
2425 
2426  LogTrace("L1GtHwValidation")
2427  << "\n Error: one or more conditions from algorithm "
2428  << algName << " (bit number " << algBitNumber << ") "
2429  << " not found in condition map!"
2430  << "\n Add it to list of algorithms excluded from comparison"
2431  << "\n data versus emulator." << std::endl;
2432  }
2433 
2434  if (algWithExcludedCondition) {
2435 
2436  m_excludedAlgoList.push_back(algBitNumber);
2437 
2438  LogTrace("L1GtHwValidation") << "\n Algorithm " << algName
2439  << " (bit number " << algBitNumber
2440  << ") contains an excluded condition."
2441  << "\n Add it to list of algorithms excluded from comparison"
2442  << "\n data versus emulator." << std::endl;
2443 
2444  }
2445 
2446  // add algorithm triggers from ExcludeAlgoTrigByName
2447  for (std::vector<std::string>::const_iterator
2448  itExcl = m_excludeAlgoTrigByName.begin();
2449  itExcl!= m_excludeAlgoTrigByName.end(); ++itExcl) {
2450 
2451  if ((*itExcl) == algName) {
2452 
2453  m_excludedAlgoList.push_back(algBitNumber);
2454 
2455  LogTrace("L1GtHwValidation") << "\n Algorithm " << algName
2456  << " (bit number " << algBitNumber
2457  << ")\n added to list of algorithms excluded from comparison"
2458  << " \n data versus emulator by ExcludeAlgoTrigByName." << std::endl;
2459  }
2460 
2461  }
2462 
2463 
2464  // add algorithm triggers from ExcludeAlgoTrigByBit
2465  for (std::vector<int>::const_iterator
2466  itExcl = m_excludeAlgoTrigByBit.begin();
2467  itExcl!= m_excludeAlgoTrigByBit.end(); ++itExcl) {
2468 
2469  if ((*itExcl) == algBitNumber) {
2470 
2471  m_excludedAlgoList.push_back(algBitNumber);
2472 
2473  LogTrace("L1GtHwValidation") << "\n Algorithm " << algName
2474  << " (bit number " << algBitNumber
2475  << ")\n added to list of algorithms excluded from comparison"
2476  << " \n data versus emulator by ExcludeAlgoTrigByBit." << std::endl;
2477  }
2478 
2479  }
2480 
2481  }
2482 
2483 }
2484 
2485 bool L1GtHwValidation::excludedAlgo(const int& iBit) const {
2486 
2487  for (std::vector<int>::const_iterator itAlgo = m_excludedAlgoList.begin(); itAlgo
2488  != m_excludedAlgoList.end(); ++itAlgo) {
2489 
2490  if (iBit == *itAlgo) {
2491  return true;
2492  }
2493  }
2494 
2495  return false;
2496 
2497 }
2498 
2499 //define this as a plug-in
2500 DEFINE_FWK_MODULE( L1GtHwValidation);
LogDebug
#define LogDebug(id)
Definition: MessageLogger.h:501
L1GtHwValidation::dqmBeginRun
virtual void dqmBeginRun(const edm::Run &, const edm::EventSetup &)
Definition: L1GtHwValidation.cc:161
edm::ParameterSet::getParameter
T getParameter(std::string const &) const
L1GtPsbWord::bData
const cms_uint16_t bData(int iB) const
get/set B_DATA_CH_IB
Definition: L1GtPsbWord.cc:323
L1GtHwValidation::m_fdlDataEmulAlgoDecision
MonitorElement * m_fdlDataEmulAlgoDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:244
L1GtHwValidation::m_fdlDataAlgoDecisionPrescaledMask_NoMatch
MonitorElement * m_fdlDataAlgoDecisionPrescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:227
L1GtPsbWord::bxNr
const cms_uint16_t bxNr() const
get/set bunch cross number of the actual bx
Definition: L1GtPsbWord.h:108
L1GtFdlWord::gtTechnicalTriggerWord
const TechnicalTriggerWord & gtTechnicalTriggerWord() const
get/set technical trigger bits
Definition: L1GtFdlWord.h:149
L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaled_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionUnprescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:237
L1GtHwValidation::m_l1GtTmTech
const L1GtTriggerMask * m_l1GtTmTech
Definition: L1GtHwValidation.h:190
L1GtPsbWord::boardId
const cms_uint16_t boardId() const
get/set board ID
Definition: L1GtPsbWord.h:66
L1GtHwValidation::m_fdlDataAlgoDecision_Err
MonitorElement * m_fdlDataAlgoDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:229
L1GtFdlWord::noAlgo
const cms_uint16_t noAlgo() const
get/set NoAlgo
Definition: L1GtFdlWord.h:286
L1GtHwValidation::m_l1GtDataEvmInputToken_
edm::EDGetTokenT< L1GlobalTriggerEvmReadoutRecord > m_l1GtDataEvmInputToken_
Definition: L1GtHwValidation.h:289
L1GtHwValidation::compareGTFE
virtual void compareGTFE(const edm::Event &, const edm::EventSetup &, const L1GtfeWord &, const L1GtfeWord &, const int)
compare the GTFE board
Definition: L1GtHwValidation.cc:826
L1GtHwValidation::matchCondCategory
bool matchCondCategory(const L1GtConditionCategory &, const L1GtConditionCategory &)
book all histograms for the module
Definition: L1GtHwValidation.cc:2266
L1GtHwValidation::analyze
virtual void analyze(const edm::Event &, const edm::EventSetup &)
Definition: L1GtHwValidation.cc:2248
L1GtHwValidation::comparePSB
virtual void comparePSB(const edm::Event &, const edm::EventSetup &, const L1GtPsbWord &, const L1GtPsbWord &)
compare the PSB board
Definition: L1GtHwValidation.cc:1795
L1GtfeWord::print
virtual void print(std::ostream &myCout) const
pretty print the content of a L1GtfeWord
Definition: L1GtfeWord.cc:321
L1GtHwValidation::m_prescaleFactorsAlgoTrig
const std::vector< std::vector< int > > * m_prescaleFactorsAlgoTrig
Definition: L1GtHwValidation.h:183
L1GtHwValidation::m_gtErrorFlag
MonitorElement * m_gtErrorFlag
PSB.
Definition: L1GtHwValidation.h:276
edm::Event::getByToken
bool getByToken(EDGetToken token, Handle< PROD > &result) const
Definition: Event.h:449
ConditionMap
std::map< std::string, L1GtCondition * > ConditionMap
map containing the conditions
Definition: L1GtTriggerMenuFwd.h:28
DEFINE_FWK_MODULE
#define DEFINE_FWK_MODULE(type)
Definition: MakerMacros.h:17
AlgorithmMap
std::map< std::string, L1GtAlgorithm > AlgorithmMap
map containing the algorithms
Definition: L1GtTriggerMenuFwd.h:31
L1GlobalTriggerReadoutSetup::NumberTechnicalTriggers
static const unsigned int NumberTechnicalTriggers
Definition: L1GlobalTriggerReadoutSetup.h:41
L1GtHwValidation::m_fdlEmulTechDecision
MonitorElement * m_fdlEmulTechDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:257
CItCond
ConditionMap::const_iterator CItCond
iterators through map containing the conditions
Definition: L1GtTriggerMenuFwd.h:34
L1GtHwValidation::m_excludedCondType
std::vector< L1GtConditionType > m_excludedCondType
excluded condition types
Definition: L1GtHwValidation.h:157
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void setBinLabel(int bin, const std::string &label, int axis=1)
set bin label for x, y or z axis (axis=1, 2, 3 respectively)
Definition: MonitorElement.cc:920
L1GtHwValidation::m_fdlDataEmulAlgoDecisionPrescaled
MonitorElement * m_fdlDataEmulAlgoDecisionPrescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:245
L1GtTriggerMenu::gtTriggerMenuImplementation
const std::string & gtTriggerMenuImplementation() const
Definition: L1GtTriggerMenu.h:106
L1GtHwValidation::m_fdlDataEmulAlgoDecisionUnprescaledAllowed
MonitorElement * m_fdlDataEmulAlgoDecisionUnprescaledAllowed[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:247
L1GtHwValidation::excludedAlgoList
void excludedAlgoList()
exclude from comparison some bits with known disagreement - bit list
Definition: L1GtHwValidation.cc:2329
L1GtHwValidation::m_fdlDataAlgoDecisionUnprescaledMask_NoMatch
MonitorElement * m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:228
l1GtConditionCategoryEnumToString
std::string l1GtConditionCategoryEnumToString(const L1GtConditionCategory &)
Definition: L1GtDefinitions.cc:248
L1GtHwValidation::m_l1GtEmulEvmInputTag
edm::InputTag m_l1GtEmulEvmInputTag
input tag for the L1 GT emulator EVM record
Definition: L1GtHwValidation.h:132
L1GtHwValidation::m_fdlEmulAlgoDecisionMask
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Definition: L1GtHwValidation.h:234
L1GtConditionType
L1GtConditionType
Definition: L1GtDefinitions.h:99
L1GtTriggerMenu::gtConditionMap
const std::vector< ConditionMap > & gtConditionMap() const
get / set / build the condition maps
Definition: L1GtTriggerMenu.h:84
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MonitorElement * m_fdlDataAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:221
L1GtHwValidation::m_l1GtMenuCacheID
unsigned long long m_l1GtMenuCacheID
Definition: L1GtHwValidation.h:174
L1GtHwValidation::m_l1GtPfTech
const L1GtPrescaleFactors * m_l1GtPfTech
Definition: L1GtHwValidation.h:180
l1GtObjectEnumToString
std::string l1GtObjectEnumToString(const L1GtObject &)
Definition: L1GtObject.cc:74
HLT_25ns14e33_v1_cff.InputTag
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Definition: HLT_25ns14e33_v1_cff.py:45333
L1GtHwValidation::m_fdlEmulAlgoDecisionPrescaledMask_NoMatch
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Definition: L1GtHwValidation.h:239
L1GtHwValidation::compareFDL
virtual void compareFDL(const edm::Event &, const edm::EventSetup &, const L1GtFdlWord &, const L1GtFdlWord &, const int)
compare the FDL board
Definition: L1GtHwValidation.cc:1033
L1GtfeWord::altNrBxBoard
const cms_uint16_t altNrBxBoard() const
get/set alternative for number of BX per board
Definition: L1GtfeWord.h:187
L1GtHwValidation::matchCondL1GtObject
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Definition: L1GtHwValidation.cc:2301
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Definition: AlCaHLTBitMon_QueryRunRegistry.py:255
L1GtHwValidation::m_excludeAlgoTrigByBit
std::vector< int > m_excludeAlgoTrigByBit
exclude algorithm triggers from comparison data - emulator by algorithm bit number ...
Definition: L1GtHwValidation.h:148
L1GtHwValidation::compareTCS
virtual void compareTCS(const edm::Event &, const edm::EventSetup &, const L1TcsWord &, const L1TcsWord &)
compare the TCS board
Definition: L1GtHwValidation.cc:1976
MonitorElement::Fill
void Fill(long long x)
Definition: MonitorElement.h:170
CItAlgo
AlgorithmMap::const_iterator CItAlgo
iterators through map containing the algorithms
Definition: L1GtTriggerMenuFwd.h:38
L1GtHwValidation::m_l1GtTmAlgoCacheID
unsigned long long m_l1GtTmAlgoCacheID
Definition: L1GtHwValidation.h:188
L1GtHwValidation::m_fdlEmulTechDecisionMask
MonitorElement * m_fdlEmulTechDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:258
L1GtFdlWord::bxNr
const cms_uint16_t bxNr() const
get/set BxNr - bunch cross number of the actual bx
Definition: L1GtFdlWord.h:110
L1GtHwValidation::m_fdlDataAlgoDecisionPrescaled
MonitorElement * m_fdlDataAlgoDecisionPrescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:220
L1GtFdlWord::boardId
const cms_uint16_t boardId() const
get/set board ID
Definition: L1GtFdlWord.h:69
L1GtHwValidation::m_fdlDataAlgoDecisionMask_NoMatch
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Definition: L1GtHwValidation.h:226
L1GtFdlWord::printGtDecisionWord
void printGtDecisionWord(std::ostream &myCout) const
Definition: L1GtFdlWord.cc:345
L1GtfeWord::recordLength
const cms_uint16_t recordLength() const
get/set record length for alternative 0
Definition: L1GtfeWord.h:104
L1GtFdlWord::eventNr
const cms_uint32_t eventNr() const
get/set event number since last L1 reset generated in FDL
Definition: L1GtFdlWord.h:130
L1GtHwValidation::m_gtfeDataEmul
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histograms
Definition: L1GtHwValidation.h:214
l1GtConditionTypeStringToEnum
L1GtConditionType l1GtConditionTypeStringToEnum(const std::string &)
Definition: L1GtDefinitions.cc:195
L1GtHwValidation::m_fdlDataAlgoDecisionUnprescaled_NoMatch
MonitorElement * m_fdlDataAlgoDecisionUnprescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:225
DecisionWordExtended
std::vector< bool > DecisionWordExtended
Definition: L1GlobalTriggerReadoutSetupFwd.h:38
L1GtHwValidation::m_triggerMaskTechTrig
std::vector< unsigned int > m_triggerMaskTechTrig
Definition: L1GtHwValidation.h:194
iEvent
int iEvent
Definition: GenABIO.cc:230
L1GtHwValidation::~L1GtHwValidation
virtual ~L1GtHwValidation()
Definition: L1GtHwValidation.cc:155
L1GtHwValidation::m_fdlDataEmulAlgoDecisionMask
MonitorElement * m_fdlDataEmulAlgoDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:248
l1GtObjectStringToEnum
L1GtObject l1GtObjectStringToEnum(const std::string &)
Definition: L1GtObject.cc:24
L1GtPsbWord::aData
const cms_uint16_t aData(int iA) const
get/set A_DATA_CH_IA
Definition: L1GtPsbWord.cc:228
L1GtHwValidation::m_excludedL1GtObject
std::vector< L1GtObject > m_excludedL1GtObject
excluded L1 GT objects
Definition: L1GtHwValidation.h:160
L1GtHwValidation::m_fdlDataAlgoDecisionPrescaled_NoMatch
MonitorElement * m_fdlDataAlgoDecisionPrescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:224
L1GtTriggerMask::gtTriggerMask
const std::vector< unsigned int > & gtTriggerMask() const
get the trigger mask
Definition: L1GtTriggerMask.h:51
L1GtHwValidation::m_excludeAlgoTrigByName
std::vector< std::string > m_excludeAlgoTrigByName
exclude algorithm triggers from comparison data - emulator by algorithm name
Definition: L1GtHwValidation.h:145
DecisionWord
std::vector< bool > DecisionWord
typedefs
Definition: L1GlobalTriggerReadoutSetupFwd.h:34
L1GtHwValidation::m_excludedAlgorithmsAgreement
MonitorElement * m_excludedAlgorithmsAgreement
Definition: L1GtHwValidation.h:269
L1GtHwValidation::m_l1GtTmAlgo
const L1GtTriggerMask * m_l1GtTmAlgo
trigger masks
Definition: L1GtHwValidation.h:187
L1GtHwValidation::m_agree
bool m_agree
internal members
Definition: L1GtHwValidation.h:200
L1GtHwValidation::m_l1GtEmulDaqInputTag
edm::InputTag m_l1GtEmulDaqInputTag
input tag for the L1 GT emulator DAQ record
Definition: L1GtHwValidation.h:129
L1GtHwValidation::m_fdlDataEmulTechDecision
MonitorElement * m_fdlDataEmulTechDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:261
L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:240
L1GtFdlWord::bxInEvent
const int bxInEvent() const
get/set bunch cross in the GT event record
Definition: L1GtFdlWord.h:90
L1GtfeWord::totalTriggerNr
const cms_uint32_t totalTriggerNr() const
get/set total number of L1A sent since start of run
Definition: L1GtfeWord.h:211
L1GtFdlWord::printGtDecisionWordExtended
void printGtDecisionWordExtended(std::ostream &myCout) const
Definition: L1GtFdlWord.cc:503
DQMStore::IBooker::book1D
MonitorElement * book1D(Args &&...args)
Definition: DQMStore.h:115
L1GtConditionCategory
L1GtConditionCategory
condition categories
Definition: L1GtDefinitions.h:128
L1GtHwValidation::compareEvmRecord
virtual void compareEvmRecord(const edm::Event &, const edm::EventSetup &)
L1 GT EVM record comparison.
Definition: L1GtHwValidation.cc:2150
L1GtHwValidation::m_fdlDataTechDecision_Err
MonitorElement * m_fdlDataTechDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:255
L1GtHwValidation::matchCondType
bool matchCondType(const L1GtConditionType &, const L1GtConditionType &)
Definition: L1GtHwValidation.cc:2284
L1GtHwValidation::m_fdlDataAlgoDecision
MonitorElement * m_fdlDataAlgoDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:219
TechnicalTriggerWord
std::vector< bool > TechnicalTriggerWord
technical trigger bits (64 bits)
Definition: L1GlobalTriggerReadoutSetupFwd.h:41
L1GtHwValidation::L1GtHwValidation
L1GtHwValidation(const edm::ParameterSet &)
Definition: L1GtHwValidation.cc:52
L1GlobalTriggerReadoutSetup::NumberPhysTriggers
static const unsigned int NumberPhysTriggers
Definition: L1GlobalTriggerReadoutSetup.h:39
l1GtConditionCategoryStringToEnum
L1GtConditionCategory l1GtConditionCategoryStringToEnum(const std::string &)
Definition: L1GtDefinitions.cc:229
L1GtHwValidation::m_l1GtDataDaqInputToken_
edm::EDGetTokenT< L1GlobalTriggerReadoutRecord > m_l1GtDataDaqInputToken_
Definition: L1GtHwValidation.h:287
L1GtHwValidation::TotalBxInEvent
static const int TotalBxInEvent
Definition: L1GtHwValidation.h:208
L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaled
MonitorElement * m_fdlEmulAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:233
L1GtPsbWord::localBxNr
const cms_uint16_t localBxNr() const
get/set local bunch cross number of the actual bx
Definition: L1GtPsbWord.h:178
edm::HandleBase::isValid
bool isValid() const
Definition: HandleBase.h:75
L1GtfeWord::activeBoards
const cms_uint16_t activeBoards() const
get/set boards contributing to EVM respectively DAQ record
Definition: L1GtfeWord.h:163
LogTrace
#define LogTrace(id)
Definition: MessageLogger.h:502
L1GtHwValidation::m_l1GtMenu
const L1GtTriggerMenu * m_l1GtMenu
trigger menu
Definition: L1GtHwValidation.h:173
L1GtHwValidation::m_fdlEmulAlgoDecision_Err
MonitorElement * m_fdlEmulAlgoDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:241
L1GtfeWord::bxNr
const cms_uint16_t bxNr() const
get/set bunch cross number as counted in the GTFE board
Definition: L1GtfeWord.h:122
L1GtHwValidation::m_l1GtEmulEvmInputToken_
edm::EDGetTokenT< L1GlobalTriggerEvmReadoutRecord > m_l1GtEmulEvmInputToken_
Definition: L1GtHwValidation.h:290
L1GtFdlWord::print
void print(std::ostream &myCout) const
pretty print the content of a L1GtFdlWord
Definition: L1GtFdlWord.cc:766
L1GtPsbWord::print
void print(std::ostream &myCout) const
pretty print
Definition: L1GtPsbWord.cc:453
dtDQMClient_cfg.prescaleFactor
tuple prescaleFactor
Definition: dtDQMClient_cfg.py:51
l1GtConditionTypeEnumToString
std::string l1GtConditionTypeEnumToString(const L1GtConditionType &)
Definition: L1GtDefinitions.cc:215
L1GtfeWord::boardId
const cms_uint16_t boardId() const
get/set board ID
Definition: L1GtfeWord.h:65
L1GtHwValidation::m_l1GtPfAlgoCacheID
unsigned long long m_l1GtPfAlgoCacheID
Definition: L1GtHwValidation.h:178
L1GtPsbWord::eventNr
const cms_uint32_t eventNr() const
get/set event number since last L1 reset generated in PSB
Definition: L1GtPsbWord.h:129
L1GtHwValidation::m_fdlDataTechDecisionMask
MonitorElement * m_fdlDataTechDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:254
L1GtHwValidation::m_l1GtDataDaqInputTag
edm::InputTag m_l1GtDataDaqInputTag
input tag for the L1 GT hardware DAQ record
Definition: L1GtHwValidation.h:123
L1GtHwValidation::m_fdlDataAlgoDecision_NoMatch
MonitorElement * m_fdlDataAlgoDecision_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:223
L1GtHwValidation::m_fdlDataEmul
MonitorElement * m_fdlDataEmul[TotalBxInEvent][NumberOfGtRecords]
FDL (0 for DAQ, 1 for EVM record)
Definition: L1GtHwValidation.h:217
L1GtFdlWord::gtPrescaleFactorIndexAlgo
const cms_uint16_t gtPrescaleFactorIndexAlgo() const
Definition: L1GtFdlWord.h:267
L1GtHwValidation::m_fdlDataEmul_Err
MonitorElement * m_fdlDataEmul_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:250
DQMStore::IBooker::setCurrentFolder
void setCurrentFolder(const std::string &fullpath)
Definition: DQMStore.cc:274
L1GtPrescaleFactors::gtPrescaleFactors
const std::vector< std::vector< int > > & gtPrescaleFactors() const
get the prescale factors by reference
Definition: L1GtPrescaleFactors.h:49
L1GtHwValidation::m_l1GtEmulDaqInputToken_
edm::EDGetTokenT< L1GlobalTriggerReadoutRecord > m_l1GtEmulDaqInputToken_
Definition: L1GtHwValidation.h:288
L1GtHwValidation::m_excludedCondCategory
std::vector< L1GtConditionCategory > m_excludedCondCategory
excluded condition categories
Definition: L1GtHwValidation.h:154
L1GtHwValidation::m_myCoutStream
std::ostringstream m_myCoutStream
Definition: L1GtHwValidation.h:164
L1GtHwValidation::bookHistograms
virtual void bookHistograms(DQMStore::IBooker &ibooker, const edm::Run &, const edm::EventSetup &) override
Definition: L1GtHwValidation.cc:168
L1GtPsbWord::NumberBData
static const int NumberBData
Definition: L1GtPsbWord.h:35
L1GtHwValidation::m_nrDataEventError
int m_nrDataEventError
counters
Definition: L1GtHwValidation.h:167
edm::EventSetup::get
const T & get() const
Definition: EventSetup.h:55
edm::ESHandle::product
T const * product() const
Definition: ESHandle.h:86
L1GtHwValidation::m_fdlEmulAlgoDecisionMask_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:238
L1GtPsbWord::bxInEvent
const int bxInEvent() const
get/set bunch cross in the GT event record
Definition: L1GtPsbWord.h:87
L1GtFdlWord::gtDecisionWord
const DecisionWord & gtDecisionWord() const
get/set/print algorithms bits (decision word)
Definition: L1GtFdlWord.h:171
L1GtHwValidation::m_l1GtTmTechCacheID
unsigned long long m_l1GtTmTechCacheID
Definition: L1GtHwValidation.h:191
L1GtHwValidation::compareGt_Gct
virtual void compareGt_Gct(const edm::Event &, const edm::EventSetup &)
Definition: L1GtHwValidation.cc:2240
L1GtHwValidation::m_fdlEmulTechDecision_Err
MonitorElement * m_fdlEmulTechDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:259
L1GtPsbWord::NumberAData
static const int NumberAData
Definition: L1GtPsbWord.h:34
L1GtHwValidation::m_l1GctDataInputTag
edm::InputTag m_l1GctDataInputTag
input tag for the L1 GCT hardware record
Definition: L1GtHwValidation.h:135
L1GtHwValidation::m_excludeCondCategTypeObject
std::vector< edm::ParameterSet > m_excludeCondCategTypeObject
Definition: L1GtHwValidation.h:142
L1GtFdlWord::printGtTechnicalTriggerWord
void printGtTechnicalTriggerWord(std::ostream &myCout) const
Definition: L1GtFdlWord.cc:271
L1GtHwValidation::m_fdlDataEmulAlgoDecision_Err
MonitorElement * m_fdlDataEmulAlgoDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:249
L1GtfeWord::setupVersion
const cms_uint32_t setupVersion() const
get/set setup version
Definition: L1GtfeWord.h:140
L1GtTriggerMenu::gtAlgorithmMap
const AlgorithmMap & gtAlgorithmMap() const
get / set the algorithm map (by name)
Definition: L1GtTriggerMenu.h:241
L1GtHwValidation::NumberOfGtRecords
static const int NumberOfGtRecords
Definition: L1GtHwValidation.h:209
L1GtHwValidation::m_fdlDataTechDecision
MonitorElement * m_fdlDataTechDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:253
L1GtHwValidation::m_fdlEmulAlgoDecision
MonitorElement * m_fdlEmulAlgoDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:231
L1GtHwValidation::m_prescaleFactorsTechTrig
const std::vector< std::vector< int > > * m_prescaleFactorsTechTrig
Definition: L1GtHwValidation.h:184
edm::false
volatile std::atomic< bool > shutdown_flag false
Definition: UnixSignalHandlers.cc:22
L1GtHwValidation::m_fdlEmulAlgoDecision_NoMatch
MonitorElement * m_fdlEmulAlgoDecision_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:235
L1GtFdlWord::gtDecisionWordExtended
const DecisionWordExtended & gtDecisionWordExtended() const
get/set extended algorithms bits (extended decision word)
Definition: L1GtFdlWord.h:203
L1GtHwValidation::m_fdlDataEmulTechDecisionMask
MonitorElement * m_fdlDataEmulTechDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:262
L1GtHwValidation::m_fdlDataAlgoDecisionMask
MonitorElement * m_fdlDataAlgoDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:222
L1GtHwValidation::compareDaqRecord
virtual void compareDaqRecord(const edm::Event &, const edm::EventSetup &)
L1 GT DAQ record comparison.
Definition: L1GtHwValidation.cc:1982
L1GtfeWord::recordLength1
const cms_uint16_t recordLength1() const
get/set record length for alternative 1
Definition: L1GtfeWord.h:85
L1GtHwValidation::m_triggerMaskAlgoTrig
std::vector< unsigned int > m_triggerMaskAlgoTrig
Definition: L1GtHwValidation.h:193
L1GtHwValidation::m_excludedAlgoList
std::vector< int > m_excludedAlgoList
Definition: L1GtHwValidation.h:284
L1GtHwValidation::m_fdlDataEmulTechDecision_Err
MonitorElement * m_fdlDataEmulTechDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:263
L1GtHwValidation::m_fdlEmulAlgoDecisionPrescaled_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionPrescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:236
L1GtHwValidation::beginLuminosityBlock
virtual void beginLuminosityBlock(const edm::LuminosityBlock &, const edm::EventSetup &)
Definition: L1GtHwValidation.cc:164
L1GtFdlWord::localBxNr
const cms_uint16_t localBxNr() const
get/set local bunch cross number of the actual bx
Definition: L1GtFdlWord.h:372
L1GtHwValidation::m_l1GtPfAlgo
const L1GtPrescaleFactors * m_l1GtPfAlgo
prescale factors
Definition: L1GtHwValidation.h:177
L1GtHwValidation::m_l1GtDataEvmInputTag
edm::InputTag m_l1GtDataEvmInputTag
input tag for the L1 GT hardware EVM record
Definition: L1GtHwValidation.h:126
edm::Run
Definition: Run.h:41
L1GtFdlWord::finalOR
const cms_uint16_t finalOR() const
get/set &quot;Final OR&quot; bits
Definition: L1GtFdlWord.h:306
L1GtHwValidation::m_l1GtPfTechCacheID
unsigned long long m_l1GtPfTechCacheID
Definition: L1GtHwValidation.h:181
asciidump.at
list at
Definition: asciidump.py:428
L1GtHwValidation::m_fdlEmulAlgoDecisionPrescaled
MonitorElement * m_fdlEmulAlgoDecisionPrescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:232
L1GtHwValidation::excludedAlgo
bool excludedAlgo(const int &) const
exclusion status for algorithm with bit i
Definition: L1GtHwValidation.cc:2485
L1GtHwValidation::m_dirName
std::string m_dirName
directory name for L1Extra plots
Definition: L1GtHwValidation.h:138
L1GtHwValidation::m_fdlDataEmulAlgoDecisionUnprescaled
MonitorElement * m_fdlDataEmulAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:246
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