CMS 3D CMS Logo
 All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Properties Friends Macros Pages
L1MuCSCTFConfiguration.cc
Go to the documentation of this file.
1 #include "CondFormats/L1TObjects/interface/L1MuCSCTFConfiguration.h"
2 #include <sstream>
3 #include <iostream>
4 #include <stdlib.h>
5 #include "FWCore/MessageLogger/interface/MessageLogger.h"
6 
7 edm::ParameterSet L1MuCSCTFConfiguration::parameters(int sp) const {
8 
9  LogDebug("L1MuCSCTFConfiguration") << "SP:"<<int(sp)<< std::endl;
10 
11  edm::ParameterSet pset;
12  if(sp>=12) return pset;
13 
14  // ------------------------------------------------------
15  // core configuration
16  // by default everything is disabled: we need to set them
17  // coincidence and singles
18  bool run_core = 0;
19  bool trigger_on_ME1a = 0;
20  bool trigger_on_ME1b = 0;
21  bool trigger_on_ME2 = 0;
22  bool trigger_on_ME3 = 0;
23  bool trigger_on_ME4 = 0;
24  bool trigger_on_MB1a = 0;
25  bool trigger_on_MB1d = 0;
26 
27  unsigned int BXAdepth = 0;
28  unsigned int useDT = 0;
29  unsigned int widePhi = 0;
30  unsigned int PreTrigger = 0;
31  // ------------------------------------------------------
32 
33  // ------------------------------------------------------
34  // these are very important parameters.
35  // Double check with Alex
36  unsigned int CoreLatency = 7;
37  bool rescaleSinglesPhi = 1;
38 
39  // ask Alex if use or remove them or what
40  bool AllowALCTonly = 0;
41  bool AllowCLCTonly = 0;
42 
43  // other useful parameters in general not set in the OMDS
44  unsigned int QualityEnableME1a = 0xFFFF;
45  unsigned int QualityEnableME1b = 0xFFFF;
46  unsigned int QualityEnableME1c = 0xFFFF;
47  unsigned int QualityEnableME1d = 0xFFFF;
48  unsigned int QualityEnableME1e = 0xFFFF;
49  unsigned int QualityEnableME1f = 0xFFFF;
50  unsigned int QualityEnableME2a = 0xFFFF;
51  unsigned int QualityEnableME2b = 0xFFFF;
52  unsigned int QualityEnableME2c = 0xFFFF;
53  unsigned int QualityEnableME3a = 0xFFFF;
54  unsigned int QualityEnableME3b = 0xFFFF;
55  unsigned int QualityEnableME3c = 0xFFFF;
56  unsigned int QualityEnableME4a = 0xFFFF;
57  unsigned int QualityEnableME4b = 0xFFFF;
58  unsigned int QualityEnableME4c = 0xFFFF;
59 
60  unsigned int kill_fiber = 0;
61  unsigned int singlesTrackOutput = 1;
62  // ------------------------------------------------------
63 
64 
65  //initialization of the DAT_ETA registers with default values
66  //the DAT_ETA registers meaning are explained at Table 2 of
67  //http://www.phys.ufl.edu/~uvarov/SP05/LU-SP_ReferenceGuide_090915_Update.pdf
68  std::vector<unsigned int> etamin(8), etamax(8), etawin(7);
69 
70  unsigned int mindetap = 8;
71  unsigned int mindetap_halo = 8;
72 
73  etamin[0] = 22;
74  etamin[1] = 22;
75  etamin[2] = 14;
76  etamin[3] = 14;
77  etamin[4] = 14;
78  etamin[5] = 14;
79  etamin[6] = 10;
80  etamin[7] = 22;
81 
82  unsigned int mindeta12_accp = 8;
83  unsigned int mindeta13_accp = 19;
84  unsigned int mindeta112_accp = 19;
85  unsigned int mindeta113_accp = 30;
86 
87  etamax[0] = 127;
88  etamax[1] = 127;
89  etamax[2] = 127;
90  etamax[3] = 127;
91  etamax[4] = 127;
92  etamax[5] = 24;
93  etamax[6] = 24;
94  etamax[7] = 127;
95 
96  unsigned int maxdeta12_accp = 14;
97  unsigned int maxdeta13_accp = 25;
98  unsigned int maxdeta112_accp = 25;
99  unsigned int maxdeta113_accp = 36;
100 
101  etawin[0] = 4;
102  etawin[1] = 4;
103  etawin[2] = 4;
104  etawin[3] = 4;
105  etawin[4] = 4;
106  etawin[5] = 4;
107  etawin[6] = 4;
108 
109  unsigned int maxdphi12_accp = 64;
110  unsigned int maxdphi13_accp = 64;
111  unsigned int maxdphi112_accp = 64;
112  unsigned int maxdphi113_accp = 64;
113 
114  unsigned int mindphip = 128;
115  unsigned int mindphip_halo = 128;
116 
117  unsigned int straightp = 60;
118  unsigned int curvedp = 200;
119 
120  unsigned int mbaPhiOff = 0;
121  // this differ from the default value in the documentation because during
122  // craft 09 it mbbPhiOff, as well as mbaPhiOff were not existing, thus set to 0 (they are offsets)
123  // and for backward compatibility it needs to be set to 0. Anyway mbbPhiOff since its introduction in the
124  // core will have to be ALWAYS part of the configuration, so it won't be never initialized to the
125  // default value 2048.
126  unsigned int mbbPhiOff = 0;
127 
128  int eta_cnt=0;
129 
130  // default firmware versions (the ones used from run 132440)
131  unsigned int firmwareSP=20100210;
132  unsigned int firmwareFA=20090521;
133  unsigned int firmwareDD=20090521;
134  unsigned int firmwareVM=20090521;
135 
136  // default printout
137  LogDebug("L1MuCSCTFConfiguration") << "\nCORE CONFIGURATION DEFAULT VALUES"
138  << "\nrun_core=" << run_core
139  << "\ntrigger_on_ME1a=" << trigger_on_ME1a
140  << "\ntrigger_on_ME1b=" << trigger_on_ME1b
141  << "\ntrigger_on_ME2=" << trigger_on_ME2
142  << "\ntrigger_on_ME3=" << trigger_on_ME3
143  << "\ntrigger_on_ME4=" << trigger_on_ME4
144  << "\ntrigger_on_MB1a=" << trigger_on_MB1a
145  << "\ntrigger_on_MB1d=" << trigger_on_MB1d
146 
147  << "\nBXAdepth=" << BXAdepth
148  << "\nuseDT=" << useDT
149  << "\nwidePhi=" << widePhi
150  << "\nPreTrigger=" << PreTrigger
151 
152  << "\nCoreLatency="<< CoreLatency
153  << "\nrescaleSinglesPhi=" << rescaleSinglesPhi
154 
155  << "\n\nVARIOUS CONFIGURATION PARAMETERS DEFAULT VALUES"
156  << "\nAllowALCTonly=" << AllowALCTonly
157  << "\nAllowCLCTonly=" << AllowCLCTonly
158 
159  << "\nQualityEnableME1a=" << QualityEnableME1a
160  << "\nQualityEnableME1b=" << QualityEnableME1b
161  << "\nQualityEnableME1c=" << QualityEnableME1c
162  << "\nQualityEnableME1d=" << QualityEnableME1d
163  << "\nQualityEnableME1e=" << QualityEnableME1e
164  << "\nQualityEnableME1f=" << QualityEnableME1f
165  << "\nQualityEnableME2a=" << QualityEnableME2a
166  << "\nQualityEnableME2b=" << QualityEnableME2b
167  << "\nQualityEnableME2c=" << QualityEnableME2c
168  << "\nQualityEnableME3a=" << QualityEnableME3a
169  << "\nQualityEnableME3b=" << QualityEnableME3b
170  << "\nQualityEnableME3c=" << QualityEnableME3c
171  << "\nQualityEnableME4a=" << QualityEnableME4a
172  << "\nQualityEnableME4b=" << QualityEnableME4b
173  << "\nQualityEnableME4c=" << QualityEnableME4c
174 
175  << "\nkill_fiber=" << kill_fiber
176  << "\nsinglesTrackOutput=" << singlesTrackOutput
177 
178  << "\n\nDEFAULT VALUES FOR DAT_ETA"
179  << "\nmindetap =" << mindetap
180  << "\nmindetap_halo=" << mindetap_halo
181 
182  << "\netamin[0]=" << etamin[0]
183  << "\netamin[1]=" << etamin[1]
184  << "\netamin[2]=" << etamin[2]
185  << "\netamin[3]=" << etamin[3]
186  << "\netamin[4]=" << etamin[4]
187  << "\netamin[5]=" << etamin[5]
188  << "\netamin[6]=" << etamin[6]
189  << "\netamin[7]=" << etamin[7]
190 
191  << "\nmindeta12_accp =" << mindeta12_accp
192  << "\nmindeta13_accp =" << mindeta13_accp
193  << "\nmindeta112_accp=" << mindeta112_accp
194  << "\nmindeta113_accp=" << mindeta113_accp
195 
196  << "\netamax[0]=" << etamax[0]
197  << "\netamax[1]=" << etamax[1]
198  << "\netamax[2]=" << etamax[2]
199  << "\netamax[3]=" << etamax[3]
200  << "\netamax[4]=" << etamax[4]
201  << "\netamax[5]=" << etamax[5]
202  << "\netamax[6]=" << etamax[6]
203  << "\netamax[7]=" << etamax[7]
204 
205  << "\nmaxdeta12_accp =" << maxdeta12_accp
206  << "\nmaxdeta13_accp =" << maxdeta13_accp
207  << "\nmaxdeta112_accp=" << maxdeta112_accp
208  << "\nmaxdeta113_accp=" << maxdeta113_accp
209 
210  << "\netawin[0]=" << etawin[0]
211  << "\netawin[1]=" << etawin[1]
212  << "\netawin[2]=" << etawin[2]
213  << "\netawin[3]=" << etawin[3]
214  << "\netawin[4]=" << etawin[4]
215  << "\netawin[5]=" << etawin[5]
216  << "\netawin[6]=" << etawin[6]
217 
218  << "\nmaxdphi12_accp =" << maxdphi12_accp
219  << "\nmaxdphi13_accp =" << maxdphi13_accp
220  << "\nmaxdphi112_accp=" << maxdphi112_accp
221  << "\nmaxdphi113_accp=" << maxdphi113_accp
222 
223  << "\nmindphip =" << mindphip
224  << "\nmindphip_halo=" << mindphip_halo
225 
226  << "\nstraightp=" << straightp
227  << "\ncurvedp =" << curvedp
228  << "\nmbaPhiOff=" << mbaPhiOff
229  << "\nmbbPhiOff=" << mbbPhiOff
230 
231  << "\n\nFIRMWARE VERSIONS"
232  << "\nSP: " << firmwareSP
233  << "\nFA: " << firmwareFA
234  << "\nDD: " << firmwareDD
235  << "\nVM: " << firmwareVM;
236 
237  // start filling the registers with the values in the DBS
238  std::stringstream conf(registers[sp]);
239  while( !conf.eof() ){
240  char buff[1024];
241  conf.getline(buff,1024);
242  std::stringstream line(buff);
243  //std::cout<<"buff:"<<buff<<std::endl;
244  std::string register_; line>>register_;
245  std::string chip_; line>>chip_;
246  std::string muon_; line>>muon_;
247  std::string writeValue_; line>>writeValue_;
248  std::string comments_; std::getline(line,comments_);
249 
250  if( register_=="CSR_REQ" && chip_=="SP" ){
251  unsigned int value = ::strtol(writeValue_.c_str(),NULL,16);
252  run_core = (value&0x8000);
253  trigger_on_ME1a = (value&0x0001);
254  trigger_on_ME1b = (value&0x0002);
255  trigger_on_ME2 = (value&0x0004);
256  trigger_on_ME3 = (value&0x0008);
257  trigger_on_ME4 = (value&0x0010);
258  trigger_on_MB1a = (value&0x0100);
259  trigger_on_MB1d = (value&0x0200);
260  }
261 
262 
263  if( register_=="CSR_SCC" && chip_=="SP" ){
264  unsigned int value = ::strtol(writeValue_.c_str(),NULL,16);
265 
266  BXAdepth = (value&0x3);
267  useDT = ( (value&0x80)>>7 );
268  widePhi = ( (value&0x40)>>6 );
269  PreTrigger = ( (value&0x300)>>8);
270  }
271 
272 
273  if( register_=="CSR_LQE" && chip_=="F1" && muon_=="M1" )
274  QualityEnableME1a = ::strtol(writeValue_.c_str(),NULL,16);
275  if( register_=="CSR_LQE" && chip_=="F1" && muon_=="M2" )
276  QualityEnableME1b = ::strtol(writeValue_.c_str(),NULL,16);
277  if( register_=="CSR_LQE" && chip_=="F1" && muon_=="M3" )
278  QualityEnableME1c = ::strtol(writeValue_.c_str(),NULL,16);
279  if( register_=="CSR_LQE" && chip_=="F2" && muon_=="M1" )
280  QualityEnableME1d = ::strtol(writeValue_.c_str(),NULL,16);
281  if( register_=="CSR_LQE" && chip_=="F2" && muon_=="M2" )
282  QualityEnableME1e = ::strtol(writeValue_.c_str(),NULL,16);
283  if( register_=="CSR_LQE" && chip_=="F2" && muon_=="M3" )
284  QualityEnableME1f = ::strtol(writeValue_.c_str(),NULL,16);
285  if( register_=="CSR_LQE" && chip_=="F3" && muon_=="M1" )
286  QualityEnableME2a = ::strtol(writeValue_.c_str(),NULL,16);
287  if( register_=="CSR_LQE" && chip_=="F3" && muon_=="M2" )
288  QualityEnableME2b = ::strtol(writeValue_.c_str(),NULL,16);
289  if( register_=="CSR_LQE" && chip_=="F3" && muon_=="M3" )
290  QualityEnableME2c = ::strtol(writeValue_.c_str(),NULL,16);
291  if( register_=="CSR_LQE" && chip_=="F4" && muon_=="M1" )
292  QualityEnableME3a = ::strtol(writeValue_.c_str(),NULL,16);
293  if( register_=="CSR_LQE" && chip_=="F4" && muon_=="M2" )
294  QualityEnableME3b = ::strtol(writeValue_.c_str(),NULL,16);
295  if( register_=="CSR_LQE" && chip_=="F4" && muon_=="M3" )
296  QualityEnableME3c = ::strtol(writeValue_.c_str(),NULL,16);
297  if( register_=="CSR_LQE" && chip_=="F5" && muon_=="M1" )
298  QualityEnableME4a = ::strtol(writeValue_.c_str(),NULL,16);
299  if( register_=="CSR_LQE" && chip_=="F5" && muon_=="M2" )
300  QualityEnableME4b = ::strtol(writeValue_.c_str(),NULL,16);
301  if( register_=="CSR_LQE" && chip_=="F5" && muon_=="M3" )
302  QualityEnableME4c = ::strtol(writeValue_.c_str(),NULL,16);
303 
304  if( register_=="CSR_KFL" )
305  kill_fiber = ::strtol(writeValue_.c_str(),NULL,16);
306 
307  if( register_=="CSR_SFC" && chip_=="SP" ){
308  unsigned int value = ::strtol(writeValue_.c_str(),NULL,16);
309  singlesTrackOutput = ((value&0x3000)>>12);
310  }
311 
312  if( register_=="CNT_ETA" && chip_=="SP" ){
313  unsigned int value = ::strtol(writeValue_.c_str(),NULL,16);
314  eta_cnt = value;
315  }
316 
317 
318  // LATEST VERSION FROM CORE 2010-01-22 at http://www.phys.ufl.edu/~madorsky/sp/2010-01-22
319  if( register_=="DAT_ETA" && chip_=="SP" ){
320 
321  unsigned int value = ::strtol(writeValue_.c_str(),NULL,16);
322 
323  //std::cout<<"DAT_ETA SP value:"<<value<<std::endl;
324 
325  if (eta_cnt== 0) mindetap = value;
326  if (eta_cnt== 1) mindetap_halo = value;
327 
328  if (eta_cnt>= 2 && eta_cnt<10 ) etamin[eta_cnt-2] = value;
329 
330  if (eta_cnt==10) mindeta12_accp = value;
331  if (eta_cnt==11) mindeta13_accp = value;
332  if (eta_cnt==12) mindeta112_accp = value;
333  if (eta_cnt==13) mindeta113_accp = value;
334 
335  if (eta_cnt>=14 && eta_cnt<22 ) etamax[eta_cnt-14] = value;
336 
337  if (eta_cnt==22) maxdeta12_accp = value;
338  if (eta_cnt==23) maxdeta13_accp = value;
339  if (eta_cnt==24) maxdeta112_accp = value;
340  if (eta_cnt==25) maxdeta113_accp = value;
341 
342  if( eta_cnt>=26 && eta_cnt<33) etawin[eta_cnt-26] = value;
343 
344  if (eta_cnt==33) maxdphi12_accp = value;
345  if (eta_cnt==34) maxdphi13_accp = value;
346  if (eta_cnt==35) maxdphi112_accp = value;
347  if (eta_cnt==36) maxdphi113_accp = value;
348 
349  if (eta_cnt==37) mindphip = value;
350  if (eta_cnt==38) mindphip_halo = value;
351 
352  if (eta_cnt==39) straightp = value;
353  if (eta_cnt==40) curvedp = value;
354  if (eta_cnt==41) mbaPhiOff = value;
355  if (eta_cnt==42) mbbPhiOff = value;
356 
357  eta_cnt++;
358  }
359 
360  // filling the firmware variables: SP MEZZANINE
361  if( register_=="FIRMWARE" && muon_=="SP" ){
362  unsigned int value = atoi(writeValue_.c_str());
363  firmwareSP=value;
364  }
365 
366  // filling the firmware variables: Front FPGAs
367  if( register_=="FIRMWARE" && muon_=="FA" ){
368  unsigned int value = atoi(writeValue_.c_str());
369  firmwareFA=value;
370  }
371 
372  // filling the firmware variables: DDU
373  if( register_=="FIRMWARE" && muon_=="DD" ){
374  unsigned int value = atoi(writeValue_.c_str());
375  firmwareDD=value;
376  }
377 
378  // filling the firmware variables: VM
379  if( register_=="FIRMWARE" && muon_=="VM" ){
380  unsigned int value = atoi(writeValue_.c_str());
381  firmwareVM=value;
382  }
383  }
384 
385 
386 
387  pset.addParameter<bool>("run_core" , run_core );
388  pset.addParameter<bool>("trigger_on_ME1a", trigger_on_ME1a);
389  pset.addParameter<bool>("trigger_on_ME1b", trigger_on_ME1b);
390  pset.addParameter<bool>("trigger_on_ME2" , trigger_on_ME2 );
391  pset.addParameter<bool>("trigger_on_ME3" , trigger_on_ME3 );
392  pset.addParameter<bool>("trigger_on_ME4" , trigger_on_ME4 );
393  pset.addParameter<bool>("trigger_on_MB1a", trigger_on_MB1a);
394  pset.addParameter<bool>("trigger_on_MB1d", trigger_on_MB1d);
395 
396  pset.addParameter<unsigned int>("BXAdepth" , BXAdepth );
397  pset.addParameter<unsigned int>("useDT" , useDT );
398  pset.addParameter<unsigned int>("widePhi" , widePhi );
399  pset.addParameter<unsigned int>("PreTrigger", PreTrigger);
400 
401  // this were two old settings, not used anymore. Set them to zero
402  // ask Alex if he can remove them altogether
403  pset.addParameter<bool>("AllowALCTonly", AllowALCTonly);
404  pset.addParameter<bool>("AllowCLCTonly", AllowCLCTonly);
405 
406  pset.addParameter<int>("CoreLatency", CoreLatency);
407  pset.addParameter<bool>("rescaleSinglesPhi", rescaleSinglesPhi);
408 
409  pset.addParameter<unsigned int>("QualityEnableME1a",QualityEnableME1a);
410  pset.addParameter<unsigned int>("QualityEnableME1b",QualityEnableME1b);
411  pset.addParameter<unsigned int>("QualityEnableME1c",QualityEnableME1c);
412  pset.addParameter<unsigned int>("QualityEnableME1d",QualityEnableME1d);
413  pset.addParameter<unsigned int>("QualityEnableME1e",QualityEnableME1e);
414  pset.addParameter<unsigned int>("QualityEnableME1f",QualityEnableME1f);
415  pset.addParameter<unsigned int>("QualityEnableME2a",QualityEnableME2a);
416  pset.addParameter<unsigned int>("QualityEnableME2b",QualityEnableME2b);
417  pset.addParameter<unsigned int>("QualityEnableME2c",QualityEnableME2c);
418  pset.addParameter<unsigned int>("QualityEnableME3a",QualityEnableME3a);
419  pset.addParameter<unsigned int>("QualityEnableME3b",QualityEnableME3b);
420  pset.addParameter<unsigned int>("QualityEnableME3c",QualityEnableME3c);
421  pset.addParameter<unsigned int>("QualityEnableME4a",QualityEnableME4a);
422  pset.addParameter<unsigned int>("QualityEnableME4b",QualityEnableME4b);
423  pset.addParameter<unsigned int>("QualityEnableME4c",QualityEnableME4c);
424 
425  pset.addParameter<unsigned int>("kill_fiber",kill_fiber);
426  pset.addParameter<unsigned int>("singlesTrackOutput",singlesTrackOutput);
427 
428  // add the DAT_ETA registers to the pset
429  pset.addParameter<unsigned int>("mindetap" , mindetap );
430  pset.addParameter<unsigned int>("mindetap_halo", mindetap_halo);
431 
432  pset.addParameter< std::vector<unsigned int> >("EtaMin",etamin);
433 
434  pset.addParameter<unsigned int>("mindeta12_accp", mindeta12_accp );
435  pset.addParameter<unsigned int>("mindeta13_accp" , mindeta13_accp );
436  pset.addParameter<unsigned int>("mindeta112_accp", mindeta112_accp);
437  pset.addParameter<unsigned int>("mindeta113_accp", mindeta113_accp);
438 
439  pset.addParameter< std::vector<unsigned int> >("EtaMax",etamax);
440 
441  pset.addParameter<unsigned int>("maxdeta12_accp", maxdeta12_accp );
442  pset.addParameter<unsigned int>("maxdeta13_accp" , maxdeta13_accp );
443  pset.addParameter<unsigned int>("maxdeta112_accp", maxdeta112_accp);
444  pset.addParameter<unsigned int>("maxdeta113_accp", maxdeta113_accp);
445 
446  pset.addParameter< std::vector<unsigned int> >("EtaWindows",etawin);
447 
448  pset.addParameter<unsigned int>("maxdphi12_accp", maxdphi12_accp );
449  pset.addParameter<unsigned int>("maxdphi13_accp" , maxdphi13_accp );
450  pset.addParameter<unsigned int>("maxdphi112_accp", maxdphi112_accp);
451  pset.addParameter<unsigned int>("maxdphi113_accp", maxdphi113_accp);
452 
453  pset.addParameter<unsigned int>("mindphip", mindphip );
454  pset.addParameter<unsigned int>("mindphip_halo", mindphip_halo);
455 
456  pset.addParameter<unsigned int>("straightp", straightp);
457  pset.addParameter<unsigned int>("curvedp" , curvedp );
458  pset.addParameter<unsigned int>("mbaPhiOff", mbaPhiOff);
459  pset.addParameter<unsigned int>("mbbPhiOff", mbbPhiOff);
460 
461  pset.addParameter<unsigned int>("firmwareSP", firmwareSP);
462  pset.addParameter<unsigned int>("firmwareFA", firmwareFA);
463  pset.addParameter<unsigned int>("firmwareDD", firmwareDD);
464  pset.addParameter<unsigned int>("firmwareVM", firmwareVM);
465 
466 
467  // printout
468  LogDebug("L1MuCSCTFConfiguration") << "\nCORE CONFIGURATION AFTER READING THE DBS VALUES"
469  << "\nrun_core=" << run_core
470  << "\ntrigger_on_ME1a=" << trigger_on_ME1a
471  << "\ntrigger_on_ME1b=" << trigger_on_ME1b
472  << "\ntrigger_on_ME2=" << trigger_on_ME2
473  << "\ntrigger_on_ME3=" << trigger_on_ME3
474  << "\ntrigger_on_ME4=" << trigger_on_ME4
475  << "\ntrigger_on_MB1a=" << trigger_on_MB1a
476  << "\ntrigger_on_MB1d=" << trigger_on_MB1d
477 
478  << "\nBXAdepth=" << BXAdepth
479  << "\nuseDT=" << useDT
480  << "\nwidePhi=" << widePhi
481  << "\nPreTrigger=" << PreTrigger
482 
483  << "\nCoreLatency=" << CoreLatency
484  << "\nrescaleSinglesPhi=" << rescaleSinglesPhi
485 
486  << "\n\nVARIOUS CONFIGURATION PARAMETERS AFTER READING THE DBS VALUES"
487  << "\nAllowALCTonly=" << AllowALCTonly
488  << "\nAllowCLCTonly=" << AllowCLCTonly
489 
490  << "\nQualityEnableME1a=" << QualityEnableME1a
491  << "\nQualityEnableME1b=" << QualityEnableME1b
492  << "\nQualityEnableME1c=" << QualityEnableME1c
493  << "\nQualityEnableME1d=" << QualityEnableME1d
494  << "\nQualityEnableME1e=" << QualityEnableME1e
495  << "\nQualityEnableME1f=" << QualityEnableME1f
496  << "\nQualityEnableME2a=" << QualityEnableME2a
497  << "\nQualityEnableME2b=" << QualityEnableME2b
498  << "\nQualityEnableME2c=" << QualityEnableME2c
499  << "\nQualityEnableME3a=" << QualityEnableME3a
500  << "\nQualityEnableME3b=" << QualityEnableME3b
501  << "\nQualityEnableME3c=" << QualityEnableME3c
502  << "\nQualityEnableME4a=" << QualityEnableME4a
503  << "\nQualityEnableME4b=" << QualityEnableME4b
504  << "\nQualityEnableME4c=" << QualityEnableME4c
505 
506  << "\nkill_fiber=" << kill_fiber
507  << "\nsinglesTrackOutput=" << singlesTrackOutput
508 
509  << "\n\nDAT_ETA AFTER READING THE DBS VALUES"
510  << "\nmindetap =" << mindetap
511  << "\nmindetap_halo=" << mindetap_halo
512 
513  << "\netamin[0]=" << etamin[0]
514  << "\netamin[1]=" << etamin[1]
515  << "\netamin[2]=" << etamin[2]
516  << "\netamin[3]=" << etamin[3]
517  << "\netamin[4]=" << etamin[4]
518  << "\netamin[5]=" << etamin[5]
519  << "\netamin[6]=" << etamin[6]
520  << "\netamin[7]=" << etamin[7]
521 
522  << "\nmindeta12_accp =" << mindeta12_accp
523  << "\nmindeta13_accp =" << mindeta13_accp
524  << "\nmindeta112_accp=" << mindeta112_accp
525  << "\nmindeta113_accp=" << mindeta113_accp
526 
527  << "\netamax[0]=" << etamax[0]
528  << "\netamax[1]=" << etamax[1]
529  << "\netamax[2]=" << etamax[2]
530  << "\netamax[3]=" << etamax[3]
531  << "\netamax[4]=" << etamax[4]
532  << "\netamax[5]=" << etamax[5]
533  << "\netamax[6]=" << etamax[6]
534  << "\netamax[7]=" << etamax[7]
535 
536  << "\nmaxdeta12_accp =" << maxdeta12_accp
537  << "\nmaxdeta13_accp =" << maxdeta13_accp
538  << "\nmaxdeta112_accp=" << maxdeta112_accp
539  << "\nmaxdeta113_accp=" << maxdeta113_accp
540 
541  << "\netawin[0]=" << etawin[0]
542  << "\netawin[1]=" << etawin[1]
543  << "\netawin[2]=" << etawin[2]
544  << "\netawin[3]=" << etawin[3]
545  << "\netawin[4]=" << etawin[4]
546  << "\netawin[5]=" << etawin[5]
547  << "\netawin[6]=" << etawin[6]
548 
549  << "\nmaxdphi12_accp =" << maxdphi12_accp
550  << "\nmaxdphi13_accp =" << maxdphi13_accp
551  << "\nmaxdphi112_accp=" << maxdphi112_accp
552  << "\nmaxdphi113_accp=" << maxdphi113_accp
553 
554  << "\nmindphip =" << mindphip
555  << "\nmindphip_halo=" << mindphip_halo
556 
557  << "\nstraightp=" << straightp
558  << "\ncurvedp =" << curvedp
559  << "\nmbaPhiOff=" << mbaPhiOff
560  << "\nmbbPhiOff=" << mbbPhiOff
561 
562  << "\n\nFIRMWARE VERSIONS AFTER READING THE DBS VALUES"
563  << "\nSP: " << firmwareSP
564  << "\nFA: " << firmwareFA
565  << "\nDD: " << firmwareDD
566  << "\nVM: " << firmwareVM;
567 
568  // ---------------------------------------------------------
569 
570  return pset;
571 
572 }
573 
574 
575 
576 void L1MuCSCTFConfiguration::print(std::ostream& myStr) const {
577  myStr << "\nL1 Mu CSCTF Parameters \n" << std::endl;
578 
579  for (int iSP=0;iSP<12;iSP++) {
580  myStr << "=============================================" << std::endl;
581  myStr << "Printing out Global Tag Content for SP " << iSP+1 << std::endl;
582  myStr << registers[iSP];
583  myStr << "=============================================" << std::endl;
584  }
585 }
LogDebug
#define LogDebug(id)
Definition: MessageLogger.h:501
L1MuCSCTFConfiguration::parameters
edm::ParameterSet parameters(int sp) const
Definition: L1MuCSCTFConfiguration.cc:7
NULL
#define NULL
Definition: scimark2.h:8
AlCaHLTBitMon_QueryRunRegistry.string
string string
Definition: AlCaHLTBitMon_QueryRunRegistry.py:255
L1MuCSCTFConfiguration::print
void print(std::ostream &) const
print all the L1 CSCTF Configuration Parameters
Definition: L1MuCSCTFConfiguration.cc:576
edm::ParameterSet::addParameter
void addParameter(std::string const &name, T const &value)
Definition: ParameterSet.h:142
dbtoconf.conf
tuple conf
Definition: dbtoconf.py:185
Generated for CMSSW Reference Manual by doxygen 1.8.5