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L1GtHwValidation.cc
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1 
16 // this class header
17 #include "DQM/L1TMonitor/interface/L1GtHwValidation.h"
18 
19 // system include files
20 #include <memory>
21 #include <iostream>
22 #include <iomanip>
23 
24 // user include files
25 #include "DataFormats/L1GlobalTrigger/interface/L1GlobalTriggerReadoutSetup.h"
26 #include "DataFormats/L1GlobalTrigger/interface/L1GlobalTriggerReadoutRecord.h"
27 #include "DataFormats/L1GlobalTrigger/interface/L1GlobalTriggerEvmReadoutRecord.h"
28 
29 #include "FWCore/MessageLogger/interface/MessageLogger.h"
30 #include "FWCore/ServiceRegistry/interface/Service.h"
31 
32 #include "FWCore/Framework/interface/EventSetup.h"
33 #include "FWCore/Framework/interface/ESHandle.h"
34 #include "FWCore/Framework/interface/Run.h"
35 
36 #include "CondFormats/L1TObjects/interface/L1GtTriggerMenu.h"
37 #include "CondFormats/DataRecord/interface/L1GtTriggerMenuRcd.h"
38 
39 #include "CondFormats/L1TObjects/interface/L1GtPrescaleFactors.h"
40 #include "CondFormats/DataRecord/interface/L1GtPrescaleFactorsAlgoTrigRcd.h"
41 #include "CondFormats/DataRecord/interface/L1GtPrescaleFactorsTechTrigRcd.h"
42 
43 #include "CondFormats/L1TObjects/interface/L1GtTriggerMask.h"
44 #include "CondFormats/DataRecord/interface/L1GtTriggerMaskAlgoTrigRcd.h"
45 #include "CondFormats/DataRecord/interface/L1GtTriggerMaskTechTrigRcd.h"
46 
47 #include "TH1.h"
48 #include "TH2.h"
49 #include "TTree.h"
50 
51 // constructor(s)
52 L1GtHwValidation::L1GtHwValidation(const edm::ParameterSet& paramSet) :
53  //
54  // input tag for the L1 GT hardware DAQ record
55  m_l1GtDataDaqInputTag(paramSet.getParameter<edm::InputTag>(
56  "L1GtDataDaqInputTag")),
57  // input tag for the L1 GT hardware EVM record
58  m_l1GtDataEvmInputTag(paramSet.getParameter<edm::InputTag>(
59  "L1GtDataEvmInputTag")),
60  // input tag for the L1 GT emulator DAQ record
61  m_l1GtEmulDaqInputTag(paramSet.getParameter<edm::InputTag>(
62  "L1GtEmulDaqInputTag")),
63  // input tag for the L1 GT emulator EVM record
64  m_l1GtEmulEvmInputTag(paramSet.getParameter<edm::InputTag>(
65  "L1GtEmulEvmInputTag")),
66  // input tag for the L1 GCT hardware record
67  m_l1GctDataInputTag(paramSet.getParameter<edm::InputTag>(
68  "L1GctDataInputTag")),
69  //
70  m_dirName(paramSet.getUntrackedParameter("DirName", std::string(
71  "L1TEMU/GTexpert"))),
72  //
73  m_excludeCondCategTypeObject(paramSet.getParameter<std::vector<edm::ParameterSet> >(
74  "ExcludeCondCategTypeObject")),
75  //
76  m_excludeAlgoTrigByName(paramSet.getParameter<std::vector<std::string> >(
77  "ExcludeAlgoTrigByName")),
78  //
79  m_excludeAlgoTrigByBit(paramSet.getParameter<std::vector<int> >(
80  "ExcludeAlgoTrigByBit")),
81  //
82  // initialize counters
83  m_nrDataEventError(0),
84  m_nrEmulEventError(0),
85  // cache
86  m_l1GtMenuCacheID(0ULL), m_l1GtPfAlgoCacheID(0ULL),
87  m_l1GtPfTechCacheID(0ULL), m_l1GtTmAlgoCacheID(0ULL),
88  m_l1GtTmTechCacheID(0ULL),
89  //
90  m_dbe(0),
91  m_agree(true),
92  m_dataOnly(false),
93  m_emulOnly(false),
94  m_dataOnlyMask(false),
95  m_emulOnlyMask(false),
96  //
97  m_nrEvJob(0), m_nrEvRun(0) {
98 
99 
100  for (std::vector<edm::ParameterSet>::const_iterator
101  itExclud = m_excludeCondCategTypeObject.begin();
102  itExclud != m_excludeCondCategTypeObject.end();
103  ++itExclud) {
104 
105  if (!(itExclud->getParameter<std::string> ("ExcludedCondCategory")).empty()) {
106 
107  m_excludedCondCategory.push_back(l1GtConditionCategoryStringToEnum(
108  itExclud->getParameter<std::string>("ExcludedCondCategory")));
109 
110  } else {
111  m_excludedCondCategory.push_back(CondNull);
112  }
113 
114  if (!(itExclud->getParameter<std::string>("ExcludedCondType")).empty() ) {
115 
116  m_excludedCondType.push_back(l1GtConditionTypeStringToEnum(
117  itExclud->getParameter<std::string> ("ExcludedCondType")));
118 
119  } else {
120  m_excludedCondType.push_back(TypeNull);
121  }
122 
123  if (!(itExclud->getParameter<std::string>("ExcludedL1GtObject")).empty() ) {
124 
125  m_excludedL1GtObject.push_back(l1GtObjectStringToEnum(
126  itExclud->getParameter<std::string> ("ExcludedL1GtObject")));
127 
128  } else {
129  m_excludedL1GtObject.push_back(ObjNull);
130  }
131  }
132 
133 
134  LogDebug("L1GtHwValidation")
135  << "\nInput tag for the L1 GT DAQ hardware record: "
136  << m_l1GtDataDaqInputTag
137  << "\nInput tag for the L1 GT EVM hardware record: "
138  << m_l1GtDataEvmInputTag
139  << "\nInput tag for the L1 GT DAQ emulator records: "
140  << m_l1GtEmulDaqInputTag
141  << "\nInput tag for the L1 GT EVM emulator records: "
142  << m_l1GtEmulEvmInputTag
143  << "\nInput tag for the L1 GCT hardware record: "
144  << m_l1GctDataInputTag << std::endl;
145 
146  // FIXME print in debug mode ExcludeCondCategTypeObject, ExcludeAlgoTrigByName, etc
147 
148  m_dbe = edm::Service<DQMStore>().operator->();
149  if (m_dbe == 0) {
150  edm::LogInfo("L1GtHwValidation")
151  << "\n Unable to get DQMStore service.";
152  } else {
153 
154  if (paramSet.getUntrackedParameter<bool>("DQMStore", false)) {
155  m_dbe->setVerbose(0);
156  }
157 
158  m_dbe->setCurrentFolder(m_dirName);
159 
160  }
161 
162  //set Token(-s)
163  m_l1GtDataDaqInputToken_ = consumes<L1GlobalTriggerReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtDataDaqInputTag"));
164  m_l1GtEmulDaqInputToken_ = consumes<L1GlobalTriggerReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtEmulDaqInputTag"));
165  m_l1GtDataEvmInputToken_ = consumes<L1GlobalTriggerEvmReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtDataEvmInputTag"));
166  m_l1GtEmulEvmInputToken_ = consumes<L1GlobalTriggerEvmReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtEmulEvmInputTag"));
167 }
168 
169 // destructor
170 L1GtHwValidation::~L1GtHwValidation() {
171  // empty
172 }
173 
174 // member functions
175 
176 // method called once each job just before starting event loop
177 void L1GtHwValidation::beginJob() {}
178 
179 
180 void L1GtHwValidation::beginRun(const edm::Run& iRun,
181  const edm::EventSetup& evSetup) {
182 
183  // clean up directory
184  if (m_dbe) {
185  m_dbe->setCurrentFolder(m_dirName);
186  if (m_dbe->dirExists(m_dirName)) {
187  m_dbe->rmdir(m_dirName);
188  }
189  m_dbe->setCurrentFolder(m_dirName);
190  }
191 
192  // book histograms
193  bookHistograms();
194 
195 
196  m_nrEvRun = 0;
197 
198  // get / update the trigger menu from the EventSetup
199  // local cache & check on cacheIdentifier
200 
201  unsigned long long l1GtMenuCacheID =
202  evSetup.get<L1GtTriggerMenuRcd>().cacheIdentifier();
203 
204  if (m_l1GtMenuCacheID != l1GtMenuCacheID) {
205 
206  edm::ESHandle<L1GtTriggerMenu> l1GtMenu;
207  evSetup.get<L1GtTriggerMenuRcd>().get(l1GtMenu);
208  m_l1GtMenu = l1GtMenu.product();
209 
210  // compute the list of algorithms excluded from the computing of the agreement flag
211  m_excludedAlgoList.clear();
212  excludedAlgoList();
213 
214  m_l1GtMenuCacheID = l1GtMenuCacheID;
215 
216  }
217 
218 
219 
220  // FIXME when the menu changes, make a copy of histograms, and clear the old one
221  // otherwise the labels are wrong
222 
223  LogDebug("L1GtHwValidation") << "\nUsing L1 menu: \n "
224  << m_l1GtMenu->gtTriggerMenuImplementation() << "\n"
225  << std::endl;
226 
227  const AlgorithmMap& algorithmMap = m_l1GtMenu->gtAlgorithmMap();
228 
229  for (CItAlgo itAlgo = algorithmMap.begin(); itAlgo != algorithmMap.end(); itAlgo++) {
230 
231  const int algBitNumber = (itAlgo->second).algoBitNumber();
232 
233  std::stringstream ss;
234  std::string algBitString;
235  ss << std::uppercase << algBitNumber;
236  ss >> algBitString;
237 
238  const std::string& aName = algBitString + " " + itAlgo->first;
239  const char* algName = aName.c_str();
240 
241  for (int iRec = 0; iRec < NumberOfGtRecords; ++iRec) {
242  for (int iBxInEvent = 0; iBxInEvent < TotalBxInEvent; ++iBxInEvent) {
243 
244 
245  // convert [0, TotalBxInEvent] to [-X, +X]
246  int iIndex = iBxInEvent - ((TotalBxInEvent + 1) / 2 - 1);
247  int hIndex = (iIndex + 16) % 16;
248 
249  std::stringstream ss;
250  std::string str;
251  ss << std::uppercase << std::hex << hIndex;
252  ss >> str;
253 
254  if (iRec == 0) {
255  if (m_dbe) {
256  m_dbe->setCurrentFolder(m_dirName + "/DAQ/BxInEvent_" + str);
257  }
258 
259  } else {
260  if (m_dbe) {
261  m_dbe->setCurrentFolder(m_dirName + "/EVM/BxInEvent_" + str);
262  }
263  }
264 
265 
266  m_fdlDataAlgoDecision[iBxInEvent][iRec]->setBinLabel(
267  algBitNumber + 1, algName, 1);
268  m_fdlDataAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(
269  algBitNumber + 1, algName, 1);
270  m_fdlDataAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(
271  algBitNumber + 1, algName, 1);
272  m_fdlDataAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(
273  algBitNumber + 1, algName, 1);
274  m_fdlDataAlgoDecision_NoMatch[iBxInEvent][iRec]->setBinLabel(
275  algBitNumber + 1, algName, 1);
276 
277  m_fdlEmulAlgoDecision[iBxInEvent][iRec]->setBinLabel(
278  algBitNumber + 1, algName, 1);
279  m_fdlEmulAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(
280  algBitNumber + 1, algName, 1);
281  m_fdlEmulAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(
282  algBitNumber + 1, algName, 1);
283  m_fdlEmulAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(
284  algBitNumber + 1, algName, 1);
285  m_fdlEmulAlgoDecision_NoMatch[iBxInEvent][iRec]->setBinLabel(
286  algBitNumber + 1, algName, 1);
287 
288  m_fdlDataEmulAlgoDecision[iBxInEvent][iRec]->setBinLabel(
289  algBitNumber + 1, algName, 1);
290  m_fdlDataEmulAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(
291  algBitNumber + 1, algName, 1);
292  m_fdlDataEmulAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(
293  algBitNumber + 1, algName, 1);
294  m_fdlDataEmulAlgoDecisionUnprescaledAllowed[iBxInEvent][iRec]->setBinLabel(
295  algBitNumber + 1, algName, 1);
296  m_fdlDataEmulAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(
297  algBitNumber + 1, algName, 1);
298  }
299 
300 
301  if (iRec == 0) {
302  if (m_dbe) {
303  m_dbe->setCurrentFolder(m_dirName + "/DAQ/");
304  }
305 
306  } else {
307  if (m_dbe) {
308  m_dbe->setCurrentFolder(m_dirName + "/EVM/");
309  }
310  }
311 
312 
313  m_fdlDataAlgoDecision_Err[iRec]->setBinLabel(algBitNumber + 1,
314  algName, 1);
315 
316  m_fdlEmulAlgoDecision_Err[iRec]->setBinLabel(algBitNumber + 1,
317  algName, 1);
318 
319  m_fdlDataEmulAlgoDecision_Err[iRec]->setBinLabel(algBitNumber
320  + 1, algName, 1);
321  }
322 
323  //
324  for (std::vector<int>::const_iterator itAlgo = m_excludedAlgoList.begin(); itAlgo
325  != m_excludedAlgoList.end(); ++itAlgo) {
326 
327  if (algBitNumber == *itAlgo) {
328  m_excludedAlgorithmsAgreement->setBinLabel(algBitNumber
329  + 1, algName, 1);
330  }
331  }
332 
333 
334  }
335 
336  // get / update the prescale factors from the EventSetup
337  // local cache & check on cacheIdentifier
338 
339  unsigned long long l1GtPfAlgoCacheID = evSetup.get<
340  L1GtPrescaleFactorsAlgoTrigRcd>().cacheIdentifier();
341 
342  if (m_l1GtPfAlgoCacheID != l1GtPfAlgoCacheID) {
343 
344  edm::ESHandle<L1GtPrescaleFactors> l1GtPfAlgo;
345  evSetup.get<L1GtPrescaleFactorsAlgoTrigRcd>().get(l1GtPfAlgo);
346  m_l1GtPfAlgo = l1GtPfAlgo.product();
347 
348  m_prescaleFactorsAlgoTrig = &(m_l1GtPfAlgo->gtPrescaleFactors());
349 
350  m_l1GtPfAlgoCacheID = l1GtPfAlgoCacheID;
351 
352  }
353 
354  unsigned long long l1GtPfTechCacheID = evSetup.get<
355  L1GtPrescaleFactorsTechTrigRcd>().cacheIdentifier();
356 
357  if (m_l1GtPfTechCacheID != l1GtPfTechCacheID) {
358 
359  edm::ESHandle<L1GtPrescaleFactors> l1GtPfTech;
360  evSetup.get<L1GtPrescaleFactorsTechTrigRcd>().get(l1GtPfTech);
361  m_l1GtPfTech = l1GtPfTech.product();
362 
363  m_prescaleFactorsTechTrig = &(m_l1GtPfTech->gtPrescaleFactors());
364 
365  m_l1GtPfTechCacheID = l1GtPfTechCacheID;
366 
367  }
368 
369  // get / update the trigger mask from the EventSetup
370  // local cache & check on cacheIdentifier
371 
372  unsigned long long l1GtTmAlgoCacheID = evSetup.get<
373  L1GtTriggerMaskAlgoTrigRcd>().cacheIdentifier();
374 
375  if (m_l1GtTmAlgoCacheID != l1GtTmAlgoCacheID) {
376 
377  edm::ESHandle<L1GtTriggerMask> l1GtTmAlgo;
378  evSetup.get<L1GtTriggerMaskAlgoTrigRcd>().get(l1GtTmAlgo);
379  m_l1GtTmAlgo = l1GtTmAlgo.product();
380 
381  m_triggerMaskAlgoTrig = m_l1GtTmAlgo->gtTriggerMask();
382 
383  m_l1GtTmAlgoCacheID = l1GtTmAlgoCacheID;
384 
385  }
386 
387  unsigned long long l1GtTmTechCacheID = evSetup.get<
388  L1GtTriggerMaskTechTrigRcd>().cacheIdentifier();
389 
390  if (m_l1GtTmTechCacheID != l1GtTmTechCacheID) {
391 
392  edm::ESHandle<L1GtTriggerMask> l1GtTmTech;
393  evSetup.get<L1GtTriggerMaskTechTrigRcd>().get(l1GtTmTech);
394  m_l1GtTmTech = l1GtTmTech.product();
395 
396  m_triggerMaskTechTrig = m_l1GtTmTech->gtTriggerMask();
397 
398  m_l1GtTmTechCacheID = l1GtTmTechCacheID;
399 
400  }
401 
402 }
403 
404 //compare the GTFE board
405 void L1GtHwValidation::compareGTFE(const edm::Event& iEvent,
406  const edm::EventSetup& evSetup, const L1GtfeWord& gtfeBlockData,
407  const L1GtfeWord& gtfeBlockEmul, const int iRec) {
408 
409  std::string recString;
410  if (iRec == 0) {
411  recString = "DAQ";
412  if (m_dbe) {
413  m_dbe->setCurrentFolder(m_dirName + "/DAQ/");
414  }
415  } else {
416  recString = "EVM";
417  if (m_dbe) {
418  m_dbe->setCurrentFolder(m_dirName + "/EVM/");
419  }
420  }
421 
422  if (gtfeBlockData == gtfeBlockEmul) {
423  m_myCoutStream << "\n" << recString
424  << " Data and emulated GTFE blocks: identical.\n";
425  gtfeBlockData.print(m_myCoutStream);
426  } else {
427  m_myCoutStream << "\n" << recString
428  << " Data and emulated GTFE blocks: different.\n";
429 
430  m_myCoutStream << "\nData: GTFE block\n";
431  gtfeBlockData.print(m_myCoutStream);
432 
433  m_myCoutStream << "\nEmul: GTFE block\n";
434  gtfeBlockEmul.print(m_myCoutStream);
435 
436  }
437 
438  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
439 
440  m_myCoutStream.str("");
441  m_myCoutStream.clear();
442 
443  // get BoardId value
444  const boost::uint16_t boardIdData = gtfeBlockData.boardId();
445  const boost::uint16_t boardIdEmul = gtfeBlockEmul.boardId();
446 
447  if (boardIdData == boardIdEmul) {
448  m_myCoutStream << "\n" << recString
449  << " Data and emulated GTFE boardId identical.";
450  m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4)
451  << std::setfill('0') << boardIdData << std::setfill(' ')
452  << std::dec;
453  m_myCoutStream << "\n";
454 
455  } else {
456  m_myCoutStream << "\n" << recString
457  << " Data and emulated GTFE boardId different.";
458  m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x"
459  << std::setw(4) << std::setfill('0') << boardIdData
460  << std::setfill(' ') << std::dec;
461  m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x"
462  << std::setw(4) << std::setfill('0') << boardIdEmul
463  << std::setfill(' ') << std::dec;
464  m_myCoutStream << "\n";
465  m_gtfeDataEmul[iRec]->Fill(0);
466 
467  }
468 
470  const boost::uint16_t recordLength1Data = gtfeBlockData.recordLength1();
471  const boost::uint16_t recordLength1Emul = gtfeBlockEmul.recordLength1();
472 
473  if (recordLength1Data == recordLength1Emul) {
474  m_myCoutStream << "\n" << recString
475  << " Data and emulated GTFE recordLength for alternative 1 identical.";
476  m_myCoutStream << "\n recordLength1() = " << recordLength1Data;
477  m_myCoutStream << "\n";
478 
479  } else {
480  m_myCoutStream << "\n" << recString
481  << " Data and emulated GTFE recordLength for alternative 1 different.";
482  m_myCoutStream << "\n Data: recordLength1() = " << recordLength1Data;
483  m_myCoutStream << "\n Emul: recordLength1() = " << recordLength1Emul;
484  m_myCoutStream << "\n";
485  m_gtfeDataEmul[iRec]->Fill(1);
486 
487  }
488 
490  const boost::uint16_t recordLengthData = gtfeBlockData.recordLength();
491  const boost::uint16_t recordLengthEmul = gtfeBlockEmul.recordLength();
492 
493  if (recordLengthData == recordLengthEmul) {
494  m_myCoutStream << "\n" << recString
495  << " Data and emulated GTFE recordLength for alternative 0 identical.";
496  m_myCoutStream << "\n recordLength() = " << recordLengthData;
497  m_myCoutStream << "\n";
498 
499  } else {
500  m_myCoutStream << "\n" << recString
501  << " Data and emulated GTFE recordLength for alternative 1 different.";
502  m_myCoutStream << "\n Data: recordLength() = " << recordLengthData;
503  m_myCoutStream << "\n Emul: recordLength() = " << recordLengthEmul;
504  m_myCoutStream << "\n";
505  m_gtfeDataEmul[iRec]->Fill(2);
506 
507  }
508 
510  const boost::uint16_t bxNrData = gtfeBlockData.bxNr();
511  const boost::uint16_t bxNrEmul = gtfeBlockEmul.bxNr();
512 
513  if (bxNrData == bxNrEmul) {
514  m_myCoutStream << "\n" << recString
515  << " Data and emulated GTFE bxNr identical.";
516  m_myCoutStream << "\n bxNr() = " << bxNrData;
517  m_myCoutStream << "\n";
518 
519  } else {
520  m_myCoutStream << "\n" << recString
521  << " Data and emulated GTFE bxNr different.";
522  m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
523  m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
524  m_myCoutStream << "\n";
525  m_gtfeDataEmul[iRec]->Fill(3);
526 
527  }
528 
530  const boost::uint32_t setupVersionData = gtfeBlockData.setupVersion();
531  const boost::uint32_t setupVersionEmul = gtfeBlockEmul.setupVersion();
532 
533  if (setupVersionData == setupVersionEmul) {
534  m_myCoutStream << "\n" << recString
535  << " Data and emulated GTFE setupVersion identical.";
536  m_myCoutStream << "\n setupVersion() = " << setupVersionData;
537  m_myCoutStream << "\n";
538 
539  } else {
540  m_myCoutStream << "\n" << recString
541  << " Data and emulated GTFE setupVersion different.";
542  m_myCoutStream << "\n Data: setupVersion() = " << setupVersionData;
543  m_myCoutStream << "\n Emul: setupVersion() = " << setupVersionEmul;
544  m_myCoutStream << "\n";
545  m_gtfeDataEmul[iRec]->Fill(4);
546 
547  }
548 
550  const boost::uint16_t activeBoardsData = gtfeBlockData.activeBoards();
551  const boost::uint16_t activeBoardsEmul = gtfeBlockEmul.activeBoards();
552 
553  if (activeBoardsData == activeBoardsEmul) {
554  m_myCoutStream << "\n" << recString
555  << " Data and emulated GTFE activeBoards identical.";
556  m_myCoutStream << "\n activeBoards() = " << std::hex << "0x"
557  << std::setw(4) << std::setfill('0') << activeBoardsData
558  << std::setfill(' ') << std::dec;
559  m_myCoutStream << "\n";
560 
561  } else {
562  m_myCoutStream << "\n" << recString
563  << " Data and emulated GTFE activeBoards different.";
564  m_myCoutStream << "\n Data: activeBoards() = " << std::hex << "0x"
565  << std::setw(4) << std::setfill('0') << activeBoardsData
566  << std::setfill(' ') << std::dec;
567  m_myCoutStream << "\n Emul: activeBoards() = " << std::hex << "0x"
568  << std::setw(4) << std::setfill('0') << activeBoardsEmul
569  << std::setfill(' ') << std::dec;
570  m_myCoutStream << "\n";
571  m_gtfeDataEmul[iRec]->Fill(5);
572 
573  }
578  const boost::uint16_t altNrBxBoardData = gtfeBlockData.altNrBxBoard();
579  const boost::uint16_t altNrBxBoardEmul = gtfeBlockEmul.altNrBxBoard();
580 
581  if (altNrBxBoardData == altNrBxBoardEmul) {
582  m_myCoutStream << "\n" << recString
583  << " Data and emulated GTFE altNrBxBoard identical.";
584  m_myCoutStream << "\n altNrBxBoard() = " << altNrBxBoardData;
585  m_myCoutStream << "\n";
586 
587  } else {
588  m_myCoutStream << "\n" << recString
589  << " Data and emulated GTFE altNrBxBoard different.";
590  m_myCoutStream << "\n Data: altNrBxBoard() = " << altNrBxBoardData;
591  m_myCoutStream << "\n Emul: altNrBxBoard() = " << altNrBxBoardEmul;
592  m_myCoutStream << "\n";
593  m_gtfeDataEmul[iRec]->Fill(6);
594 
595  }
596 
598  const boost::uint32_t totalTriggerNrData = gtfeBlockData.totalTriggerNr();
599  const boost::uint32_t totalTriggerNrEmul = gtfeBlockEmul.totalTriggerNr();
600 
601  if (totalTriggerNrData == totalTriggerNrEmul) {
602  m_myCoutStream << "\n" << recString
603  << " Data and emulated GTFE totalTriggerNr identical.";
604  m_myCoutStream << "\n totalTriggerNr() = " << totalTriggerNrData;
605  m_myCoutStream << "\n";
606 
607  } else {
608  m_myCoutStream << "\n" << recString
609  << " Data and emulated GTFE totalTriggerNr different.";
610  m_myCoutStream << "\n Data: totalTriggerNr() = " << totalTriggerNrData;
611  m_myCoutStream << "\n Emul: totalTriggerNr() = " << totalTriggerNrEmul;
612  m_myCoutStream << "\n";
613  m_gtfeDataEmul[iRec]->Fill(7);
614 
615  }
616 
617  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
618  m_myCoutStream.str("");
619  m_myCoutStream.clear();
620 
621 }
622 
623 //compare the FDL board
624 void L1GtHwValidation::compareFDL(const edm::Event& iEvent,
625  const edm::EventSetup& evSetup, const L1GtFdlWord& fdlBlockData,
626  const L1GtFdlWord& fdlBlockEmul, const int iRec) {
627 
628  // index of physics partition
629  int PhysicsPartition = 0;
630 
631  //
632  std::string recString;
633  if (iRec == 0) {
634  recString = "DAQ";
635  if (m_dbe) {
636  m_dbe->setCurrentFolder(m_dirName + "/DAQ/");
637  }
638  } else {
639  recString = "EVM";
640  if (m_dbe) {
641  m_dbe->setCurrentFolder(m_dirName + "/EVM/");
642  }
643  }
644 
645  if (fdlBlockData == fdlBlockEmul) {
646  m_myCoutStream << "\n" << recString
647  << " Data and emulated FDL blocks: identical.\n";
648  fdlBlockData.print(m_myCoutStream);
649 
650  } else {
651  m_myCoutStream << "\n" << recString
652  << " Data and emulated FDL blocks: different.\n";
653 
654  m_myCoutStream << "\nData: FDL block\n";
655  fdlBlockData.print(m_myCoutStream);
656 
657  m_myCoutStream << "\nEmul: FDL block\n";
658  fdlBlockEmul.print(m_myCoutStream);
659 
660  }
661 
662  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
663 
664  m_myCoutStream.str("");
665  m_myCoutStream.clear();
666 
667  // get bunch cross in the GT event record -
668  // move it first as histograms are BxInEvent dependent
669  const int bxInEventData = fdlBlockData.bxInEvent();
670  const int bxInEventEmul = fdlBlockEmul.bxInEvent();
671 
672  bool matchBxInEvent = false;
673 
674  if (bxInEventData == bxInEventEmul) {
675  m_myCoutStream << "\n" << recString
676  << " Data and emulated FDL bxInEvent identical.";
677  m_myCoutStream << "\n bxInEvent() = " << bxInEventData;
678  m_myCoutStream << "\n";
679  matchBxInEvent = true;
680 
681  } else {
682  m_myCoutStream << "\n" << recString
683  << " Data and emulated FDL bxInEvent different.";
684  m_myCoutStream << "\n Data: bxInEvent() = " << bxInEventData;
685  m_myCoutStream << "\n Emul: bxInEvent() = " << bxInEventEmul;
686  m_myCoutStream << "\n";
687 
688  m_fdlDataEmul_Err[iRec]->Fill(1);
689 
690  if (iRec == 0) {
691  m_agree = false;
692 
693  m_myCoutStream << "\nDisagreement data versus emulator: "
694  << "\n Data and emulated FDL bxInEvent different \n";
695  }
696 
697  }
698 
699  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
700  m_myCoutStream.str("");
701  m_myCoutStream.clear();
702 
703  // symmetrize
704  bool validBxInEvent = false;
705  int histIndex = bxInEventData + (TotalBxInEvent + 1) / 2 - 1;
706  LogDebug("L1GtHwValidation") << "\n Convert bxInEvent = " << bxInEventData
707  << " to histIndex = " << histIndex << std::endl;
708  if ((histIndex <= TotalBxInEvent) && (histIndex >= 0)) {
709  validBxInEvent = true;
710  }
711 
712  // loop over algorithms and increase the corresponding counters
713 
714  // get BoardId value
715  const boost::uint16_t boardIdData = fdlBlockData.boardId();
716  const boost::uint16_t boardIdEmul = fdlBlockEmul.boardId();
717 
718  if (boardIdData == boardIdEmul) {
719  m_myCoutStream << "\n" << recString
720  << " Data and emulated FDL boardId identical.";
721  m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4)
722  << std::setfill('0') << boardIdData << std::setfill(' ')
723  << std::dec;
724  m_myCoutStream << "\n";
725 
726  } else {
727  m_myCoutStream << "\n" << recString
728  << " Data and emulated FDL boardId different.";
729  m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x"
730  << std::setw(4) << std::setfill('0') << boardIdData
731  << std::setfill(' ') << std::dec;
732  m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x"
733  << std::setw(4) << std::setfill('0') << boardIdEmul
734  << std::setfill(' ') << std::dec;
735  m_myCoutStream << "\n";
736 
737  if (matchBxInEvent && validBxInEvent) {
738  m_fdlDataEmul[histIndex][iRec]->Fill(0);
739  } else {
740  m_fdlDataEmul_Err[iRec]->Fill(0);
741  }
742 
743  }
744 
745  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
746  m_myCoutStream.str("");
747  m_myCoutStream.clear();
748 
749  // get BxNr - bunch cross number of the actual bx
750  const boost::uint16_t bxNrData = fdlBlockData.bxNr();
751  const boost::uint16_t bxNrEmul = fdlBlockEmul.bxNr();
752 
753  if (bxNrData == bxNrEmul) {
754  m_myCoutStream << "\n" << recString
755  << " Data and emulated FDL bxNr identical.";
756  m_myCoutStream << "\n bxNr() = " << bxNrData;
757  m_myCoutStream << "\n";
758 
759  } else {
760  m_myCoutStream << "\n" << recString
761  << " Data and emulated FDL bxNr different.";
762  m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
763  m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
764  m_myCoutStream << "\n";
765 
766  if (matchBxInEvent && validBxInEvent) {
767  m_fdlDataEmul[histIndex][iRec]->Fill(2);
768  } else {
769  m_fdlDataEmul_Err[iRec]->Fill(2);
770  }
771  }
772 
773  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
774  m_myCoutStream.str("");
775  m_myCoutStream.clear();
776 
777  // get event number since last L1 reset generated in FDL
778  const boost::uint32_t eventNrData = fdlBlockData.eventNr();
779  const boost::uint32_t eventNrEmul = fdlBlockEmul.eventNr();
780 
781  if (eventNrData == eventNrEmul) {
782  m_myCoutStream << "\n" << recString
783  << " Data and emulated FDL eventNr identical.";
784  m_myCoutStream << "\n eventNr() = " << eventNrData;
785  m_myCoutStream << "\n";
786 
787  } else {
788  m_myCoutStream << "\n" << recString
789  << " Data and emulated FDL eventNr different.";
790  m_myCoutStream << "\n Data: eventNr() = " << eventNrData;
791  m_myCoutStream << "\n Emul: eventNr() = " << eventNrEmul;
792  m_myCoutStream << "\n";
793 
794  if (matchBxInEvent && validBxInEvent) {
795  m_fdlDataEmul[histIndex][iRec]->Fill(3);
796  } else {
797  m_fdlDataEmul_Err[iRec]->Fill(3);
798  }
799 
800  }
801 
802  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
803  m_myCoutStream.str("");
804  m_myCoutStream.clear();
805 
806  // get technical trigger bits
807  const TechnicalTriggerWord& gtTechnicalTriggerWordData =
808  fdlBlockData.gtTechnicalTriggerWord();
809  const TechnicalTriggerWord& gtTechnicalTriggerWordEmul =
810  fdlBlockEmul.gtTechnicalTriggerWord();
811 
812  int nTechBits = gtTechnicalTriggerWordData.size();
813 
814  TechnicalTriggerWord gtTechnicalTriggerWordDataMask(nTechBits);
815  TechnicalTriggerWord gtTechnicalTriggerWordEmulMask(nTechBits);
816 
817  unsigned int bitValue = 0;
818 
819  if (matchBxInEvent && validBxInEvent) {
820  for (int iBit = 0; iBit < nTechBits; ++iBit) {
821 
822  unsigned int triggerMask = (m_triggerMaskTechTrig.at(iBit)) & (1
823  << PhysicsPartition);
824 
825  if (gtTechnicalTriggerWordData[iBit]) {
826  m_fdlDataTechDecision[histIndex][iRec]->Fill(iBit);
827 
828  bitValue = (triggerMask) ? 0 : 1;
829  gtTechnicalTriggerWordDataMask[iBit] = bitValue;
830  if (bitValue) {
831  m_fdlDataTechDecisionMask[histIndex][iRec]->Fill(iBit);
832  }
833  }
834 
835  if (gtTechnicalTriggerWordEmul.at(iBit)) {
836  m_fdlEmulTechDecision[histIndex][iRec]->Fill(iBit);
837 
838  bitValue = (triggerMask) ? 0 : 1;
839  gtTechnicalTriggerWordEmulMask[iBit] = bitValue;
840  if (bitValue) {
841  m_fdlEmulTechDecisionMask[histIndex][iRec]->Fill(iBit);
842  }
843  }
844  }
845  } else {
846  for (int iBit = 0; iBit < nTechBits; ++iBit) {
847 
848  if (gtTechnicalTriggerWordData[iBit]) {
849  m_fdlDataTechDecision_Err[iRec]->Fill(iBit);
850  }
851 
852  if (gtTechnicalTriggerWordEmul.at(iBit)) {
853  m_fdlEmulTechDecision_Err[iRec]->Fill(iBit);
854  }
855  }
856  }
857 
858  if (gtTechnicalTriggerWordData == gtTechnicalTriggerWordEmul) {
859  m_myCoutStream << "\n" << recString
860  << " Data and emulated FDL gtTechnicalTriggerWord identical.\n";
861  fdlBlockData.printGtTechnicalTriggerWord(m_myCoutStream);
862  m_myCoutStream << "\n";
863 
864  } else {
865  m_myCoutStream << "\n" << recString
866  << " Data and emulated FDL gtTechnicalTriggerWord different.";
867  m_myCoutStream << "\n Data: ";
868  fdlBlockData.printGtTechnicalTriggerWord(m_myCoutStream);
869  m_myCoutStream << "\n Emul: ";
870  fdlBlockEmul.printGtTechnicalTriggerWord(m_myCoutStream);
871  m_myCoutStream << "\n";
872 
873  if (matchBxInEvent && validBxInEvent) {
874  m_fdlDataEmul[histIndex][iRec]->Fill(4);
875  } else {
876  m_fdlDataEmul_Err[iRec]->Fill(4);
877  }
878 
879  if (matchBxInEvent && validBxInEvent) {
880  for (int iBit = 0; iBit < nTechBits; ++iBit) {
881  if (gtTechnicalTriggerWordData[iBit]
882  != gtTechnicalTriggerWordEmul.at(iBit)) {
883  m_fdlDataEmulTechDecision[histIndex][iRec]->Fill(iBit);
884  }
885  }
886  } else {
887  for (int iBit = 0; iBit < nTechBits; ++iBit) {
888  if (gtTechnicalTriggerWordData[iBit]
889  != gtTechnicalTriggerWordEmul.at(iBit)) {
890  m_fdlDataEmulTechDecision_Err[iRec]->Fill(iBit);
891  }
892  }
893  }
894  }
895 
896  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
897  m_myCoutStream.str("");
898  m_myCoutStream.clear();
899 
900  if (gtTechnicalTriggerWordDataMask == gtTechnicalTriggerWordEmulMask) {
901  m_myCoutStream << "\n" << recString
902  << " Data and emulated FDL gtTechnicalTriggerWord after mask identical.\n";
903  m_myCoutStream << "\n";
904 
905  } else {
906  m_myCoutStream << "\n" << recString
907  << " Data and emulated FDL gtTechnicalTriggerWord after mask different.";
908  m_myCoutStream << "\n Data: ";
909  m_myCoutStream << "\n Emul: ";
910  m_myCoutStream << "\n";
911 
912  if (matchBxInEvent && validBxInEvent) {
913  m_fdlDataEmul[histIndex][iRec]->Fill(5);
914  } else {
915  m_fdlDataEmul_Err[iRec]->Fill(5);
916  }
917 
918  if (matchBxInEvent && validBxInEvent) {
919  for (int iBit = 0; iBit < nTechBits; ++iBit) {
920  if (gtTechnicalTriggerWordData[iBit]
921  != gtTechnicalTriggerWordEmul.at(iBit)) {
922  m_fdlDataEmulTechDecisionMask[histIndex][iRec]->Fill(iBit);
923  }
924  }
925  }
926  }
927 
928  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
929  m_myCoutStream.str("");
930  m_myCoutStream.clear();
931 
932  // get algorithms bits (decision word)
933  const DecisionWord& gtDecisionWordData = fdlBlockData.gtDecisionWord();
934  const DecisionWord& gtDecisionWordEmul = fdlBlockEmul.gtDecisionWord();
935 
936  int nAlgoBits = gtDecisionWordData.size();
937 
938  DecisionWord gtDecisionWordDataMask(nAlgoBits);
939  DecisionWord gtDecisionWordEmulMask(nAlgoBits);
940 
941  // get the index of the prescale factor set from data
942  int iPfSet = fdlBlockData.gtPrescaleFactorIndexAlgo();
943 
944  // check that the prescale factor is not out of range for the prescale factor
945  // record retrieved from event setup
946  size_t pfSetsSize = (*m_prescaleFactorsAlgoTrig).size();
947 
948  if (iPfSet < 0) {
949 
950  LogDebug("L1GtHwValidation")
951  << "\nError: index of prescale factor set retrieved from the data \n"
952  << "less than zero."
953  << "\n Value of index retrieved from data = " << iPfSet
954  << std::endl;
955 
956  // FIXME add a histogram to be used for a quality test
957 
958  return;
959 
960  } else if (iPfSet >= (static_cast<int>(pfSetsSize))) {
961 
962  LogDebug("L1GtHwValidation")
963  << "\nError: index of prescale factor set retrieved from the data \n"
964  << "greater than the size of the vector of prescale factor sets."
965  << "\n Value of index retrieved from data = " << iPfSet
966  << "\n Vector size = " << pfSetsSize << std::endl;
967 
968  // FIXME add a histogram to be used for a quality test
969 
970  return;
971 
972  }
973 
974  const std::vector<int>& prescaleFactorsAlgoTrig =
975  (*m_prescaleFactorsAlgoTrig).at(iPfSet);
976 
977 
978  if (matchBxInEvent && validBxInEvent) {
979 
980  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
981 
982  unsigned int triggerMask = (m_triggerMaskAlgoTrig.at(iBit)) & (1
983  << PhysicsPartition);
984 
985  int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
986 
987  LogTrace("L1GtHwValidation") << "Bit " << iBit
988  << ": prescale factor = " << prescaleFactor
989  << " trigger mask = " << triggerMask << std::endl;
990 
991  if (gtDecisionWordData[iBit]) {
992  m_fdlDataAlgoDecision[histIndex][iRec]->Fill(iBit);
993 
994  if (prescaleFactor == 1) {
995  m_fdlDataAlgoDecisionUnprescaled[histIndex][iRec]->Fill(
996  iBit);
997  } else {
998  m_fdlDataAlgoDecisionPrescaled[histIndex][iRec]->Fill(iBit);
999  }
1000 
1001  bitValue = (triggerMask) ? 0 : 1;
1002  gtDecisionWordDataMask[iBit] = bitValue;
1003  if (bitValue) {
1004  m_fdlDataAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
1005  }
1006  }
1007 
1008  if (gtDecisionWordEmul.at(iBit)) {
1009  m_fdlEmulAlgoDecision[histIndex][iRec]->Fill(iBit);
1010 
1011  bitValue = (triggerMask) ? 0 : 1;
1012  gtDecisionWordEmulMask[iBit] = bitValue;
1013  if (bitValue) {
1014  m_fdlEmulAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
1015  }
1016  }
1017  }
1018  } else {
1019  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1020  if (gtDecisionWordData[iBit]) {
1021  m_fdlDataAlgoDecision_Err[iRec]->Fill(iBit);
1022  }
1023  }
1024 
1025  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1026  if (gtDecisionWordEmul.at(iBit)) {
1027  m_fdlEmulAlgoDecision_Err[iRec]->Fill(iBit);
1028  }
1029  }
1030 
1031  if (iRec == 0) {
1032  m_agree = false;
1033 
1034  m_myCoutStream << "\nDisagreement data versus emulator: "
1035  << "\n matchBxInEvent && validBxInEvent false \n";
1036  }
1037 
1038  }
1039 
1040  if (gtDecisionWordData == gtDecisionWordEmul) {
1041  m_myCoutStream << "\n" << recString
1042  << " Data and emulated FDL gtDecisionWord identical.";
1043  fdlBlockData.printGtDecisionWord(m_myCoutStream);
1044  m_myCoutStream << "\n";
1045 
1046  } else {
1047  m_myCoutStream << "\n" << recString
1048  << " Data and emulated FDL gtDecisionWord different.";
1049  m_myCoutStream << "\n Data: ";
1050  fdlBlockData.printGtDecisionWord(m_myCoutStream);
1051  m_myCoutStream << "\n Emul: ";
1052  fdlBlockEmul.printGtDecisionWord(m_myCoutStream);
1053  m_myCoutStream << "\n";
1054 
1055  if (matchBxInEvent && validBxInEvent) {
1056  m_fdlDataEmul[histIndex][iRec]->Fill(6);
1057  } else {
1058  m_fdlDataEmul_Err[iRec]->Fill(6);
1059  }
1060 
1061  if (matchBxInEvent && validBxInEvent) {
1062  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1063 
1064  int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
1065 
1066  if (gtDecisionWordData[iBit] != gtDecisionWordEmul.at(iBit)) {
1067 
1068  m_fdlDataEmulAlgoDecision[histIndex][iRec]->Fill(iBit);
1069 
1070  // for excluded algorithms, fill mismatch for BxInEvent = 0 and DAQ record only
1071  if (excludedAlgo(iBit) && (bxInEventData == 0) && (iRec
1072  == 0)) {
1073  m_excludedAlgorithmsAgreement->Fill(iBit);
1074  }
1075 
1076  if (prescaleFactor == 1) {
1077  m_fdlDataEmulAlgoDecisionUnprescaled[histIndex][iRec]->Fill(
1078  iBit);
1079 
1080  // fill a histogram for allowed algorithm triggers only
1081  if (!excludedAlgo(iBit)) {
1082  m_fdlDataEmulAlgoDecisionUnprescaledAllowed[histIndex][iRec]->Fill(
1083  iBit);
1084  }
1085 
1086  } else {
1087  m_fdlDataEmulAlgoDecisionPrescaled[histIndex][iRec]->Fill(
1088  iBit);
1089  }
1090 
1091  if (gtDecisionWordData[iBit]) {
1092  m_fdlDataAlgoDecision_NoMatch[histIndex][iRec]->Fill(
1093  iBit);
1094 
1095  if (prescaleFactor == 1) {
1096  m_fdlDataAlgoDecisionUnprescaled_NoMatch[histIndex][iRec]->Fill(
1097  iBit);
1098 
1099  // compare for agreement only unprescaled algorithms and algorithms which
1100  // are not excluded from comparison
1101  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1102  && (iRec == 0)) {
1103  m_agree = false;
1104  m_dataOnly = true;
1105 
1106  m_myCoutStream
1107  << "\nDisagreement data versus emulator: "
1108  << "result before mask for algorithm with bit number "
1109  << iBit
1110  << "\n Data: true, emulator: false \n";
1111  }
1112 
1113  } else {
1114  m_fdlDataAlgoDecisionPrescaled_NoMatch[histIndex][iRec]->Fill(
1115  iBit);
1116  }
1117 
1118  } else {
1119  m_fdlEmulAlgoDecision_NoMatch[histIndex][iRec]->Fill(
1120  iBit);
1121 
1122  if (prescaleFactor == 1) {
1123  m_fdlEmulAlgoDecisionUnprescaled_NoMatch[histIndex][iRec]->Fill(
1124  iBit);
1125 
1126  // compare for agreement only unprescaled algorithms and algorithms which
1127  // are not excluded from comparison
1128  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1129  && (iRec == 0)) {
1130  m_agree = false;
1131  m_emulOnly = true;
1132 
1133  m_myCoutStream
1134  << "\nDisagreement data versus emulator: "
1135  << "result before mask for algorithm with bit number "
1136  << iBit
1137  << "\n Data: false, emulator: true \n";
1138  }
1139 
1140  } else {
1141  m_fdlEmulAlgoDecisionPrescaled_NoMatch[histIndex][iRec]->Fill(
1142  iBit);
1143  }
1144  }
1145  }
1146  }
1147  } else {
1148  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1149  if (gtDecisionWordData[iBit] != gtDecisionWordEmul.at(iBit)) {
1150  m_fdlDataEmulAlgoDecision_Err[iRec]->Fill(iBit);
1151  }
1152  }
1153 
1154  if (iRec == 0) {
1155  m_agree = false;
1156 
1157  m_myCoutStream << "\nDisagreement data versus emulator: "
1158  << "\n matchBxInEvent && validBxInEvent false \n";
1159  }
1160  }
1161 
1162  }
1163 
1164  if (gtDecisionWordDataMask == gtDecisionWordEmulMask) {
1165  m_myCoutStream << "\n" << recString
1166  << " Data and emulated FDL gtDecisionWord after mask identical.";
1167  m_myCoutStream << "\n";
1168 
1169  } else {
1170  m_myCoutStream << "\n" << recString
1171  << " Data and emulated FDL gtDecisionWord after mask different.";
1172  m_myCoutStream << "\n Data: ";
1173  m_myCoutStream << "\n Emul: ";
1174  m_myCoutStream << "\n";
1175 
1176  if (matchBxInEvent && validBxInEvent) {
1177  m_fdlDataEmul[histIndex][iRec]->Fill(7);
1178  } else {
1179  m_fdlDataEmul_Err[iRec]->Fill(7);
1180  }
1181 
1182  if (matchBxInEvent && validBxInEvent) {
1183  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1184  if (gtDecisionWordDataMask[iBit] != gtDecisionWordEmulMask.at(
1185  iBit)) {
1186  m_fdlDataEmulAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
1187 
1188 
1189  int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
1190 
1191  if (gtDecisionWordDataMask[iBit]) {
1192  m_fdlDataAlgoDecisionMask_NoMatch[histIndex][iRec]->Fill(
1193  iBit);
1194 
1195  if (prescaleFactor == 1) {
1196  m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[histIndex][iRec]->Fill(
1197  iBit);
1198 
1199  // compare for agreement only unprescaled algorithms and algorithms which
1200  // are not excluded from comparison
1201  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1202  && (iRec == 0)) {
1203  m_agree = false;
1204  m_dataOnlyMask = true;
1205 
1206  m_myCoutStream
1207  << "\nDisagreement data versus emulator: "
1208  << "result after mask for algorithm with bit number "
1209  << iBit
1210  << " different in data versus emulator "
1211  << "\n Data: true, emulator: false \n";
1212  }
1213 
1214  } else {
1215  m_fdlDataAlgoDecisionPrescaledMask_NoMatch[histIndex][iRec]->Fill(
1216  iBit);
1217  }
1218 
1219  } else {
1220  m_fdlEmulAlgoDecisionMask_NoMatch[histIndex][iRec]->Fill(
1221  iBit);
1222 
1223  if (prescaleFactor == 1) {
1224  m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[histIndex][iRec]->Fill(
1225  iBit);
1226 
1227  // compare for agreement only unprescaled algorithms and algorithms which
1228  // are not excluded from comparison
1229  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1230  && (iRec == 0)) {
1231  m_agree = false;
1232  m_emulOnlyMask = true;
1233 
1234  m_myCoutStream
1235  << "\nDisagreement data versus emulator: "
1236  << "result after mask for algorithm with bit number "
1237  << iBit
1238  << " different in data versus emulator "
1239  << "\n Data: false, emulator: true \n";
1240  }
1241 
1242  } else {
1243  m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[histIndex][iRec]->Fill(
1244  iBit);
1245  }
1246  }
1247 
1248 
1249  }
1250  }
1251  }
1252 
1253  }
1254 
1255  // get extended algorithms bits (extended decision word)
1256  const DecisionWordExtended gtDecisionWordExtendedData =
1257  fdlBlockData.gtDecisionWordExtended();
1258  const DecisionWordExtended gtDecisionWordExtendedEmul =
1259  fdlBlockEmul.gtDecisionWordExtended();
1260 
1261  if (gtDecisionWordExtendedData == gtDecisionWordExtendedEmul) {
1262  m_myCoutStream << "\n" << recString
1263  << " Data and emulated FDL gtDecisionWordExtended identical.\n";
1264  fdlBlockData.printGtDecisionWordExtended(m_myCoutStream);
1265  m_myCoutStream << "\n";
1266 
1267  } else {
1268  m_myCoutStream << "\n" << recString
1269  << " Data and emulated FDL gtDecisionWordExtended different.\n";
1270  m_myCoutStream << "\n Data: ";
1271  fdlBlockData.printGtDecisionWordExtended(m_myCoutStream);
1272  m_myCoutStream << "\n Emul: ";
1273  fdlBlockEmul.printGtDecisionWordExtended(m_myCoutStream);
1274  m_myCoutStream << "\n";
1275 
1276  if (matchBxInEvent && validBxInEvent) {
1277  m_fdlDataEmul[histIndex][iRec]->Fill(8);
1278  } else {
1279  m_fdlDataEmul_Err[iRec]->Fill(8);
1280  }
1281 
1282  }
1283 
1284  // get NoAlgo
1285  const boost::uint16_t noAlgoData = fdlBlockData.noAlgo();
1286  const boost::uint16_t noAlgoEmul = fdlBlockEmul.noAlgo();
1287 
1288  if (noAlgoData == noAlgoEmul) {
1289  m_myCoutStream << "\n" << recString
1290  << " Data and emulated FDL noAlgo identical.";
1291  m_myCoutStream << "\n noAlgo() = " << noAlgoData;
1292  m_myCoutStream << "\n";
1293 
1294  } else {
1295  m_myCoutStream << "\n" << recString
1296  << " Data and emulated FDL noAlgo different.";
1297  m_myCoutStream << "\n Data: noAlgo() = " << noAlgoData;
1298  m_myCoutStream << "\n Emul: noAlgo() = " << noAlgoEmul;
1299  m_myCoutStream << "\n";
1300 
1301  if (matchBxInEvent && validBxInEvent) {
1302  m_fdlDataEmul[histIndex][iRec]->Fill(9);
1303  } else {
1304  m_fdlDataEmul_Err[iRec]->Fill(9);
1305  }
1306 
1307  }
1308 
1309  // get "Final OR" bits
1310  const boost::uint16_t finalORData = fdlBlockData.finalOR();
1311  const boost::uint16_t finalOREmul = fdlBlockEmul.finalOR();
1312 
1313  if (finalORData == finalOREmul) {
1314  m_myCoutStream << "\n" << recString
1315  << " Data and emulated FDL finalOR identical.";
1316  m_myCoutStream << "\n finalOR() = " << std::hex << "0x" << std::setw(2)
1317  << std::setfill('0') << finalORData << std::setfill(' ')
1318  << std::dec;
1319  m_myCoutStream << "\n";
1320 
1321  } else {
1322  m_myCoutStream << "\n" << recString
1323  << " Data and emulated FDL finalOR different.";
1324  m_myCoutStream << "\n Data: finalOR() = " << std::hex << "0x"
1325  << std::setw(2) << std::setfill('0') << finalORData
1326  << std::setfill(' ') << std::dec;
1327  m_myCoutStream << "\n Emul: finalOR() = " << std::hex << "0x"
1328  << std::setw(2) << std::setfill('0') << finalOREmul
1329  << std::setfill(' ') << std::dec;
1330  m_myCoutStream << "\n";
1331 
1332  if (matchBxInEvent && validBxInEvent) {
1333  m_fdlDataEmul[histIndex][iRec]->Fill(10);
1334  } else {
1335  m_fdlDataEmul_Err[iRec]->Fill(10);
1336  }
1337 
1338  }
1339 
1340  // get "Final OR" for physics partition
1341  const int finalORPhysData = finalORData & (1 << PhysicsPartition);
1342  const int finalORPhysEmul = finalOREmul & (1 << PhysicsPartition);
1343 
1344  if (finalORPhysData == finalORPhysEmul) {
1345  m_myCoutStream << "\n" << recString
1346  << " Data and emulated FDL finalOR for the physics partition identical.";
1347  m_myCoutStream << "\n finalOR() = " << finalORPhysData;
1348  m_myCoutStream << "\n";
1349 
1350  } else {
1351  m_myCoutStream << "\n" << recString
1352  << " Data and emulated FDL finalOR for the physics partition different.";
1353  m_myCoutStream << "\n Data: finalOR() = " << finalORPhysData;
1354  m_myCoutStream << "\n Emul: finalOR() = " << finalORPhysEmul;
1355  m_myCoutStream << "\n";
1356 
1357  if (matchBxInEvent && validBxInEvent) {
1358  m_fdlDataEmul[histIndex][iRec]->Fill(11);
1359  } else {
1360  m_fdlDataEmul_Err[iRec]->Fill(11);
1361  }
1362 
1363  }
1364 
1365  // get local bunch cross number of the actual bx
1366  const boost::uint16_t localBxNrData = fdlBlockData.localBxNr();
1367  const boost::uint16_t localBxNrEmul = fdlBlockEmul.localBxNr();
1368 
1369  if (localBxNrData == localBxNrEmul) {
1370  m_myCoutStream << "\n" << recString
1371  << " Data and emulated FDL localBxNr identical.";
1372  m_myCoutStream << "\n localBxNr() = " << localBxNrData;
1373  m_myCoutStream << "\n";
1374 
1375  } else {
1376  m_myCoutStream << "\n" << recString
1377  << " Data and emulated FDL localBxNr different.";
1378  m_myCoutStream << "\n Data: localBxNr() = " << localBxNrData;
1379  m_myCoutStream << "\n Emul: localBxNr() = " << localBxNrEmul;
1380  m_myCoutStream << "\n";
1381 
1382  if (matchBxInEvent && validBxInEvent) {
1383  m_fdlDataEmul[histIndex][iRec]->Fill(12);
1384  } else {
1385  m_fdlDataEmul_Err[iRec]->Fill(12);
1386  }
1387 
1388  }
1389 
1390  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1391  m_myCoutStream.str("");
1392  m_myCoutStream.clear();
1393 
1394 }
1395 
1396 //compare the PSB board
1397 void L1GtHwValidation::comparePSB(const edm::Event& iEvent,
1398  const edm::EventSetup& evSetup, const L1GtPsbWord& psbBlockData,
1399  const L1GtPsbWord& psbBlockEmul) {
1400 
1401  if (psbBlockData == psbBlockEmul) {
1402  m_myCoutStream << "\nData and emulated PSB blocks: identical.\n";
1403  psbBlockData.print(m_myCoutStream);
1404 
1405  } else {
1406  m_myCoutStream << "\nData and emulated PSB blocks: different.\n";
1407 
1408  m_myCoutStream << "\nData: PSB block\n";
1409  psbBlockData.print(m_myCoutStream);
1410 
1411  m_myCoutStream << "\nEmul: PSB block\n";
1412  psbBlockEmul.print(m_myCoutStream);
1413 
1414  }
1415 
1416  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1417 
1418  m_myCoutStream.str("");
1419  m_myCoutStream.clear();
1420 
1421  // get BoardId value
1422  const boost::uint16_t boardIdData = psbBlockData.boardId();
1423  const boost::uint16_t boardIdEmul = psbBlockEmul.boardId();
1424 
1425  if (boardIdData == boardIdEmul) {
1426  m_myCoutStream << "\nData and emulated PSB boardId identical.";
1427  m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4)
1428  << std::setfill('0') << boardIdData << std::setfill(' ')
1429  << std::dec;
1430  m_myCoutStream << "\n";
1431 
1432  } else {
1433  m_myCoutStream << "\nData and emulated PSB boardId different.";
1434  m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x"
1435  << std::setw(4) << std::setfill('0') << boardIdData
1436  << std::setfill(' ') << std::dec;
1437  m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x"
1438  << std::setw(4) << std::setfill('0') << boardIdEmul
1439  << std::setfill(' ') << std::dec;
1440  m_myCoutStream << "\n";
1441 
1442  }
1443 
1444  // get bunch cross in the GT event record
1445  const int bxInEventData = psbBlockData.bxInEvent();
1446  const int bxInEventEmul = psbBlockEmul.bxInEvent();
1447 
1448  if (bxInEventData == bxInEventEmul) {
1449  m_myCoutStream << "\nData and emulated PSB bxInEvent identical.";
1450  m_myCoutStream << "\n bxInEvent() = " << bxInEventData;
1451  m_myCoutStream << "\n";
1452 
1453  } else {
1454  m_myCoutStream << "\nData and emulated PSB bxInEvent different.";
1455  m_myCoutStream << "\n Data: bxInEvent() = " << bxInEventData;
1456  m_myCoutStream << "\n Emul: bxInEvent() = " << bxInEventEmul;
1457  m_myCoutStream << "\n";
1458 
1459  }
1460 
1461  // get BxNr - bunch cross number of the actual bx
1462  const boost::uint16_t bxNrData = psbBlockData.bxNr();
1463  const boost::uint16_t bxNrEmul = psbBlockEmul.bxNr();
1464 
1465  if (bxNrData == bxNrEmul) {
1466  m_myCoutStream << "\nData and emulated PSB bxNr identical.";
1467  m_myCoutStream << "\n bxNr() = " << bxNrData;
1468  m_myCoutStream << "\n";
1469 
1470  } else {
1471  m_myCoutStream << "\nData and emulated PSB bxNr different.";
1472  m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
1473  m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
1474  m_myCoutStream << "\n";
1475 
1476  }
1477 
1478  // get event number since last L1 reset generated in FDL
1479  const boost::uint32_t eventNrData = psbBlockData.eventNr();
1480  const boost::uint32_t eventNrEmul = psbBlockEmul.eventNr();
1481 
1482  if (eventNrData == eventNrEmul) {
1483  m_myCoutStream << "\nData and emulated PSB eventNr identical.";
1484  m_myCoutStream << "\n eventNr() = " << eventNrData;
1485  m_myCoutStream << "\n";
1486 
1487  } else {
1488  m_myCoutStream << "\nData and emulated PSB eventNr different.";
1489  m_myCoutStream << "\n Data: eventNr() = " << eventNrData;
1490  m_myCoutStream << "\n Emul: eventNr() = " << eventNrEmul;
1491  m_myCoutStream << "\n";
1492 
1493  }
1494 
1496  boost::uint16_t valData;
1497  boost::uint16_t valEmul;
1498 
1499  for (int iA = 0; iA < psbBlockData.NumberAData; ++iA) {
1500  valData = psbBlockData.aData(iA);
1501  valEmul = psbBlockEmul.aData(iA);
1502 
1503  if (valData == valEmul) {
1504  m_myCoutStream << "\nData and emulated PSB aData(" << iA
1505  << ") identical.";
1506  m_myCoutStream << "\n aData(iA) = " << std::hex << "0x"
1507  << std::setw(4) << std::setfill('0') << valData
1508  << std::setfill(' ') << std::dec;
1509  m_myCoutStream << "\n";
1510 
1511  } else {
1512  m_myCoutStream << "\nData and emulated PSB aData(" << iA
1513  << ") different.";
1514  m_myCoutStream << "\n Data: aData(iA) = " << std::hex << "0x"
1515  << std::setw(4) << std::setfill('0') << valData
1516  << std::setfill(' ') << std::dec;
1517  m_myCoutStream << "\n Emul: aData(iA) = " << std::hex << "0x"
1518  << std::setw(4) << std::setfill('0') << valEmul
1519  << std::setfill(' ') << std::dec;
1520  m_myCoutStream << "\n";
1521 
1522  }
1523 
1524  }
1525 
1527  for (int iB = 0; iB < psbBlockData.NumberBData; ++iB) {
1528  valData = psbBlockData.bData(iB);
1529  valEmul = psbBlockEmul.bData(iB);
1530 
1531  if (valData == valEmul) {
1532  m_myCoutStream << "\nData and emulated PSB bData(" << iB
1533  << ") identical.";
1534  m_myCoutStream << "\n bData(iA) = " << std::hex << "0x"
1535  << std::setw(4) << std::setfill('0') << valData
1536  << std::setfill(' ') << std::dec;
1537  m_myCoutStream << "\n";
1538 
1539  } else {
1540  m_myCoutStream << "\nData and emulated PSB bData(" << iB
1541  << ") different.";
1542  m_myCoutStream << "\n Data: bData(iA) = " << std::hex << "0x"
1543  << std::setw(4) << std::setfill('0') << valData
1544  << std::setfill(' ') << std::dec;
1545  m_myCoutStream << "\n Emul: bData(iA) = " << std::hex << "0x"
1546  << std::setw(4) << std::setfill('0') << valEmul
1547  << std::setfill(' ') << std::dec;
1548  m_myCoutStream << "\n";
1549 
1550  }
1551 
1552  }
1553 
1554  // get local bunch cross number of the actual bx
1555  const boost::uint16_t localBxNrData = psbBlockData.localBxNr();
1556  const boost::uint16_t localBxNrEmul = psbBlockEmul.localBxNr();
1557 
1558  if (localBxNrData == localBxNrEmul) {
1559  m_myCoutStream << "\nData and emulated PSB localBxNr identical.";
1560  m_myCoutStream << "\n localBxNr() = " << localBxNrData;
1561  m_myCoutStream << "\n";
1562 
1563  } else {
1564  m_myCoutStream << "\nData and emulated PSB localBxNr different.";
1565  m_myCoutStream << "\n Data: localBxNr() = " << localBxNrData;
1566  m_myCoutStream << "\n Emul: localBxNr() = " << localBxNrEmul;
1567  m_myCoutStream << "\n";
1568 
1569  }
1570 
1571  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1572  m_myCoutStream.str("");
1573  m_myCoutStream.clear();
1574 
1575 }
1576 
1577 //compare the TCS board
1578 void L1GtHwValidation::compareTCS(const edm::Event& iEvent,
1579  const edm::EventSetup& evSetup, const L1TcsWord&, const L1TcsWord&) {
1580  // empty
1581 }
1582 
1583 //L1 GT DAQ record comparison
1584 void L1GtHwValidation::compareDaqRecord(const edm::Event& iEvent,
1585  const edm::EventSetup& evSetup) {
1586 
1587  // formal index for DAQ record
1588  int iRec = 0;
1589 
1590  // reset the flags - they are used for DAQ recor only
1591  m_agree = true;
1592  m_dataOnly = false;
1593  m_emulOnly = false;
1594  m_dataOnlyMask = false;
1595  m_emulOnlyMask = false;
1596 
1597 
1598  // get the L1 GT hardware DAQ record L1GlobalTriggerReadoutRecord
1599  edm::Handle<L1GlobalTriggerReadoutRecord> gtReadoutRecordData;
1600  iEvent.getByToken(m_l1GtDataDaqInputToken_, gtReadoutRecordData);
1601 
1602  bool validData = false;
1603 
1604  if (!gtReadoutRecordData.isValid()) {
1605  m_nrDataEventError++;
1606  } else {
1607  validData = true;
1608  }
1609 
1610  // get the L1 GT emulator DAQ record L1GlobalTriggerReadoutRecord
1611  edm::Handle<L1GlobalTriggerReadoutRecord> gtReadoutRecordEmul;
1612  iEvent.getByToken(m_l1GtEmulDaqInputToken_, gtReadoutRecordEmul);
1613 
1614  bool validEmul = false;
1615 
1616  if (!gtReadoutRecordEmul.isValid()) {
1617  m_nrEmulEventError++;
1618  } else {
1619  validEmul = true;
1620  }
1621 
1622  if ((!validData) || (!validEmul)) {
1623  edm::LogWarning("L1GtHwValidation")
1624  << "\n No valid product found: DAQ L1GlobalTriggerReadoutRecord"
1625  << "\n Data validity [1 = true; 0 = false]: " << validData
1626  << "\n Emulator validity: [1 = true; 0 = false]: "
1627  << validEmul << "\n DAQ histograms will not be filled.\n"
1628  << std::endl;
1629 
1630  return;
1631  }
1632 
1633  // compare GTFE
1634  const L1GtfeWord& gtfeBlockData = gtReadoutRecordData->gtfeWord();
1635  const L1GtfeWord& gtfeBlockEmul = gtReadoutRecordEmul->gtfeWord();
1636 
1637  compareGTFE(iEvent, evSetup, gtfeBlockData, gtfeBlockEmul, iRec);
1638 
1639  // FDL comparison
1640  const std::vector<L1GtFdlWord>& gtFdlVectorData =
1641  gtReadoutRecordData->gtFdlVector();
1642  const std::vector<L1GtFdlWord>& gtFdlVectorEmul =
1643  gtReadoutRecordEmul->gtFdlVector();
1644 
1645  int gtFdlVectorDataSize = gtFdlVectorData.size();
1646  int gtFdlVectorEmulSize = gtFdlVectorEmul.size();
1647 
1648  if (gtFdlVectorDataSize == gtFdlVectorEmulSize) {
1649  m_myCoutStream << "\nData and emulated FDL vector size: identical.\n";
1650  m_myCoutStream << " Size: " << gtFdlVectorDataSize << std::endl;
1651 
1652  for (int iFdl = 0; iFdl < gtFdlVectorDataSize; ++iFdl) {
1653 
1654  const L1GtFdlWord& fdlBlockData = gtFdlVectorData[iFdl];
1655  const L1GtFdlWord& fdlBlockEmul = gtFdlVectorEmul[iFdl];
1656 
1657  compareFDL(iEvent, evSetup, fdlBlockData, fdlBlockEmul, iRec);
1658  }
1659  } else {
1660  m_myCoutStream << "\nData and emulated FDL vector size: different.\n";
1661  m_myCoutStream << " Data: size = " << gtFdlVectorDataSize << std::endl;
1662  m_myCoutStream << " Emul: size = " << gtFdlVectorEmulSize << std::endl;
1663 
1664  }
1665 
1666  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1667 
1668  m_myCoutStream.str("");
1669  m_myCoutStream.clear();
1670 
1671  // PSB comparison
1672  const std::vector<L1GtPsbWord>& gtPsbVectorData =
1673  gtReadoutRecordData->gtPsbVector();
1674  const std::vector<L1GtPsbWord>& gtPsbVectorEmul =
1675  gtReadoutRecordEmul->gtPsbVector();
1676 
1677  int gtPsbVectorDataSize = gtPsbVectorData.size();
1678  int gtPsbVectorEmulSize = gtPsbVectorEmul.size();
1679 
1680  if (gtPsbVectorDataSize == gtPsbVectorEmulSize) {
1681  m_myCoutStream << "\nData and emulated PSB vector size: identical.\n";
1682  m_myCoutStream << " Size: " << gtPsbVectorDataSize << std::endl;
1683  } else {
1684  m_myCoutStream << "\nData and emulated PSB vector size: different.\n";
1685  m_myCoutStream << " Data: size = " << gtPsbVectorDataSize << std::endl;
1686  m_myCoutStream << " Emul: size = " << gtPsbVectorEmulSize << std::endl;
1687 
1688  }
1689 
1690  // the order of PSB block in the gtPsbVector is different in emulator and in data
1691  // in emulator: all active PSB in one BxInEvent, ordered L1A-1, L1A, L1A+1
1692  // in unpacker: every PSB in all BxInEvent
1693  for (int iPsb = 0; iPsb < gtPsbVectorDataSize; ++iPsb) {
1694 
1695  const L1GtPsbWord& psbBlockData = gtPsbVectorData[iPsb];
1696  const boost::uint16_t boardIdData = psbBlockData.boardId();
1697  const int bxInEventData = psbBlockData.bxInEvent();
1698 
1699  // search the corresponding PSB in the emulated record using the
1700  // BoardId and the BxInEvent
1701 
1702  bool foundPSB = false;
1703 
1704  for (int iPsbF = 0; iPsbF < gtPsbVectorEmulSize; ++iPsbF) {
1705 
1706  const L1GtPsbWord& psbBlockEmul = gtPsbVectorEmul[iPsbF];
1707  const boost::uint16_t boardIdEmul = psbBlockEmul.boardId();
1708  const int bxInEventEmul = psbBlockEmul.bxInEvent();
1709 
1710  if ((boardIdEmul == boardIdData)
1711  && (bxInEventData == bxInEventEmul)) {
1712 
1713  foundPSB = true;
1714 
1715  // compare the boards
1716  comparePSB(iEvent, evSetup, psbBlockData, psbBlockEmul);
1717  }
1718 
1719  }
1720 
1721  if (!foundPSB) {
1722  m_myCoutStream << "\nNo emulated PSB with boardId() = " << std::hex
1723  << "0x" << std::setw(4) << std::setfill('0') << boardIdData
1724  << std::setfill(' ') << std::dec << " and BxInEvent = "
1725  << bxInEventData << " was found";
1726 
1727  }
1728 
1729  }
1730 
1731  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1732 
1733  m_myCoutStream.str("");
1734  m_myCoutStream.clear();
1735 
1736  // fill the m_gtErrorFlag histogram (only for L1 GT DAQ record)
1737 
1738 
1739  if (m_dbe) {
1740  m_dbe->setCurrentFolder(m_dirName);
1741  }
1742 
1743 
1744  if (m_agree) {
1745  m_gtErrorFlag->Fill(0.0001);
1746  }
1747 
1748  if (m_dataOnly || m_dataOnlyMask) {
1749  m_gtErrorFlag->Fill(3.0001);
1750  }
1751 
1752  if (m_emulOnly || m_emulOnlyMask) {
1753  m_gtErrorFlag->Fill(4.0001);
1754  }
1755 
1756 }
1757 
1758 // L1 GT EVM record comparison
1759 void L1GtHwValidation::compareEvmRecord(const edm::Event& iEvent,
1760  const edm::EventSetup& evSetup) {
1761 
1762  // formal index for EVM record
1763  int iRec = 1;
1764 
1765  // get the L1 GT hardware EVM record L1GlobalTriggerEvmReadoutRecord
1766  edm::Handle<L1GlobalTriggerEvmReadoutRecord> gtReadoutRecordData;
1767  iEvent.getByToken(m_l1GtDataEvmInputToken_, gtReadoutRecordData);
1768 
1769  bool validData = false;
1770 
1771  if (!gtReadoutRecordData.isValid()) {
1772  m_nrDataEventError++;
1773  } else {
1774  validData = true;
1775  }
1776 
1777  // get the L1 GT emulator EVM record L1GlobalTriggerEvmReadoutRecord
1778  edm::Handle<L1GlobalTriggerEvmReadoutRecord> gtReadoutRecordEmul;
1779  iEvent.getByToken(m_l1GtEmulEvmInputToken_, gtReadoutRecordEmul);
1780 
1781  bool validEmul = false;
1782 
1783  if (!gtReadoutRecordEmul.isValid()) {
1784  m_nrEmulEventError++;
1785  } else {
1786  validEmul = true;
1787  }
1788 
1789  if ((!validData) || (!validEmul)) {
1790  edm::LogWarning("L1GtHwValidation")
1791  << "\n No valid product found: EVM L1GlobalTriggerEvmReadoutRecord"
1792  << "\n Data validity [1 = true; 0 = false]: " << validData
1793  << "\n Emulator validity: [1 = true; 0 = false]: "
1794  << validEmul << "\n EVM histograms will not be filled.\n"
1795  << std::endl;
1796 
1797  return;
1798  }
1799 
1800  // compare GTFE
1801  const L1GtfeWord& gtfeBlockData = gtReadoutRecordData->gtfeWord();
1802  const L1GtfeWord& gtfeBlockEmul = gtReadoutRecordEmul->gtfeWord();
1803 
1804  compareGTFE(iEvent, evSetup, gtfeBlockData, gtfeBlockEmul, iRec);
1805 
1806  // FDL comparison
1807  const std::vector<L1GtFdlWord>& gtFdlVectorData =
1808  gtReadoutRecordData->gtFdlVector();
1809  const std::vector<L1GtFdlWord>& gtFdlVectorEmul =
1810  gtReadoutRecordEmul->gtFdlVector();
1811 
1812  int gtFdlVectorDataSize = gtFdlVectorData.size();
1813  int gtFdlVectorEmulSize = gtFdlVectorEmul.size();
1814 
1815  if (gtFdlVectorDataSize == gtFdlVectorEmulSize) {
1816  m_myCoutStream << "\nData and emulated FDL vector size: identical.\n";
1817  m_myCoutStream << " Size: " << gtFdlVectorDataSize << std::endl;
1818 
1819  for (int iFdl = 0; iFdl < gtFdlVectorDataSize; ++iFdl) {
1820 
1821  const L1GtFdlWord& fdlBlockData = gtFdlVectorData[iFdl];
1822  const L1GtFdlWord& fdlBlockEmul = gtFdlVectorEmul[iFdl];
1823 
1824  compareFDL(iEvent, evSetup, fdlBlockData, fdlBlockEmul, iRec);
1825  }
1826  } else {
1827  m_myCoutStream << "\nData and emulated FDL vector size: different.\n";
1828  m_myCoutStream << " Data: size = " << gtFdlVectorDataSize << std::endl;
1829  m_myCoutStream << " Emul: size = " << gtFdlVectorEmulSize << std::endl;
1830 
1831  }
1832 
1833  // FIXME compare TCS
1834 
1835  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1836 
1837  m_myCoutStream.str("");
1838  m_myCoutStream.clear();
1839 
1840  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1841 
1842  m_myCoutStream.str("");
1843  m_myCoutStream.clear();
1844 
1845 }
1846 
1847 // compare the GCT collections obtained from L1 GT PSB with the input
1848 // GCT collections
1849 void L1GtHwValidation::compareGt_Gct(const edm::Event& iEvent,
1850  const edm::EventSetup&) {
1851 
1852  // FIXME
1853 
1854 }
1855 
1856 // analyze each event: event loop
1857 void L1GtHwValidation::analyze(const edm::Event& iEvent,
1858  const edm::EventSetup& evSetup) {
1859 
1860  ++m_nrEvJob;
1861  ++m_nrEvRun;
1862 
1863  // L1 GT DAQ record comparison
1864  compareDaqRecord(iEvent, evSetup);
1865 
1866  // L1 GT EVM record comparison
1867  compareEvmRecord(iEvent, evSetup);
1868 
1869  // GCT collections from L1 GT PSB versus unpacked GCT
1870  compareGt_Gct(iEvent, evSetup);
1871 
1872 }
1873 
1874 // book all histograms for the module
1875 void L1GtHwValidation::bookHistograms() {
1876 
1877  // histograms
1878 
1879  const unsigned int numberTechTriggers =
1880  L1GlobalTriggerReadoutSetup::NumberTechnicalTriggers;
1881 
1882  const unsigned int numberAlgoTriggers =
1883  L1GlobalTriggerReadoutSetup::NumberPhysTriggers;
1884 
1885  for (int iRec = 0; iRec < NumberOfGtRecords; ++iRec) {
1886 
1887  std::string recString;
1888  if (iRec == 0) {
1889  recString = "Daq_";
1890  if (m_dbe) {
1891  m_dbe->setCurrentFolder(m_dirName + "/DAQ/");
1892  }
1893 
1894  } else {
1895  recString = "Evm_";
1896  if (m_dbe) {
1897  m_dbe->setCurrentFolder(m_dirName + "/EVM/");
1898  }
1899  }
1900 
1901  std::string hName;
1902  const char* histName;
1903 
1904  hName = recString + "gtfeDataEmul";
1905  histName = hName.c_str();
1906 
1907  // GTFE histograms
1908  m_gtfeDataEmul[iRec] = m_dbe->book1D(histName,
1909  "GTFE data vs emul mismatch", 8, 0., 7.);
1910  m_gtfeDataEmul[iRec]->setBinLabel(1, "BoardId", 1);
1911  m_gtfeDataEmul[iRec]->setBinLabel(2, "RecordLength1", 1);
1912  m_gtfeDataEmul[iRec]->setBinLabel(3, "RecordLength0", 1);
1913  m_gtfeDataEmul[iRec]->setBinLabel(4, "BxNr", 1);
1914  m_gtfeDataEmul[iRec]->setBinLabel(5, "SetupVersion", 1);
1915  m_gtfeDataEmul[iRec]->setBinLabel(6, "DaqActiveBoards", 1);
1916  m_gtfeDataEmul[iRec]->setBinLabel(7, "AltNrBxBoard", 1);
1917  m_gtfeDataEmul[iRec]->setBinLabel(8, "TotalTriggerNr", 1);
1918 
1919  // FDL histograms
1920 
1921  for (int iHist = 0; iHist < TotalBxInEvent; ++iHist) {
1922 
1923  // convert [0, TotalBxInEvent] to [-X, +X] and add to histogram name
1924  int iIndex = iHist - ((TotalBxInEvent + 1) / 2 - 1);
1925  int hIndex = (iIndex + 16) % 16;
1926 
1927  std::stringstream ss;
1928  std::string str;
1929  ss << std::uppercase << std::hex << hIndex;
1930  ss >> str;
1931 
1932  if (iRec == 0) {
1933  if (m_dbe) {
1934  m_dbe->setCurrentFolder(m_dirName + "/DAQ/BxInEvent_" + str);
1935  }
1936 
1937  } else {
1938  if (m_dbe) {
1939  m_dbe->setCurrentFolder(m_dirName + "/EVM/BxInEvent_" + str);
1940  }
1941  }
1942 
1943  hName = recString + "FdlDataEmul_" + str;
1944  histName = hName.c_str();
1945 
1946  std::string hTitle = "FDL data vs emul mismatch for BxInEvent = "
1947  + str;
1948  const char* histTitle = hTitle.c_str();
1949 
1950  //
1951 
1952  m_fdlDataEmul[iHist][iRec] = m_dbe->book1D(histName, histTitle, 13,
1953  0., 13.);
1954  m_fdlDataEmul[iHist][iRec]->setBinLabel(1, "BoardId", 1);
1955  m_fdlDataEmul[iHist][iRec]->setBinLabel(2, "BxInEvent", 1);
1956  m_fdlDataEmul[iHist][iRec]->setBinLabel(3, "BxNr", 1);
1957  m_fdlDataEmul[iHist][iRec]->setBinLabel(4, "EventNr", 1);
1958  m_fdlDataEmul[iHist][iRec]->setBinLabel(5, "TechTrigger", 1);
1959  m_fdlDataEmul[iHist][iRec]->setBinLabel(6, "TechTriggerMask", 1);
1960  m_fdlDataEmul[iHist][iRec]->setBinLabel(7, "AlgoTrigger", 1);
1961  m_fdlDataEmul[iHist][iRec]->setBinLabel(8, "AlgoTriggerMask", 1);
1962  m_fdlDataEmul[iHist][iRec]->setBinLabel(9, "AlgoExtend", 1);
1963  m_fdlDataEmul[iHist][iRec]->setBinLabel(10, "NoAlgo", 1);
1964  m_fdlDataEmul[iHist][iRec]->setBinLabel(11, "FinalORAllParts", 1);
1965  m_fdlDataEmul[iHist][iRec]->setBinLabel(12, "FinalORPhysPart", 1);
1966  m_fdlDataEmul[iHist][iRec]->setBinLabel(13, "LocalBxNr", 1);
1967 
1968  // algorithm decision
1969  // data
1970  hName = recString + "Data_AlgoDecision_" + str;
1971  histName = hName.c_str();
1972 
1973  hTitle = "Data: algorithm decision word for BxInEvent = " + str;
1974  histTitle = hTitle.c_str();
1975 
1976  m_fdlDataAlgoDecision[iHist][iRec] = m_dbe->book1D(histName,
1977  histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
1978 
1979  // emul
1980  hName = recString + "Emul_AlgoDecision_" + str;
1981  histName = hName.c_str();
1982 
1983  hTitle = "Emul: algorithm decision word for BxInEvent = " + str;
1984  histTitle = hTitle.c_str();
1985 
1986  m_fdlEmulAlgoDecision[iHist][iRec] = m_dbe->book1D(histName,
1987  histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
1988 
1989  // algorithm decision for prescaled algorithms
1990  // data
1991  hName = recString + "Data_AlgoDecision_Prescaled_" + str;
1992  histName = hName.c_str();
1993 
1994  hTitle
1995  = "Data: prescaled algorithms: algorithm decision for BxInEvent = "
1996  + str;
1997  histTitle = hTitle.c_str();
1998 
1999  m_fdlDataAlgoDecisionPrescaled[iHist][iRec] = m_dbe->book1D(
2000  histName, histTitle, numberAlgoTriggers, 0.,
2001  numberAlgoTriggers);
2002 
2003  // emul
2004  hName = recString + "Emul_AlgoDecision_Prescaled_" + str;
2005  histName = hName.c_str();
2006 
2007  hTitle
2008  = "Emul: prescaled algorithms: algorithm decision for BxInEvent = "
2009  + str;
2010  histTitle = hTitle.c_str();
2011 
2012  m_fdlEmulAlgoDecisionPrescaled[iHist][iRec] = m_dbe->book1D(
2013  histName, histTitle, numberAlgoTriggers, 0.,
2014  numberAlgoTriggers);
2015 
2016  // algorithm decision for unprescaled algorithms
2017  // data
2018  hName = recString + "Data_AlgoDecision_Unprescaled_" + str;
2019  histName = hName.c_str();
2020 
2021  hTitle
2022  = "Data: unprescaled algorithms: algorithm decision for BxInEvent = "
2023  + str;
2024  histTitle = hTitle.c_str();
2025 
2026  m_fdlDataAlgoDecisionUnprescaled[iHist][iRec] = m_dbe->book1D(
2027  histName, histTitle, numberAlgoTriggers, 0.,
2028  numberAlgoTriggers);
2029 
2030  // emul
2031  hName = recString + "Emul_AlgoDecision_Unprescaled_" + str;
2032  histName = hName.c_str();
2033 
2034  hTitle
2035  = "Emul: unprescaled algorithms: algorithm decision for BxInEvent = "
2036  + str;
2037  histTitle = hTitle.c_str();
2038 
2039  m_fdlEmulAlgoDecisionUnprescaled[iHist][iRec] = m_dbe->book1D(
2040  histName, histTitle, numberAlgoTriggers, 0.,
2041  numberAlgoTriggers);
2042 
2043  // algorithm decision after masking (partition physics)
2044  // data
2045  hName = recString + "Data_AlgoDecisionAfterMask_" + str;
2046  histName = hName.c_str();
2047 
2048  hTitle
2049  = "Data, physics partition: algorithm decision word after mask for BxInEvent = "
2050  + str;
2051  histTitle = hTitle.c_str();
2052 
2053  m_fdlDataAlgoDecisionMask[iHist][iRec] = m_dbe->book1D(histName,
2054  histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
2055 
2056  // emul
2057  hName = recString + "Emul_AlgoDecisionAfterMask_" + str;
2058  histName = hName.c_str();
2059 
2060  hTitle
2061  = "Emul, physics partition: algorithm decision word after mask for BxInEvent = "
2062  + str;
2063  histTitle = hTitle.c_str();
2064 
2065  m_fdlEmulAlgoDecisionMask[iHist][iRec] = m_dbe->book1D(histName,
2066  histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
2067 
2068  //
2069  hName = recString + "DataEmul_AlgoDecision_" + str;
2070  histName = hName.c_str();
2071 
2072  hTitle
2073  = "Data vs emul: non-matching algorithm decision word for BxInEvent = "
2074  + str;
2075  histTitle = hTitle.c_str();
2076 
2077  m_fdlDataEmulAlgoDecision[iHist][iRec] = m_dbe->book1D(histName,
2078  histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
2079 
2080  //
2081  hName = recString + "DataEmul_AlgoDecision_Prescaled_" + str;
2082  histName = hName.c_str();
2083 
2084  hTitle
2085  = "Data vs emul: prescaled algorithms with non-matching decision for BxInEvent = "
2086  + str;
2087  histTitle = hTitle.c_str();
2088 
2089  m_fdlDataEmulAlgoDecisionPrescaled[iHist][iRec] = m_dbe->book1D(
2090  histName, histTitle, numberAlgoTriggers, 0.,
2091  numberAlgoTriggers);
2092 
2093  //
2094  hName = recString + "DataEmul_AlgoDecision_Unprescaled_" + str;
2095  histName = hName.c_str();
2096 
2097  hTitle
2098  = "Data vs emul: unprescaled algorithms with non-matching decision for BxInEvent = "
2099  + str;
2100  histTitle = hTitle.c_str();
2101 
2102  m_fdlDataEmulAlgoDecisionUnprescaled[iHist][iRec] = m_dbe->book1D(
2103  histName, histTitle, numberAlgoTriggers, 0.,
2104  numberAlgoTriggers);
2105 
2106  //
2107  hName = recString + "DataEmul_AlgoDecision_Unprescaled_Allowed_" + str;
2108  histName = hName.c_str();
2109 
2110  hTitle
2111  = "Data vs emul: unprescaled algorithms not excluded with non-matching decision for BxInEvent = "
2112  + str;
2113  histTitle = hTitle.c_str();
2114 
2115  m_fdlDataEmulAlgoDecisionUnprescaledAllowed[iHist][iRec] = m_dbe->book1D(
2116  histName, histTitle, numberAlgoTriggers, 0.,
2117  numberAlgoTriggers);
2118 
2119  //
2120  hName = recString + "Data_AlgoDecision_NoMatch_" + str;
2121  histName = hName.c_str();
2122 
2123  hTitle
2124  = "Data: algorithm decision for non-matching cases for BxInEvent = "
2125  + str;
2126  histTitle = hTitle.c_str();
2127 
2128  m_fdlDataAlgoDecision_NoMatch[iHist][iRec] = m_dbe->book1D(
2129  histName, histTitle, numberAlgoTriggers, 0.,
2130  numberAlgoTriggers);
2131 
2132  //
2133  hName = recString + "Emul_AlgoDecision_NoMatch_" + str;
2134  histName = hName.c_str();
2135 
2136  hTitle
2137  = "Emul: algorithm decision for non-matching cases for BxInEvent = "
2138  + str;
2139  histTitle = hTitle.c_str();
2140 
2141  m_fdlEmulAlgoDecision_NoMatch[iHist][iRec] = m_dbe->book1D(
2142  histName, histTitle, numberAlgoTriggers, 0.,
2143  numberAlgoTriggers);
2144 
2145  // prescaled algorithms
2146  hName = recString + "Data_AlgoDecision_Prescaled_NoMatch_" + str;
2147  histName = hName.c_str();
2148 
2149  hTitle
2150  = "Data: prescaled algorithms: non-matching algorithm decision for BxInEvent = "
2151  + str;
2152  histTitle = hTitle.c_str();
2153 
2154  m_fdlDataAlgoDecisionPrescaled_NoMatch[iHist][iRec]
2155  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2156  0., numberAlgoTriggers);
2157 
2158  //
2159  hName = recString + "Emul_AlgoDecision_Prescaled_NoMatch_" + str;
2160  histName = hName.c_str();
2161 
2162  hTitle
2163  = "Emul: prescaled algorithms: non-matching algorithm decision for BxInEvent = "
2164  + str;
2165  histTitle = hTitle.c_str();
2166 
2167  m_fdlEmulAlgoDecisionPrescaled_NoMatch[iHist][iRec]
2168  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2169  0., numberAlgoTriggers);
2170 
2171 
2172  // unprescaled algorithms - non-matching
2173  hName = recString + "Data_AlgoDecision_Unprescaled_NoMatch_" + str;
2174  histName = hName.c_str();
2175 
2176  hTitle
2177  = "Data: unprescaled algorithms: non-matching algorithm decision for BxInEvent = "
2178  + str;
2179  histTitle = hTitle.c_str();
2180 
2181  m_fdlDataAlgoDecisionUnprescaled_NoMatch[iHist][iRec]
2182  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2183  0., numberAlgoTriggers);
2184 
2185  //
2186  hName = recString + "Emul_AlgoDecision_Unprescaled_NoMatch_" + str;
2187  histName = hName.c_str();
2188 
2189  hTitle
2190  = "Emul: unprescaled algorithms: non-matching algorithm decision for BxInEvent = "
2191  + str;
2192  histTitle = hTitle.c_str();
2193 
2194  m_fdlEmulAlgoDecisionUnprescaled_NoMatch[iHist][iRec]
2195  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2196  0., numberAlgoTriggers);
2197 
2198 
2199 
2200  //
2201  hName = recString + "Data_AlgoDecisionMask_NoMatch_" + str;
2202  histName = hName.c_str();
2203 
2204  hTitle
2205  = "Data: algorithm decision for non-matching cases after mask for BxInEvent = "
2206  + str;
2207  histTitle = hTitle.c_str();
2208 
2209  m_fdlDataAlgoDecisionMask_NoMatch[iHist][iRec] = m_dbe->book1D(
2210  histName, histTitle, numberAlgoTriggers, 0.,
2211  numberAlgoTriggers);
2212 
2213  //
2214  hName = recString + "Emul_AlgoDecisionMask_NoMatch_" + str;
2215  histName = hName.c_str();
2216 
2217  hTitle
2218  = "Emul: algorithm decision for non-matching cases after mask for BxInEvent = "
2219  + str;
2220  histTitle = hTitle.c_str();
2221 
2222  m_fdlEmulAlgoDecisionMask_NoMatch[iHist][iRec] = m_dbe->book1D(
2223  histName, histTitle, numberAlgoTriggers, 0.,
2224  numberAlgoTriggers);
2225 
2226  // prescaled algorithms
2227  hName = recString + "Data_AlgoDecisionMask_Prescaled_NoMatch_" + str;
2228  histName = hName.c_str();
2229 
2230  hTitle
2231  = "Data: prescaled algorithms: non-matching algorithm decision after mask for BxInEvent = "
2232  + str;
2233  histTitle = hTitle.c_str();
2234 
2235  m_fdlDataAlgoDecisionPrescaledMask_NoMatch[iHist][iRec]
2236  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2237  0., numberAlgoTriggers);
2238 
2239  //
2240  hName = recString + "Emul_AlgoDecision_PrescaledMask_NoMatch_" + str;
2241  histName = hName.c_str();
2242 
2243  hTitle
2244  = "Emul: prescaled algorithms: non-matching algorithm decision after mask for BxInEvent = "
2245  + str;
2246  histTitle = hTitle.c_str();
2247 
2248  m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[iHist][iRec]
2249  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2250  0., numberAlgoTriggers);
2251 
2252 
2253  // unprescaled algorithms - non-matching
2254  hName = recString + "Data_AlgoDecision_UnprescaledMask_NoMatch_" + str;
2255  histName = hName.c_str();
2256 
2257  hTitle
2258  = "Data: unprescaled algorithms: non-matching algorithm decision after mask for BxInEvent = "
2259  + str;
2260  histTitle = hTitle.c_str();
2261 
2262  m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[iHist][iRec]
2263  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2264  0., numberAlgoTriggers);
2265 
2266  //
2267  hName = recString + "Emul_AlgoDecision_UnprescaledMask_NoMatch_" + str;
2268  histName = hName.c_str();
2269 
2270  hTitle
2271  = "Emul: unprescaled algorithms: non-matching algorithm decision after mask for BxInEvent = "
2272  + str;
2273  histTitle = hTitle.c_str();
2274 
2275  m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[iHist][iRec]
2276  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2277  0., numberAlgoTriggers);
2278 
2279 
2280 
2281  //
2282  hName = recString + "DataEmul_AlgoDecisionAfterMask_" + str;
2283  histName = hName.c_str();
2284 
2285  hTitle
2286  = "Data vs emul, physics partition: non-matching algorithm decision word after mask for BxInEvent = "
2287  + str;
2288  histTitle = hTitle.c_str();
2289 
2290  m_fdlDataEmulAlgoDecisionMask[iHist][iRec] = m_dbe->book1D(
2291  histName, histTitle, numberAlgoTriggers, 0.,
2292  numberAlgoTriggers);
2293 
2294  // technical trigger decision
2295  // data
2296  hName = recString + "Data_TechDecision_" + str;
2297  histName = hName.c_str();
2298 
2299  hTitle = "Data technical trigger decision word for BxInEvent = "
2300  + str;
2301  histTitle = hTitle.c_str();
2302 
2303  m_fdlDataTechDecision[iHist][iRec] = m_dbe->book1D(histName,
2304  histTitle, numberTechTriggers, 0., numberTechTriggers);
2305 
2306  // emul
2307  hName = recString + "Emul_TechDecision_" + str;
2308  histName = hName.c_str();
2309 
2310  hTitle = "Emul: technical trigger decision word for BxInEvent = "
2311  + str;
2312  histTitle = hTitle.c_str();
2313 
2314  m_fdlEmulTechDecision[iHist][iRec] = m_dbe->book1D(histName,
2315  histTitle, numberTechTriggers, 0., numberTechTriggers);
2316 
2317  // technical trigger decision after masking (partition physics)
2318  hName = recString + "Data_TechDecisionAfterMask_" + str;
2319  histName = hName.c_str();
2320 
2321  hTitle
2322  = "Data technical trigger decision word after mask for BxInEvent = "
2323  + str;
2324  histTitle = hTitle.c_str();
2325 
2326  m_fdlDataTechDecisionMask[iHist][iRec] = m_dbe->book1D(histName,
2327  histTitle, numberTechTriggers, 0., numberTechTriggers);
2328 
2329  //
2330  hName = recString + "Emul_TechDecisionAfterMask_" + str;
2331  histName = hName.c_str();
2332 
2333  hTitle
2334  = "Emul: technical trigger decision word after mask for BxInEvent = "
2335  + str;
2336  histTitle = hTitle.c_str();
2337 
2338  m_fdlEmulTechDecisionMask[iHist][iRec] = m_dbe->book1D(histName,
2339  histTitle, numberTechTriggers, 0., numberTechTriggers);
2340 
2341  //
2342  hName = recString + "DataEmul_TechDecision_" + str;
2343  histName = hName.c_str();
2344 
2345  hTitle
2346  = "Data vs emul: non-matching technical trigger decision word for BxInEvent = "
2347  + str;
2348  histTitle = hTitle.c_str();
2349 
2350  m_fdlDataEmulTechDecision[iHist][iRec] = m_dbe->book1D(histName,
2351  histTitle, numberTechTriggers, 0., numberTechTriggers);
2352 
2353  hName = recString + "DataEmul_TechDecisionAfterMask_" + str;
2354  histName = hName.c_str();
2355 
2356  hTitle
2357  = "Data vs emul: non-matching technical trigger decision word after mask for BxInEvent = "
2358  + str;
2359  histTitle = hTitle.c_str();
2360 
2361  m_fdlDataEmulTechDecisionMask[iHist][iRec] = m_dbe->book1D(
2362  histName, histTitle, numberTechTriggers, 0.,
2363  numberTechTriggers);
2364 
2365  }
2366 
2367  if (iRec == 0) {
2368  if (m_dbe) {
2369  m_dbe->setCurrentFolder(m_dirName + "/DAQ/");
2370  }
2371 
2372  } else {
2373  if (m_dbe) {
2374  m_dbe->setCurrentFolder(m_dirName + "/EVM/");
2375  }
2376  }
2377 
2378  hName = recString + "FdlDataEmul_Err";
2379  histName = hName.c_str();
2380 
2381  m_fdlDataEmul_Err[iRec]
2382  = m_dbe->book1D(
2383  histName,
2384  "FDL data vs emul mismatch for non-matching BxInEvent in FDL payload",
2385  13, 0., 13.);
2386  m_fdlDataEmul_Err[iRec]->setBinLabel(1, "BoardId", 1);
2387  m_fdlDataEmul_Err[iRec]->setBinLabel(2, "BxInEvent", 1);
2388  m_fdlDataEmul_Err[iRec]->setBinLabel(3, "BxNr", 1);
2389  m_fdlDataEmul_Err[iRec]->setBinLabel(4, "EventNr", 1);
2390  m_fdlDataEmul_Err[iRec]->setBinLabel(5, "TechTrigger", 1);
2391  m_fdlDataEmul_Err[iRec]->setBinLabel(6, "TechTriggerMask", 1);
2392  m_fdlDataEmul_Err[iRec]->setBinLabel(7, "AlgoTrigger", 1);
2393  m_fdlDataEmul_Err[iRec]->setBinLabel(8, "AlgoTriggerMask", 1);
2394  m_fdlDataEmul_Err[iRec]->setBinLabel(9, "AlgoExtend", 1);
2395  m_fdlDataEmul_Err[iRec]->setBinLabel(10, "NoAlgo", 1);
2396  m_fdlDataEmul_Err[iRec]->setBinLabel(11, "FinalORAllParts", 1);
2397  m_fdlDataEmul_Err[iRec]->setBinLabel(12, "FinalORPhysPart", 1);
2398  m_fdlDataEmul_Err[iRec]->setBinLabel(13, "LocalBxNr", 1);
2399 
2400  hName = recString + "FdlDataAlgoDecision_Err";
2401  histName = hName.c_str();
2402 
2403  m_fdlDataAlgoDecision_Err[iRec]
2404  = m_dbe->book1D(
2405  histName,
2406  "Data: algorithm trigger decision word, non-matching BxInEvent",
2407  numberAlgoTriggers, 0., numberAlgoTriggers);
2408 
2409  //
2410  hName = recString + "Emul_AlgoDecision_Err";
2411  histName = hName.c_str();
2412 
2413  m_fdlEmulAlgoDecision_Err[iRec]
2414  = m_dbe->book1D(
2415  histName,
2416  "Emul: algorithm trigger decision word, non-matching BxInEvent",
2417  numberAlgoTriggers, 0., numberAlgoTriggers);
2418 
2419  hName = recString + "DataEmul_AlgoDecision_Err";
2420  histName = hName.c_str();
2421 
2422  m_fdlDataEmulAlgoDecision_Err[iRec]
2423  = m_dbe->book1D(
2424  histName,
2425  "Data vs emul: algorithm trigger decision word, non-matching BxInEvent",
2426  numberAlgoTriggers, 0., numberAlgoTriggers);
2427 
2428  //
2429  hName = recString + "Data_TechDecision_Err";
2430  histName = hName.c_str();
2431 
2432  m_fdlDataTechDecision_Err[iRec]
2433  = m_dbe->book1D(
2434  histName,
2435  "Data: technical trigger decision word, non-matching BxInEvent",
2436  numberTechTriggers, 0., numberTechTriggers);
2437 
2438  hName = recString + "Emul_TechDecision_Err";
2439  histName = hName.c_str();
2440 
2441  m_fdlEmulTechDecision_Err[iRec]
2442  = m_dbe->book1D(
2443  histName,
2444  "Emul: technical trigger decision word, non-matching BxInEvent",
2445  numberTechTriggers, 0., numberTechTriggers);
2446 
2447  hName = recString + "DataEmul_TechDecision_Err";
2448  histName = hName.c_str();
2449 
2450  m_fdlDataEmulTechDecision_Err[iRec]
2451  = m_dbe->book1D(
2452  histName,
2453  "Data vs emul: technical trigger decision word, non-matching BxInEvent",
2454  numberTechTriggers, 0., numberTechTriggers);
2455 
2456  }
2457 
2458  if (m_dbe) {
2459  m_dbe->setCurrentFolder(m_dirName);
2460  }
2461 
2462  //
2463  m_excludedAlgorithmsAgreement = m_dbe->book1D(
2464  "ExcludedAlgorithmsFromAgreement",
2465  "Algorithms excluded from data versus emulator agreement flag",
2466  numberAlgoTriggers, 0., numberAlgoTriggers);
2467 
2468  //
2469 
2470  m_gtErrorFlag = m_dbe->book1D("GTErrorFlag",
2471  "L1 GT error flag for data versus emulator comparison", 5, 0., 5);
2472 
2473  m_gtErrorFlag->setBinLabel(1, "Agree", 1);
2474  m_gtErrorFlag->setBinLabel(2, "", 1);
2475  m_gtErrorFlag->setBinLabel(3, "", 1);
2476  m_gtErrorFlag->setBinLabel(4, "Data only", 1);
2477  m_gtErrorFlag->setBinLabel(5, "Emul only", 1);
2478 
2479 
2480 }
2481 
2482 bool L1GtHwValidation::matchCondCategory(
2483  const L1GtConditionCategory& conditionCategory,
2484  const L1GtConditionCategory& excludedCategory) {
2485 
2486  bool matchValue = false;
2487 
2488  if (excludedCategory == CondNull) {
2489  matchValue = true;
2490  } else {
2491  if (conditionCategory == excludedCategory) {
2492  matchValue = true;
2493  }
2494  }
2495 
2496  return matchValue;
2497 }
2498 
2499 
2500 bool L1GtHwValidation::matchCondType(const L1GtConditionType& conditionType,
2501  const L1GtConditionType& excludedType) {
2502 
2503  bool matchValue = false;
2504 
2505  if (excludedType == TypeNull) {
2506  matchValue = true;
2507  } else {
2508  if (conditionType == excludedType) {
2509  matchValue = true;
2510  }
2511  }
2512 
2513  return matchValue;
2514 }
2515 
2516 
2517 bool L1GtHwValidation::matchCondL1GtObject(
2518  const std::vector<L1GtObject>& condObjects,
2519  const L1GtObject& excludedObject) {
2520 
2521  bool matchValue = false;
2522 
2523  if (excludedObject == ObjNull) {
2524 
2525  matchValue = true;
2526 
2527  } else {
2528 
2529  for (std::vector<L1GtObject>::const_iterator itCondObj =
2530  condObjects.begin(); itCondObj != condObjects.end(); ++itCondObj) {
2531 
2532  if ((*itCondObj) == excludedObject) {
2533 
2534  matchValue = true;
2535 
2536  }
2537  }
2538  }
2539 
2540  return matchValue;
2541 
2542 }
2543 
2544 
2545 void L1GtHwValidation::excludedAlgoList() {
2546 
2547 
2548  const AlgorithmMap& algorithmMap = m_l1GtMenu->gtAlgorithmMap();
2549  (const_cast<L1GtTriggerMenu*> (m_l1GtMenu))->buildGtConditionMap(); //...ugly
2550 
2551  for (CItAlgo itAlgo = algorithmMap.begin(); itAlgo != algorithmMap.end(); itAlgo++) {
2552 
2553  const std::string& algName = itAlgo->first;
2554  const int algBitNumber = (itAlgo->second).algoBitNumber();
2555  const int chipNr = (itAlgo->second).algoChipNumber();
2556 
2557  const ConditionMap& conditionMap = (m_l1GtMenu->gtConditionMap()).at(
2558  chipNr);
2559 
2560  const std::vector<L1GtLogicParser::TokenRPN>& aRpnVector =
2561  (itAlgo->second).algoRpnVector();
2562  size_t aRpnVectorSize = aRpnVector.size();
2563 
2564  bool algWithExcludedCondition = false;
2565  bool algWithConditionNotInMap = false;
2566 
2567  // loop over RpnVector and check each conditions against list of excluded conditions
2568  for (size_t opI = 0; opI < aRpnVectorSize; ++opI) {
2569 
2570  const std::string& cndName = (aRpnVector[opI]).operand;
2571 
2572  if (!cndName.empty()) {
2573  bool foundCond = false;
2574 
2575  CItCond itCond = conditionMap.find(cndName);
2576  if (itCond != conditionMap.end()) {
2577 
2578  const L1GtConditionCategory& cCateg = (itCond->second)->condCategory();
2579  const L1GtConditionType& cType = (itCond->second)->condType();
2580  const std::vector<L1GtObject>& objType = (itCond->second)->objectType();
2581 
2582  // condition index in the m_excludedCondCategory, m_excludedCondType, m_excludedL1GtObject vectors
2583  int iCond = -1;
2584 
2585  for (std::vector<L1GtConditionCategory>::const_iterator
2586  itCateg = m_excludedCondCategory.begin();
2587  itCateg != m_excludedCondCategory.end(); ++itCateg) {
2588 
2589  iCond++;
2590 
2591  bool matchCondCategoryValue = matchCondCategory(cCateg, (*itCateg));
2592  bool matchCondTypeValue = matchCondType(cType, m_excludedCondType.at(iCond));
2593  bool matchCondL1GtObjectValue = matchCondL1GtObject(objType, m_excludedL1GtObject.at(iCond));
2594 
2595  LogTrace("L1GtHwValidation")
2596  << "\n "
2597  << "Algorithm: " << algName
2598  << " Condition: " << cndName
2599  << "\n "
2600  << "Category: " << l1GtConditionCategoryEnumToString(cCateg)
2601  << "; excluded: " << l1GtConditionCategoryEnumToString((*itCateg))
2602  << "\n "
2603  << "Type: " << l1GtConditionTypeEnumToString(cType)
2604  << "; excluded: " << l1GtConditionTypeEnumToString(m_excludedCondType.at(iCond))
2605  << "\n "
2606  << "Object excluded: " << l1GtObjectEnumToString(m_excludedL1GtObject.at(iCond))
2607  << std::endl;
2608 
2609 
2610  if (matchCondCategoryValue && matchCondTypeValue && matchCondL1GtObjectValue) {
2611 
2612  algWithExcludedCondition = true;
2613 
2614  }
2615 
2616  }
2617 
2618  foundCond = true;
2619  }
2620 
2621  if (!foundCond) {
2622  // it should never be happen, all conditions are in the maps
2623 
2624  algWithConditionNotInMap = true;
2625 
2626  LogTrace("L1GtHwValidation") << "\n Error: condition "
2627  << cndName << " not found in condition map!"
2628  << "\n Add algorithm " << algName
2629  << " (bit number " << algBitNumber << ") "
2630  << "\n to list of algorithms excluded from comparison"
2631  << "\n data versus emulator." << std::endl;
2632  }
2633 
2634  }
2635  }
2636 
2637  if (algWithConditionNotInMap) {
2638  // it should never be happen, all conditions are in the maps
2639 
2640  m_excludedAlgoList.push_back(algBitNumber);
2641 
2642  LogTrace("L1GtHwValidation")
2643  << "\n Error: one or more conditions from algorithm "
2644  << algName << " (bit number " << algBitNumber << ") "
2645  << " not found in condition map!"
2646  << "\n Add it to list of algorithms excluded from comparison"
2647  << "\n data versus emulator." << std::endl;
2648  }
2649 
2650  if (algWithExcludedCondition) {
2651 
2652  m_excludedAlgoList.push_back(algBitNumber);
2653 
2654  LogTrace("L1GtHwValidation") << "\n Algorithm " << algName
2655  << " (bit number " << algBitNumber
2656  << ") contains an excluded condition."
2657  << "\n Add it to list of algorithms excluded from comparison"
2658  << "\n data versus emulator." << std::endl;
2659 
2660  }
2661 
2662  // add algorithm triggers from ExcludeAlgoTrigByName
2663  for (std::vector<std::string>::const_iterator
2664  itExcl = m_excludeAlgoTrigByName.begin();
2665  itExcl!= m_excludeAlgoTrigByName.end(); ++itExcl) {
2666 
2667  if ((*itExcl) == algName) {
2668 
2669  m_excludedAlgoList.push_back(algBitNumber);
2670 
2671  LogTrace("L1GtHwValidation") << "\n Algorithm " << algName
2672  << " (bit number " << algBitNumber
2673  << ")\n added to list of algorithms excluded from comparison"
2674  << " \n data versus emulator by ExcludeAlgoTrigByName." << std::endl;
2675  }
2676 
2677  }
2678 
2679 
2680  // add algorithm triggers from ExcludeAlgoTrigByBit
2681  for (std::vector<int>::const_iterator
2682  itExcl = m_excludeAlgoTrigByBit.begin();
2683  itExcl!= m_excludeAlgoTrigByBit.end(); ++itExcl) {
2684 
2685  if ((*itExcl) == algBitNumber) {
2686 
2687  m_excludedAlgoList.push_back(algBitNumber);
2688 
2689  LogTrace("L1GtHwValidation") << "\n Algorithm " << algName
2690  << " (bit number " << algBitNumber
2691  << ")\n added to list of algorithms excluded from comparison"
2692  << " \n data versus emulator by ExcludeAlgoTrigByBit." << std::endl;
2693  }
2694 
2695  }
2696 
2697  }
2698 
2699 }
2700 
2701 bool L1GtHwValidation::excludedAlgo(const int& iBit) const {
2702 
2703  for (std::vector<int>::const_iterator itAlgo = m_excludedAlgoList.begin(); itAlgo
2704  != m_excludedAlgoList.end(); ++itAlgo) {
2705 
2706  if (iBit == *itAlgo) {
2707  return true;
2708  }
2709  }
2710 
2711  return false;
2712 
2713 }
2714 
2715 
2716 void L1GtHwValidation::endRun(const edm::Run& run,
2717  const edm::EventSetup& evSetup) {
2718 
2719  LogDebug("L1GtHwValidation") << "\n\n endRun: " << run.id()
2720  << "\n Number of events analyzed in this run: " << m_nrEvRun
2721  << "\n Total number of events analyzed in this job: " << m_nrEvJob
2722  << "\n" << std::endl;
2723 
2724 }
2725 
2726 // method called once each job just after ending the event loop
2727 void L1GtHwValidation::endJob() {
2728 
2729  edm::LogInfo("L1GtHwValidation")
2730  << "\n\nTotal number of events analyzed in this job: " << m_nrEvJob
2731  << "\n" << std::endl;
2732 
2733  return;
2734 
2735 }
2736 
2737 //define this as a plug-in
2738 DEFINE_FWK_MODULE( L1GtHwValidation);
LogDebug
#define LogDebug(id)
Definition: MessageLogger.h:501
edm::ParameterSet::getParameter
T getParameter(std::string const &) const
L1GtPsbWord::bData
const cms_uint16_t bData(int iB) const
get/set B_DATA_CH_IB
Definition: L1GtPsbWord.cc:323
L1GtHwValidation::m_fdlDataEmulAlgoDecision
MonitorElement * m_fdlDataEmulAlgoDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:244
edm::ParameterSet::getUntrackedParameter
T getUntrackedParameter(std::string const &, T const &) const
L1GtHwValidation::m_fdlDataAlgoDecisionPrescaledMask_NoMatch
MonitorElement * m_fdlDataAlgoDecisionPrescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:227
L1GtPsbWord::bxNr
const cms_uint16_t bxNr() const
get/set bunch cross number of the actual bx
Definition: L1GtPsbWord.h:108
L1GtFdlWord::gtTechnicalTriggerWord
const TechnicalTriggerWord & gtTechnicalTriggerWord() const
get/set technical trigger bits
Definition: L1GtFdlWord.h:149
L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaled_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionUnprescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:237
L1GtHwValidation::m_l1GtTmTech
const L1GtTriggerMask * m_l1GtTmTech
Definition: L1GtHwValidation.h:188
L1GtPsbWord::boardId
const cms_uint16_t boardId() const
get/set board ID
Definition: L1GtPsbWord.h:66
edm::RunBase::id
RunID const & id() const
Definition: RunBase.h:41
L1GtHwValidation::m_fdlDataAlgoDecision_Err
MonitorElement * m_fdlDataAlgoDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:229
L1GtFdlWord::noAlgo
const cms_uint16_t noAlgo() const
get/set NoAlgo
Definition: L1GtFdlWord.h:286
L1GtHwValidation::m_l1GtDataEvmInputToken_
edm::EDGetTokenT< L1GlobalTriggerEvmReadoutRecord > m_l1GtDataEvmInputToken_
Definition: L1GtHwValidation.h:285
L1GtHwValidation::compareGTFE
virtual void compareGTFE(const edm::Event &, const edm::EventSetup &, const L1GtfeWord &, const L1GtfeWord &, const int)
compare the GTFE board
Definition: L1GtHwValidation.cc:405
L1GtHwValidation::matchCondCategory
bool matchCondCategory(const L1GtConditionCategory &, const L1GtConditionCategory &)
Definition: L1GtHwValidation.cc:2482
L1GtHwValidation::analyze
virtual void analyze(const edm::Event &, const edm::EventSetup &)
Definition: L1GtHwValidation.cc:1857
L1GtHwValidation::comparePSB
virtual void comparePSB(const edm::Event &, const edm::EventSetup &, const L1GtPsbWord &, const L1GtPsbWord &)
compare the PSB board
Definition: L1GtHwValidation.cc:1397
DQMStore::book1D
MonitorElement * book1D(const char *name, const char *title, int nchX, double lowX, double highX)
Book 1D histogram.
Definition: DQMStore.cc:954
L1GtfeWord::print
virtual void print(std::ostream &myCout) const
pretty print the content of a L1GtfeWord
Definition: L1GtfeWord.cc:321
DQMStore::rmdir
void rmdir(const std::string &fullpath)
Definition: DQMStore.cc:3101
L1GtHwValidation::m_prescaleFactorsAlgoTrig
const std::vector< std::vector< int > > * m_prescaleFactorsAlgoTrig
Definition: L1GtHwValidation.h:181
L1GtHwValidation::m_gtErrorFlag
MonitorElement * m_gtErrorFlag
PSB.
Definition: L1GtHwValidation.h:272
edm::Event::getByToken
bool getByToken(EDGetToken token, Handle< PROD > &result) const
Definition: Event.h:434
ConditionMap
std::map< std::string, L1GtCondition * > ConditionMap
map containing the conditions
Definition: L1GtTriggerMenuFwd.h:28
DEFINE_FWK_MODULE
#define DEFINE_FWK_MODULE(type)
Definition: MakerMacros.h:17
AlgorithmMap
std::map< std::string, L1GtAlgorithm > AlgorithmMap
map containing the algorithms
Definition: L1GtTriggerMenuFwd.h:31
L1GlobalTriggerReadoutSetup::NumberTechnicalTriggers
static const unsigned int NumberTechnicalTriggers
Definition: L1GlobalTriggerReadoutSetup.h:41
L1GtHwValidation::m_fdlEmulTechDecision
MonitorElement * m_fdlEmulTechDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:257
CItCond
ConditionMap::const_iterator CItCond
iterators through map containing the conditions
Definition: L1GtTriggerMenuFwd.h:34
L1GtHwValidation::m_excludedCondType
std::vector< L1GtConditionType > m_excludedCondType
excluded condition types
Definition: L1GtHwValidation.h:155
MonitorElement::setBinLabel
void setBinLabel(int bin, const std::string &label, int axis=1)
set bin label for x, y or z axis (axis=1, 2, 3 respectively)
Definition: MonitorElement.cc:942
L1GtHwValidation::m_fdlDataEmulAlgoDecisionPrescaled
MonitorElement * m_fdlDataEmulAlgoDecisionPrescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:245
L1GtTriggerMenu::gtTriggerMenuImplementation
const std::string & gtTriggerMenuImplementation() const
Definition: L1GtTriggerMenu.h:106
L1GtHwValidation::m_fdlDataEmulAlgoDecisionUnprescaledAllowed
MonitorElement * m_fdlDataEmulAlgoDecisionUnprescaledAllowed[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:247
L1GtHwValidation::excludedAlgoList
void excludedAlgoList()
exclude from comparison some bits with known disagreement - bit list
Definition: L1GtHwValidation.cc:2545
L1GtHwValidation::bookHistograms
void bookHistograms()
book all histograms for the module
Definition: L1GtHwValidation.cc:1875
L1GtHwValidation::m_fdlDataAlgoDecisionUnprescaledMask_NoMatch
MonitorElement * m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:228
l1GtConditionCategoryEnumToString
std::string l1GtConditionCategoryEnumToString(const L1GtConditionCategory &)
Definition: L1GtDefinitions.cc:248
L1GtHwValidation::m_l1GtEmulEvmInputTag
edm::InputTag m_l1GtEmulEvmInputTag
input tag for the L1 GT emulator EVM record
Definition: L1GtHwValidation.h:130
L1GtHwValidation::m_fdlEmulAlgoDecisionMask
MonitorElement * m_fdlEmulAlgoDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:234
L1GtConditionType
L1GtConditionType
Definition: L1GtDefinitions.h:99
L1GtTriggerMenu::gtConditionMap
const std::vector< ConditionMap > & gtConditionMap() const
get / set / build the condition maps
Definition: L1GtTriggerMenu.h:84
L1GtHwValidation::m_fdlDataAlgoDecisionUnprescaled
MonitorElement * m_fdlDataAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:221
L1GtHwValidation::m_l1GtMenuCacheID
unsigned long long m_l1GtMenuCacheID
Definition: L1GtHwValidation.h:172
L1GtHwValidation::m_l1GtPfTech
const L1GtPrescaleFactors * m_l1GtPfTech
Definition: L1GtHwValidation.h:178
l1GtObjectEnumToString
std::string l1GtObjectEnumToString(const L1GtObject &)
Definition: L1GtObject.cc:74
L1GtHwValidation::m_fdlEmulAlgoDecisionPrescaledMask_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:239
L1GtHwValidation::compareFDL
virtual void compareFDL(const edm::Event &, const edm::EventSetup &, const L1GtFdlWord &, const L1GtFdlWord &, const int)
compare the FDL board
Definition: L1GtHwValidation.cc:624
L1GtfeWord::altNrBxBoard
const cms_uint16_t altNrBxBoard() const
get/set alternative for number of BX per board
Definition: L1GtfeWord.h:187
L1GtHwValidation::matchCondL1GtObject
bool matchCondL1GtObject(const std::vector< L1GtObject > &, const L1GtObject &)
Definition: L1GtHwValidation.cc:2517
AlCaHLTBitMon_QueryRunRegistry.string
string string
Definition: AlCaHLTBitMon_QueryRunRegistry.py:255
L1GtHwValidation::m_excludeAlgoTrigByBit
std::vector< int > m_excludeAlgoTrigByBit
exclude algorithm triggers from comparison data - emulator by algorithm bit number ...
Definition: L1GtHwValidation.h:146
L1GtHwValidation::compareTCS
virtual void compareTCS(const edm::Event &, const edm::EventSetup &, const L1TcsWord &, const L1TcsWord &)
compare the TCS board
Definition: L1GtHwValidation.cc:1578
L1GtHwValidation::m_dbe
DQMStore * m_dbe
internal members
Definition: L1GtHwValidation.h:198
MonitorElement::Fill
void Fill(long long x)
Definition: MonitorElement.h:166
CItAlgo
AlgorithmMap::const_iterator CItAlgo
iterators through map containing the algorithms
Definition: L1GtTriggerMenuFwd.h:38
L1GtHwValidation::m_l1GtTmAlgoCacheID
unsigned long long m_l1GtTmAlgoCacheID
Definition: L1GtHwValidation.h:186
L1GtHwValidation::m_fdlEmulTechDecisionMask
MonitorElement * m_fdlEmulTechDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:258
L1GtFdlWord::bxNr
const cms_uint16_t bxNr() const
get/set BxNr - bunch cross number of the actual bx
Definition: L1GtFdlWord.h:110
L1GtHwValidation::m_fdlDataAlgoDecisionPrescaled
MonitorElement * m_fdlDataAlgoDecisionPrescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:220
L1GtFdlWord::boardId
const cms_uint16_t boardId() const
get/set board ID
Definition: L1GtFdlWord.h:69
L1GtHwValidation::m_fdlDataAlgoDecisionMask_NoMatch
MonitorElement * m_fdlDataAlgoDecisionMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:226
L1GtFdlWord::printGtDecisionWord
void printGtDecisionWord(std::ostream &myCout) const
Definition: L1GtFdlWord.cc:345
L1GtfeWord::recordLength
const cms_uint16_t recordLength() const
get/set record length for alternative 0
Definition: L1GtfeWord.h:104
L1GtFdlWord::eventNr
const cms_uint32_t eventNr() const
get/set event number since last L1 reset generated in FDL
Definition: L1GtFdlWord.h:130
L1GtHwValidation::m_gtfeDataEmul
MonitorElement * m_gtfeDataEmul[NumberOfGtRecords]
histograms
Definition: L1GtHwValidation.h:214
l1GtConditionTypeStringToEnum
L1GtConditionType l1GtConditionTypeStringToEnum(const std::string &)
Definition: L1GtDefinitions.cc:195
L1GtHwValidation::m_fdlDataAlgoDecisionUnprescaled_NoMatch
MonitorElement * m_fdlDataAlgoDecisionUnprescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:225
DecisionWordExtended
std::vector< bool > DecisionWordExtended
Definition: L1GlobalTriggerReadoutSetupFwd.h:38
L1GtHwValidation::beginRun
void beginRun(const edm::Run &run, const edm::EventSetup &c)
Definition: L1GtHwValidation.cc:180
L1GtHwValidation::m_triggerMaskTechTrig
std::vector< unsigned int > m_triggerMaskTechTrig
Definition: L1GtHwValidation.h:192
iEvent
int iEvent
Definition: GenABIO.cc:230
L1GtHwValidation::~L1GtHwValidation
virtual ~L1GtHwValidation()
Definition: L1GtHwValidation.cc:170
L1GtHwValidation::m_fdlDataEmulAlgoDecisionMask
MonitorElement * m_fdlDataEmulAlgoDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:248
l1GtObjectStringToEnum
L1GtObject l1GtObjectStringToEnum(const std::string &)
Definition: L1GtObject.cc:24
L1GtPsbWord::aData
const cms_uint16_t aData(int iA) const
get/set A_DATA_CH_IA
Definition: L1GtPsbWord.cc:228
L1GtHwValidation::m_excludedL1GtObject
std::vector< L1GtObject > m_excludedL1GtObject
excluded L1 GT objects
Definition: L1GtHwValidation.h:158
L1GtHwValidation::m_fdlDataAlgoDecisionPrescaled_NoMatch
MonitorElement * m_fdlDataAlgoDecisionPrescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:224
L1GtTriggerMask::gtTriggerMask
const std::vector< unsigned int > & gtTriggerMask() const
get the trigger mask
Definition: L1GtTriggerMask.h:51
L1GtHwValidation::m_excludeAlgoTrigByName
std::vector< std::string > m_excludeAlgoTrigByName
exclude algorithm triggers from comparison data - emulator by algorithm name
Definition: L1GtHwValidation.h:143
DecisionWord
std::vector< bool > DecisionWord
typedefs
Definition: L1GlobalTriggerReadoutSetupFwd.h:34
L1GtHwValidation::m_excludedAlgorithmsAgreement
MonitorElement * m_excludedAlgorithmsAgreement
Definition: L1GtHwValidation.h:265
L1GtHwValidation::m_l1GtTmAlgo
const L1GtTriggerMask * m_l1GtTmAlgo
trigger masks
Definition: L1GtHwValidation.h:185
L1GtHwValidation::m_l1GtEmulDaqInputTag
edm::InputTag m_l1GtEmulDaqInputTag
input tag for the L1 GT emulator DAQ record
Definition: L1GtHwValidation.h:127
L1GtHwValidation::m_fdlDataEmulTechDecision
MonitorElement * m_fdlDataEmulTechDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:261
L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:240
L1GtFdlWord::bxInEvent
const int bxInEvent() const
get/set bunch cross in the GT event record
Definition: L1GtFdlWord.h:90
L1GtfeWord::totalTriggerNr
const cms_uint32_t totalTriggerNr() const
get/set total number of L1A sent since start of run
Definition: L1GtfeWord.h:211
L1GtFdlWord::printGtDecisionWordExtended
void printGtDecisionWordExtended(std::ostream &myCout) const
Definition: L1GtFdlWord.cc:503
L1GtHwValidation::endRun
void endRun(const edm::Run &run, const edm::EventSetup &c)
Definition: L1GtHwValidation.cc:2716
L1GtConditionCategory
L1GtConditionCategory
condition categories
Definition: L1GtDefinitions.h:128
L1GtHwValidation::compareEvmRecord
virtual void compareEvmRecord(const edm::Event &, const edm::EventSetup &)
L1 GT EVM record comparison.
Definition: L1GtHwValidation.cc:1759
L1GtHwValidation::m_fdlDataTechDecision_Err
MonitorElement * m_fdlDataTechDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:255
L1GtHwValidation::matchCondType
bool matchCondType(const L1GtConditionType &, const L1GtConditionType &)
Definition: L1GtHwValidation.cc:2500
L1GtHwValidation::m_fdlDataAlgoDecision
MonitorElement * m_fdlDataAlgoDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:219
TechnicalTriggerWord
std::vector< bool > TechnicalTriggerWord
technical trigger bits (64 bits)
Definition: L1GlobalTriggerReadoutSetupFwd.h:41
L1GtHwValidation::L1GtHwValidation
L1GtHwValidation(const edm::ParameterSet &)
Definition: L1GtHwValidation.cc:52
L1GlobalTriggerReadoutSetup::NumberPhysTriggers
static const unsigned int NumberPhysTriggers
Definition: L1GlobalTriggerReadoutSetup.h:39
l1GtConditionCategoryStringToEnum
L1GtConditionCategory l1GtConditionCategoryStringToEnum(const std::string &)
Definition: L1GtDefinitions.cc:229
L1GtHwValidation::m_l1GtDataDaqInputToken_
edm::EDGetTokenT< L1GlobalTriggerReadoutRecord > m_l1GtDataDaqInputToken_
Definition: L1GtHwValidation.h:283
DQMStore::setVerbose
void setVerbose(unsigned level)
Definition: DQMStore.cc:631
L1GtHwValidation::TotalBxInEvent
static const int TotalBxInEvent
Definition: L1GtHwValidation.h:208
L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaled
MonitorElement * m_fdlEmulAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:233
L1GtPsbWord::localBxNr
const cms_uint16_t localBxNr() const
get/set local bunch cross number of the actual bx
Definition: L1GtPsbWord.h:178
edm::HandleBase::isValid
bool isValid() const
Definition: HandleBase.h:76
L1GtfeWord::activeBoards
const cms_uint16_t activeBoards() const
get/set boards contributing to EVM respectively DAQ record
Definition: L1GtfeWord.h:163
LogTrace
#define LogTrace(id)
Definition: MessageLogger.h:502
L1GtHwValidation::m_l1GtMenu
const L1GtTriggerMenu * m_l1GtMenu
trigger menu
Definition: L1GtHwValidation.h:171
L1GtHwValidation::m_fdlEmulAlgoDecision_Err
MonitorElement * m_fdlEmulAlgoDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:241
L1GtfeWord::bxNr
const cms_uint16_t bxNr() const
get/set bunch cross number as counted in the GTFE board
Definition: L1GtfeWord.h:122
L1GtHwValidation::m_l1GtEmulEvmInputToken_
edm::EDGetTokenT< L1GlobalTriggerEvmReadoutRecord > m_l1GtEmulEvmInputToken_
Definition: L1GtHwValidation.h:286
L1GtFdlWord::print
void print(std::ostream &myCout) const
pretty print the content of a L1GtFdlWord
Definition: L1GtFdlWord.cc:766
L1GtPsbWord::print
void print(std::ostream &myCout) const
pretty print
Definition: L1GtPsbWord.cc:453
dtDQMClient_cfg.prescaleFactor
tuple prescaleFactor
Definition: dtDQMClient_cfg.py:51
DQMStore::dirExists
bool dirExists(const std::string &path) const
true if directory exists
Definition: DQMStore.cc:732
l1GtConditionTypeEnumToString
std::string l1GtConditionTypeEnumToString(const L1GtConditionType &)
Definition: L1GtDefinitions.cc:215
L1GtfeWord::boardId
const cms_uint16_t boardId() const
get/set board ID
Definition: L1GtfeWord.h:65
L1GtHwValidation::m_l1GtPfAlgoCacheID
unsigned long long m_l1GtPfAlgoCacheID
Definition: L1GtHwValidation.h:176
L1GtPsbWord::eventNr
const cms_uint32_t eventNr() const
get/set event number since last L1 reset generated in PSB
Definition: L1GtPsbWord.h:129
L1GtHwValidation::m_fdlDataTechDecisionMask
MonitorElement * m_fdlDataTechDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:254
L1GtHwValidation::m_l1GtDataDaqInputTag
edm::InputTag m_l1GtDataDaqInputTag
input tag for the L1 GT hardware DAQ record
Definition: L1GtHwValidation.h:121
L1GtHwValidation::m_fdlDataAlgoDecision_NoMatch
MonitorElement * m_fdlDataAlgoDecision_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:223
L1GtHwValidation::m_fdlDataEmul
MonitorElement * m_fdlDataEmul[TotalBxInEvent][NumberOfGtRecords]
FDL (0 for DAQ, 1 for EVM record)
Definition: L1GtHwValidation.h:217
L1GtFdlWord::gtPrescaleFactorIndexAlgo
const cms_uint16_t gtPrescaleFactorIndexAlgo() const
Definition: L1GtFdlWord.h:267
L1GtHwValidation::m_fdlDataEmul_Err
MonitorElement * m_fdlDataEmul_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:250
L1GtPrescaleFactors::gtPrescaleFactors
const std::vector< std::vector< int > > & gtPrescaleFactors() const
get the prescale factors by reference
Definition: L1GtPrescaleFactors.h:49
L1GtHwValidation::m_l1GtEmulDaqInputToken_
edm::EDGetTokenT< L1GlobalTriggerReadoutRecord > m_l1GtEmulDaqInputToken_
Definition: L1GtHwValidation.h:284
L1GtHwValidation::m_excludedCondCategory
std::vector< L1GtConditionCategory > m_excludedCondCategory
excluded condition categories
Definition: L1GtHwValidation.h:152
L1GtHwValidation::m_myCoutStream
std::ostringstream m_myCoutStream
Definition: L1GtHwValidation.h:162
L1GtPsbWord::NumberBData
static const int NumberBData
Definition: L1GtPsbWord.h:35
L1GtHwValidation::beginJob
virtual void beginJob()
Definition: L1GtHwValidation.cc:177
L1GtHwValidation::m_nrDataEventError
int m_nrDataEventError
counters
Definition: L1GtHwValidation.h:165
edm::EventSetup::get
const T & get() const
Definition: EventSetup.h:55
edm::ESHandle::product
T const * product() const
Definition: ESHandle.h:62
L1GtHwValidation::m_fdlEmulAlgoDecisionMask_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:238
L1GtPsbWord::bxInEvent
const int bxInEvent() const
get/set bunch cross in the GT event record
Definition: L1GtPsbWord.h:87
L1GtFdlWord::gtDecisionWord
const DecisionWord & gtDecisionWord() const
get/set/print algorithms bits (decision word)
Definition: L1GtFdlWord.h:171
L1GtHwValidation::m_l1GtTmTechCacheID
unsigned long long m_l1GtTmTechCacheID
Definition: L1GtHwValidation.h:189
L1GtHwValidation::compareGt_Gct
virtual void compareGt_Gct(const edm::Event &, const edm::EventSetup &)
Definition: L1GtHwValidation.cc:1849
L1GtHwValidation::m_fdlEmulTechDecision_Err
MonitorElement * m_fdlEmulTechDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:259
L1GtPsbWord::NumberAData
static const int NumberAData
Definition: L1GtPsbWord.h:34
L1GtHwValidation::m_l1GctDataInputTag
edm::InputTag m_l1GctDataInputTag
input tag for the L1 GCT hardware record
Definition: L1GtHwValidation.h:133
L1GtHwValidation::m_excludeCondCategTypeObject
std::vector< edm::ParameterSet > m_excludeCondCategTypeObject
Definition: L1GtHwValidation.h:140
L1GtFdlWord::printGtTechnicalTriggerWord
void printGtTechnicalTriggerWord(std::ostream &myCout) const
Definition: L1GtFdlWord.cc:271
L1GtHwValidation::m_fdlDataEmulAlgoDecision_Err
MonitorElement * m_fdlDataEmulAlgoDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:249
L1GtfeWord::setupVersion
const cms_uint32_t setupVersion() const
get/set setup version
Definition: L1GtfeWord.h:140
L1GtTriggerMenu::gtAlgorithmMap
const AlgorithmMap & gtAlgorithmMap() const
get / set the algorithm map (by name)
Definition: L1GtTriggerMenu.h:241
L1GtHwValidation::NumberOfGtRecords
static const int NumberOfGtRecords
Definition: L1GtHwValidation.h:209
L1GtHwValidation::m_fdlDataTechDecision
MonitorElement * m_fdlDataTechDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:253
L1GtHwValidation::m_fdlEmulAlgoDecision
MonitorElement * m_fdlEmulAlgoDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:231
L1GtHwValidation::m_prescaleFactorsTechTrig
const std::vector< std::vector< int > > * m_prescaleFactorsTechTrig
Definition: L1GtHwValidation.h:182
edm::false
volatile std::atomic< bool > shutdown_flag false
Definition: UnixSignalHandlers.cc:22
L1GtHwValidation::m_fdlEmulAlgoDecision_NoMatch
MonitorElement * m_fdlEmulAlgoDecision_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:235
L1GtFdlWord::gtDecisionWordExtended
const DecisionWordExtended & gtDecisionWordExtended() const
get/set extended algorithms bits (extended decision word)
Definition: L1GtFdlWord.h:203
L1GtHwValidation::m_fdlDataEmulTechDecisionMask
MonitorElement * m_fdlDataEmulTechDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:262
L1GtHwValidation::m_fdlDataAlgoDecisionMask
MonitorElement * m_fdlDataAlgoDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:222
L1GtHwValidation::compareDaqRecord
virtual void compareDaqRecord(const edm::Event &, const edm::EventSetup &)
L1 GT DAQ record comparison.
Definition: L1GtHwValidation.cc:1584
L1GtfeWord::recordLength1
const cms_uint16_t recordLength1() const
get/set record length for alternative 1
Definition: L1GtfeWord.h:85
L1GtHwValidation::m_triggerMaskAlgoTrig
std::vector< unsigned int > m_triggerMaskAlgoTrig
Definition: L1GtHwValidation.h:191
L1GtHwValidation::m_excludedAlgoList
std::vector< int > m_excludedAlgoList
Definition: L1GtHwValidation.h:280
L1GtHwValidation::m_fdlDataEmulTechDecision_Err
MonitorElement * m_fdlDataEmulTechDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:263
L1GtHwValidation::m_fdlEmulAlgoDecisionPrescaled_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionPrescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:236
DQMStore::setCurrentFolder
void setCurrentFolder(const std::string &fullpath)
Definition: DQMStore.cc:667
L1GtFdlWord::localBxNr
const cms_uint16_t localBxNr() const
get/set local bunch cross number of the actual bx
Definition: L1GtFdlWord.h:372
L1GtHwValidation::m_l1GtPfAlgo
const L1GtPrescaleFactors * m_l1GtPfAlgo
prescale factors
Definition: L1GtHwValidation.h:175
L1GtHwValidation::m_l1GtDataEvmInputTag
edm::InputTag m_l1GtDataEvmInputTag
input tag for the L1 GT hardware EVM record
Definition: L1GtHwValidation.h:124
edm::Run
Definition: Run.h:41
L1GtFdlWord::finalOR
const cms_uint16_t finalOR() const
get/set &quot;Final OR&quot; bits
Definition: L1GtFdlWord.h:306
L1GtHwValidation::m_l1GtPfTechCacheID
unsigned long long m_l1GtPfTechCacheID
Definition: L1GtHwValidation.h:179
asciidump.at
list at
Definition: asciidump.py:428
L1GtHwValidation::m_fdlEmulAlgoDecisionPrescaled
MonitorElement * m_fdlEmulAlgoDecisionPrescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:232
L1GtHwValidation::excludedAlgo
bool excludedAlgo(const int &) const
exclusion status for algorithm with bit i
Definition: L1GtHwValidation.cc:2701
L1GtHwValidation::m_dirName
std::string m_dirName
directory name for L1Extra plots
Definition: L1GtHwValidation.h:136
L1GtHwValidation::endJob
virtual void endJob()
Definition: L1GtHwValidation.cc:2727
L1GtHwValidation::m_fdlDataEmulAlgoDecisionUnprescaled
MonitorElement * m_fdlDataEmulAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:246
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