Signal Class Reference

#include <FWCore/ServiceRegistry/interface/Signal.h>

Inheritance diagram for Signal:

Public Member Functions
Signal	asgn (Signal)
void	clock (const char *rname)
void	create ()
int	getalwaysn ()
bool	getbool ()
int	getchange ()
int	geth ()
int	getint ()
int	getl ()
rval	getmask ()
int	getnegedge ()
int	getposedge ()
rval	getr ()
rval	getval ()
void	init (int, int, const char *)
void	init (const char *rname)
void	init (Signal *shost, int h, int l, const char *rname)
void	initreg (int, int, const char *)
void	inout (int, int, const char *)
void	inout (const char *rname)
void	input (int, int, const char *)
void	input (const char *rname)
void	makemask ()
Signal	operator! ()
Signal	operator!= (Signal)
Signal	operator% (Signal)
Signal	operator& (Signal)
Signal *	operator& ()
Signal	operator&& (Signal)
Signal	operator() (Signal, Signal)
Signal	operator() (Signal)
Signal	operator* (Signal)
Signal	operator+ (Signal)
Signal	operator++ ()
Signal	operator++ (int)
Signal	operator, (Signal)
Signal	operator- (Signal)
Signal	operator-- ()
Signal	operator-- (int)
Signal	operator/ (Signal)
Signal	operator< (Signal)
Signal	operator<< (Signal)
Signal	operator<= (Signal)
Signal	operator= (Signal)
Signal	operator== (Signal)
Signal	operator> (Signal)
Signal	operator>= (Signal)
Signal	operator>> (Signal)
Signal	operator^ (Signal)
Signal	operator| (Signal)
Signal	operator|| (Signal)
Signal	operator~ ()
void	output (int, int, const char *)
void	output (const char *rname)
void	output (int high, int low, const char *rname, module *parent)
void	output (const char *rname, module *parent)
void	reg (int, int, const char *)
void	reg (const char *rname)
Signal	set (Signal)
void	setalwaysn (int n)
void	setchange (int ch)
void	sethlmask (int high, int low, rval imask)
void	setnegedge (int ch)
void	setposedge (int ch)
void	setprintable (int p)
void	setr (rval rv)
void	setrc (rval rv)
	Signal ()
	Signal (rval)
	Signal (int)
	Signal (unsigned int)
	Signal (const char *)
	Signal (int bits, rval value)
void	wire (int, int, const char *)
void	wire (int, int, const char *, int)
void	wire (const char *rname)

Protected Attributes
int	alwaysn
Signal *	ca1
Signal *	ca2
int	change
int	h
Signal *	host
int	hostl
int	inited
int	l
rval	mask
int	mode
int	nedge
Signal *	outhost
Signal *	outreg
int	pedge
int	printable
rval	r
rval	rc
Signal *	source

Friends
std::ostream &	operator<< (std::ostream &stream, Signal s)
Signal	rand (Signal)
Signal	ror (Signal)
Signal	rxor (Signal)

Detailed Description

Description: A simple implementation of the signal/slot pattern

Usage: This is a simple version of the signal/slot pattern and is used by the Framework. It is safe to call 'emit' from multiple threads simultaneously. Assumptions: -The attached slots have a life-time greater than the last 'emit' call issued from the Signal. -'connect' is not called simultaneously with any other methods of the class.

Definition at line 39 of file vlib.h.

Constructor & Destructor Documentation

Signal::Signal

(

)

Definition at line 43 of file vlib.cc.

References create().

{
    create();
}

Signal::Signal

(

rval

n

)

Definition at line 184 of file vlib.cc.

References create(), init(), inited, mnum, mode, n, r, rc, and Sizeofrval.

{
    create();
    mode = mnum;
#ifdef VGEN
    ostringstream ln;
    ln << dec << n;
    init (8*Sizeofrval - 1, 0, ln.str().c_str());
#else
    init (8*Sizeofrval - 1, 0, "");
#endif
    inited = 0;
    rc = n;
    r = n;
}

Signal::Signal

(

int

n

)

Definition at line 200 of file vlib.cc.

References create(), init(), inited, mnum, mode, n, r, rc, and Sizeofrval.

{
    create();
    mode = mnum;
#ifdef VGEN
    ostringstream ln;
    ln << dec << n;
    init (Sizeofrval * 8 - 1, 0, ln.str().c_str());
#else
    init (Sizeofrval * 8 - 1, 0, "");
#endif
    inited = 0;
    r = (rval)n;
    rc = r;
}

Signal::Signal

(

unsigned int

n

)

Definition at line 216 of file vlib.cc.

References create(), init(), inited, mnum, mode, n, r, rc, and Sizeofrval.

{
    create();
    mode = mnum;
#ifdef VGEN
    ostringstream ln;
    ln << dec << n;
    init (Sizeofrval * 8 - 1, 0, ln.str().c_str());
#else
    init (Sizeofrval * 8 - 1, 0, "");
#endif
    inited = 0;
    r = (rval)n;
    rc = r;
}

Signal::Signal

(

const char *

sval

)

Definition at line 61 of file vlib.cc.

References bits, create(), i, init(), mask, mnum, mode, r, rc, AlCaHLTBitMon_QueryRunRegistry::string, and relativeConstraints::value.

{
    create();
    mode = mnum;
    std::string val = sval;
    int bits;
        unsigned int i;
    char radix;
    rval value = 0;
    int dig;

    sscanf(val.c_str(), "%d'%c", &bits, &radix);
    switch (radix)
    {
    case 'h':
    case 'H': 
//      sscanf (val.c_str(), "%d'%c%x", &bits, &radix, &value);
        for (i = 0; val[i] != 'h' && val[i] != 'H'; ++i);
        for (; i < val.length(); ++i)
        {
            switch (val[i])
            {
            case '0':
            case '1':
            case '2':
            case '3':
            case '4':
            case '5':
            case '6':
            case '7':
            case '8':
            case '9':
                dig = val[i] - '0';
                break;
            case 'a':
            case 'b':
            case 'c':
            case 'd':
            case 'e':
            case 'f':
                dig = val[i] - 'a' + 10;
                break;
            case 'A':
            case 'B':
            case 'C':
            case 'D':
            case 'E':
            case 'F':
                dig = val[i] - 'A' + 10;
                break;
            default: 
                dig = -1;
                break;
            }
            if (dig >= 0)
            {
                value = value << 4;
                value = value | dig;
            }
        }


        break;
    case 'd':
    case 'D': 
        sscanf (val.c_str(), "%d'%c%d", &bits, &radix, reinterpret_cast<int *>(&value));
        break;
    case 'o': 
    case 'O': 
//      sscanf (val.c_str(), "%d'%c%o", &bits, &radix, &value);
        for (i = 0; val[i] != 'o' && val[i] != 'O'; ++i);
        for (; i < val.length(); ++i)
        {
            switch (val[i])
            {
            case '0':
            case '1':
            case '2':
            case '3':
            case '4':
            case '5':
            case '6':
            case '7':
                dig = val[i] - '0';
                break;
            default: 
                dig = -1;
                break;
            }
            if (dig >= 0)
            {
                value = value << 3;
                value = value | dig;
            }
        }

        break;

    case 'b': 
    case 'B': 
        
        for (i = 0; val[i] != 'b' && val[i] != 'B'; ++i);
        for (; i < val.length(); ++i)
        {
            switch (val[i])
            {
            case '0':
                value = value << 1;
                break;
            case '1':
                value = value << 1;
                value = value | 1;
                break;
            }
        }
        break;
    }
    Signal::init(bits - 1, 0, val.c_str());
    rc = value & mask;
    r = rc;

}

Signal::Signal	(	int	bits,
		rval	value
	)

Definition at line 48 of file vlib.cc.

References create(), init(), mask, r, rc, and relativeConstraints::value.

{
    create();
#ifdef VGEN 
    ostringstream sval;
    sval << dec << bits << "'d" << value;
    Signal::init(bits - 1, 0, sval.str().c_str());
#else
    Signal::init(bits - 1, 0, "");
#endif
    r = rc = value & mask;
}

Member Function Documentation

Signal Signal::asgn

(

Signal

other

)

Definition at line 533 of file vlib.cc.

References ca1, ca2, change, gather_cfg::cout, globcontrol::getalwaysn(), getl(), getval(), h, host, hostl, AnalysisDataFormats_SUSYBSMObjects::hr, l, mask, minout, mode, moutput, mergeVDriftHistosByStation::name, nedge, NULL, outhost, outreg, pedge, r, rc, set(), setalwaysn(), globcontrol::setchange(), and edmStreamStallGrapher::t.

Referenced by operator=(), and set().

{
    Signal t;

#ifdef VGEN
    t.name = lb + name + rb + " = " + other.getcatname();
    if (glc.printassign()) std::cout << glc.getmargin() << t.name << ";\n" << flush;    
#endif
    rval hr, portionr, portionmask, otr;
    int shn;

    otr = other.getval() & mask;

    if (otr != r) 
    {
        setalwaysn (glc.getalwaysn());
        glc.setchange(1);
    }

    rc = otr;
    if (host) //  is this a portion of the other register?
    {
        hr = host->rc;
        if (hostl > 0) shn = (hostl - host->getl());
        else shn = (l - host->getl());
        portionr = rc << shn;
        portionmask = mask << shn;
        host->set((hr & (~portionmask)) | portionr);
    }

    if (ca1 != NULL && ca2 != NULL) // is this a concatenation of the two registers?
    {
        ca2->set(other);
        ca1->set(other >> (ca2->h - ca2->l + 1));
    }
    if (outhost != NULL && outhost != this && (mode == moutput || mode == minout)) 
    {
        outhost->set(other);
    }
    if (outreg)  
    {
        outreg->set(other);
    }

    t.h = h;
    t.l = l;
    t.mask = mask;
    t.pedge = pedge;
    t.nedge = nedge;
    t.change = change;
    t.r = rc;
#ifdef VGEN
    glc.setprintassign(1);
#endif
    return t;
}

void Signal::clock

(

const char *

rname

)

Definition at line 677 of file vlib.cc.

References module::AddOutReg(), change, dbgmsg, globcontrol::getparent(), h, host, init(), inited, l, minput, mode, mergeVDriftHistosByStation::name, nedge, NULL, obnames, outhost, outreg, pedge, printable, r, rc, module::setchange(), setr(), and setrc().

{
#ifdef VGEN
    if (lb == "{") glc.AddIO(lb + name + rb);
    else glc.AddIO(name);
#else
#ifdef _VDEBUG
    if (h-l != 0 && inited) // inited is analysed in case the passed parameter is a temp var. Actually, every operator should return temp with the proper mask,h,l inherited from operands
    {
        dbgmsg("Different port length for clock argument: declared [" << 0 << ":" << 0 << "], passed: [" << h << ":" << l <<"]. ");
    }
#endif
#endif
    Signal::init(0, 0, rname);
    h = l = 0;
    mode = minput;
#ifdef VGEN
    obname = obnames[mode];
    ostringstream ln;
    glc.AddParameter(name);
    if (h == l) ln << obname << name << ";\n";
    else ln << obname << "[" << dec << h << ":" << l << "] " << name << ";\n";
    glc.AddDeclarator(ln.str());
    printable = 0;
#else
    outreg = glc.getparent()->AddOutReg((Signal)(*this));
    if (rc != r) 
    {
        change = 1; 
        glc.getparent()->setchange(1);
        if (rc == 1 && r == 0) pedge = 1; else pedge = 0;
        if (rc == 0 && r == 1) nedge = 1; else nedge = 0;
    }
    else change = pedge = nedge = 0;
    outreg->setr(r);
    outreg->setrc(r);
    outhost = host = NULL;
#endif

}

void Signal::create

(

)

Definition at line 25 of file vlib.cc.

References alwaysn, ca1, ca2, change, h, host, hostl, inited, l, mask, mode, mergeVDriftHistosByStation::name, nedge, NULL, outhost, outreg, pedge, printable, r, rc, and Sizeofrval.

Referenced by Signal().

{
#ifdef VGEN
    name = "";
    orname = "";
    obname = "";
    lb = "(";
    rb = ")";
#endif

    outhost = host = outreg = ca1 = ca2 = NULL;
    inited = printable = r = rc = l = pedge = nedge = change = alwaysn = mode = 0;
    h = 8*Sizeofrval - 1;
    mask = (rval)(- 1);
    hostl = -1;

}

int Signal::getalwaysn ( )

inline

Definition at line 78 of file vlib.h.

References alwaysn.

Referenced by getval().

{return alwaysn;};

bool Signal::getbool ( )

inline

Definition at line 70 of file vlib.h.

References getval().

Referenced by module::ifelse().

{return (getval() != 0);};

int Signal::getchange ( )

inline

Definition at line 73 of file vlib.h.

References change.

Referenced by output().

{return change;};

int Signal::geth ( )

inline

Definition at line 64 of file vlib.h.

References h.

Referenced by module::AddOutReg().

{return h;};

int Signal::getint ( )

inline

Definition at line 62 of file vlib.h.

References r.

{return (unsigned int)r;};

int Signal::getl ( )

inline

Definition at line 63 of file vlib.h.

References l.

Referenced by module::AddOutReg(), asgn(), and init().

{return l;};

rval Signal::getmask ( )

inline

Definition at line 65 of file vlib.h.

References mask.

Referenced by input().

{return mask;};

int Signal::getnegedge ( )

inline

Definition at line 72 of file vlib.h.

References nedge.

Referenced by module::negedge(), and output().

{return nedge;};

int Signal::getposedge ( )

inline

Definition at line 71 of file vlib.h.

References pedge.

Referenced by output(), and module::posedge().

{return pedge;};

rval Signal::getr ( )

inline

Definition at line 61 of file vlib.h.

References r.

Referenced by init(), input(), operator<<(), parameter::operator=(), output(), and function::vendfunction().

{return r;};

rval Signal::getval

(

)

Definition at line 481 of file vlib.cc.

References getalwaysn(), globcontrol::getalwaysn(), r, and rc.

Referenced by asgn(), getbool(), operator()(), operator,(), memory::operator[](), rand(), and rxor().

{
    return (getalwaysn() == glc.getalwaysn()) ? rc : r;
}

void Signal::init	(	int	high,
		int	low,
		const char *	rname
	)

Definition at line 239 of file vlib.cc.

References h, inited, l, makemask(), mergeVDriftHistosByStation::name, and source.

Referenced by clock(), parameter::init(), initreg(), inout(), input(), module::negedge(), operator()(), operator,(), operator||(), output(), module::posedge(), rand(), ror(), rxor(), Signal(), and wire().

{
    
#ifdef VGEN
    name = rname;
    orname = rname;
    lb = "";
    rb = "";
#endif
    if (!inited)
    {
        h = high;
        l = low;
        makemask();
        inited = 1;
    }
    source = this;
}

void Signal::init ( const char *  rname )

inline

Definition at line 50 of file vlib.h.

References init().

Referenced by init().

{init(0, 0, rname);};

void Signal::init	(	Signal *	shost,
		int	h,
		int	l,
		const char *	rname
	)

Definition at line 258 of file vlib.cc.

References change, getl(), getr(), h, host, l, makemask(), mask, mergeVDriftHistosByStation::name, nedge, pedge, r, rc, and source.

{
    host = shost; 
#ifdef VGEN
    name = rname;
    orname = rname;
    lb = "";
    rb = "";
#endif
    h = high;
    l = low;
    makemask();
    source = this;
    if (host) 
    {
        rc = (host->getr() >> (l - host->getl())) & mask;
        r = rc;
    }
    change = pedge = nedge = 0;
}

void Signal::initreg	(	int	high,
		int	low,
		const char *	rname
	)

Definition at line 837 of file vlib.cc.

References change, globcontrol::getparent(), init(), mode, mreg, nedge, obnames, pedge, r, rc, and module::setchange().

Referenced by reg(), and memory::reg().

{
    Signal::init(high, low, rname);
    mode = mreg;
#ifdef VGEN
    obname = obnames[mode];
#endif
    change = (r != rc);
    if (change) glc.getparent()->setchange(1);
    pedge = (rc == 1 && r == 0);
    nedge = (rc == 0 && r == 1);
    r = rc;
}

void Signal::inout	(	int	high,
		int	low,
		const char *	rname
	)

Definition at line 788 of file vlib.cc.

References dbgmsg, h, hostl, init(), l, minout, mode, mergeVDriftHistosByStation::name, obnames, and printable.

{
#ifdef VGEN
    if (lb == "{") glc.AddIO(lb + name + rb);
    else glc.AddIO(name);
#else
#ifdef _VDEBUG
    if (h-l != high-low)
    {
        dbgmsg("Different port length for inout argument: declared [" << high << ":" << low << "], passed: [" << h << ":" << l <<"]. ");
    }
#endif
#endif
    hostl = l;
    Signal::init(high, low, rname);
    if (high >= low)
    {
        h = high;
        l = low;
    }
    else
    {
        h = low;
        l = high;
    }
    mode = minout;
#ifdef VGEN
    obname = obnames[mode];
    ostringstream ln;
    glc.AddParameter(name);
    if (h == l) ln << obname << name << ";\n";
    else ln << obname << "[" << dec << h << ":" << l << "] " << name << ";\n";
    glc.AddDeclarator(ln.str());
    printable = 0;
#endif

}

void Signal::inout ( const char *  rname )

inline

Definition at line 136 of file vlib.h.

References inout().

Referenced by inout().

{inout(0, 0, rname);};

void Signal::input	(	int	high,
		int	low,
		const char *	rname
	)

Definition at line 625 of file vlib.cc.

References module::AddOutReg(), change, dbgmsg, getmask(), globcontrol::getparent(), getr(), h, host, init(), inited, l, minput, mode, mergeVDriftHistosByStation::name, nedge, NULL, obnames, outhost, outreg, pedge, printable, r, module::setchange(), setr(), and setrc().

{
#ifdef VGEN
    if (lb == "{") glc.AddIO(lb + name + rb);
    else glc.AddIO(name);
#else
#ifdef _VDEBUG
    if (h-l != high-low && inited) // inited is analysed in case the passed parameter is a temp var. Actually, every operator should return temp with the proper mask,h,l inherited from operands
    {
        dbgmsg("Different port length for input argument: declared [" << high << ":" << low << "], passed: [" << h << ":" << l <<"]. ");
    }
#endif
#endif
    Signal::init(high, low, rname);
    if (high >= low)
    {
        h = high;
        l = low;
    }
    else
    {
        h = low;
        l = high;
    }
    mode = minput;
#ifdef VGEN
    obname = obnames[mode];
    ostringstream ln;
    glc.AddParameter(name);
    if (h == l) ln << obname << name << ";\n";
    else ln << obname << "[" << dec << h << ":" << l << "] " << name << ";\n";
    glc.AddDeclarator(ln.str());
    printable = 0;
#else
    outreg = glc.getparent()->AddOutReg((Signal)(*this));
    r = r & outreg->getmask();
    if (outreg->getr() != r) 
    {
        change = 1; 
        glc.getparent()->setchange(1);
        if (r == 1 && outreg->getr() == 0) pedge = 1; else pedge = 0;
        if (r == 0 && outreg->getr() == 1) nedge = 1; else nedge = 0;
    }
    else change = pedge = nedge = 0;
    outreg->setr(r);
    outreg->setrc(r);
    outhost = host = NULL;
#endif

}

void Signal::input ( const char *  rname )

inline

Definition at line 127 of file vlib.h.

References input().

Referenced by input().

{input(0, 0, rname);};

void Signal::makemask

(

)

Definition at line 232 of file vlib.cc.

References h, l, and mask.

Referenced by init().

{
    mask = (1LL << (h - l + 1)) - 1LL;
    if (mask == 0LL) mask = ~mask;
}

Signal Signal::operator!

(

)

Signal Signal::operator!=

(

Signal

)

Signal Signal::operator%

(

Signal

)

Signal Signal::operator&

(

Signal

)

Signal * Signal::operator&

(

)

Definition at line 316 of file vlib.cc.

{
#ifdef VGEN
    printable = 0;
#endif
    return this;
}

Signal Signal::operator&&

(

Signal

)

Signal Signal::operator()	(	Signal	hn,
		Signal	ln
	)

Definition at line 593 of file vlib.cc.

References getval(), init(), l, mask, mergeVDriftHistosByStation::name, printable, r, rc, and edmStreamStallGrapher::t.

{
    Signal t;
#ifdef VGEN
    string bname;
    if (hn.getname().compare(ln.getname()) != 0) bname = name + "[" + hn.getname() + ":" + ln.getname() + "]";
    else bname = name + "[" + hn.getname() + "]";
    hn.printable = ln.printable = 0;
    t.init(this, 0, 0, bname.c_str());
#else
    t.init(this, (unsigned)hn.getval(), (unsigned)ln.getval(), "");
#endif
    t.rc = (getval() >> (t.l - l)) & t.mask;
    t.r = t.rc;
    return t;
}

Signal Signal::operator()

(

Signal

n

)

Definition at line 610 of file vlib.cc.

References n.

{
    return (*this)(n, n);
}

Signal Signal::operator*

(

Signal

)

Signal Signal::operator+

(

Signal

)

Signal Signal::operator++ ( void  )

inline

Definition at line 109 of file vlib.h.

{return *this = *this + 1;};

Signal Signal::operator++ ( int  )

inline

Definition at line 111 of file vlib.h.

{return *this = *this + 1;};        // postfix operators require some work (different names for operations and assignment printing?)

Signal Signal::operator,

(

Signal

arg

)

Definition at line 379 of file vlib.cc.

References ca1, ca2, getval(), h, init(), l, mask, mergeVDriftHistosByStation::name, printable, r, source, and edmStreamStallGrapher::t.

{
    Signal t;
#ifdef VGEN
    t.name = name + ", " + arg.name;
    t.lb = "{";
    t.rb = "}";
    printable = arg.printable = 0;
#else
    t.ca1 = this;
    t.ca2 = arg.source;
    t.init(h - l + arg.h - arg.l + 1, 0, "");
#endif
    t.r = (((getval() << (arg.h - arg.l + 1)) & (~(arg.mask))) | arg.getval()) & t.mask;
    return t;
}

Signal Signal::operator-

(

Signal

)

Signal Signal::operator-- ( )

inline

Definition at line 110 of file vlib.h.

{return *this = *this - 1;};

Signal Signal::operator-- ( int  )

inline

Definition at line 112 of file vlib.h.

{return *this = *this - 1;};

Signal Signal::operator/

(

Signal

)

Signal Signal::operator<

(

Signal

)

Signal Signal::operator<<

(

Signal

)

Signal Signal::operator<=

(

Signal

)

Signal Signal::operator=

(

Signal

other

)

Definition at line 486 of file vlib.cc.

References asgn(), dbgmsg, globcontrol::getalwaysn(), minout, minput, mode, moutput, mreg, mwire, NULL, and outreg.

{

#ifndef VGEN
#ifdef _VDEBUG
    switch (mode)
    {
        case moutput:
            if (glc.getalwaysn() == -1 && outreg != NULL) 
                dbgmsg("Assigning output-reg outside always block.");
            if (glc.getalwaysn() != -1 && outreg == NULL) 
                dbgmsg("Assigning non-reg output inside always block.");
            break;

        case minout:
            if (glc.getalwaysn() != -1) 
                dbgmsg("Assigning inout inside always block.");
            break;

        case minput:
            dbgmsg("Assigning to input is not allowed.");
            return other;

        case mreg:
            if (glc.getalwaysn() == -1) 
                dbgmsg("Assigning reg outside always block.");
            break;

        case mwire:
            if (glc.getalwaysn() != -1) 
                dbgmsg("Assigning wire inside always block.");
            break;
    }
#endif
#endif
    return asgn(other);

}

Signal Signal::operator==

(

Signal

)

Signal Signal::operator>

(

Signal

)

Signal Signal::operator>=

(

Signal

)

Signal Signal::operator>>

(

Signal

)

Signal Signal::operator^

(

Signal

)

Signal Signal::operator|

(

Signal

)

Signal Signal::operator||

(

Signal

arg

)

Definition at line 362 of file vlib.cc.

References change, h, init(), ConfigFiles::l, mask, mergeVDriftHistosByStation::name, printable, r, and edmStreamStallGrapher::t.

{
    Signal t;
#ifdef VGEN
    t.name = lb + name + rb + " || " + arg.lb + arg.name + arg.rb;
    t.orname = orname + " or " + arg.orname;
    printable = arg.printable = 0;
#else
    int ln  = h - l; 
    int aln = arg.h - arg.l; 
    t.init((ln > aln) ? ln : aln, 0, ""); 
#endif
    t.r = t.mask & (getval() || arg.getval());
    t.change = change || arg.change;
    return t;
}

Signal Signal::operator~

(

)

void Signal::output	(	int	high,
		int	low,
		const char *	rname
	)

Definition at line 722 of file vlib.cc.

References dbgmsg, h, hostl, init(), l, mode, moutput, mreg, mergeVDriftHistosByStation::name, obnames, and printable.

Referenced by output().

{
#ifdef VGEN
    if (lb == "{") glc.AddIO(lb + name + rb);
    else glc.AddIO(name);
#else
#ifdef _VDEBUG
    if (h-l != high-low)
    {
        dbgmsg("Different port length for output argument: declared [" << high << ":" << low << "], passed: [" << h << ":" << l <<"]. ");
    }
    if (mode == mreg)
    {
        dbgmsg("Using reg as output.");
    }
#endif
#endif
    hostl = l;
    Signal::init(high, low, rname);
    if (high >= low)
    {
        h = high;
        l = low;
    }
    else
    {
        h = low;
        l = high;
    }
    mode = moutput;
#ifdef VGEN
    obname = obnames[mode];
    ostringstream ln;
    glc.AddParameter(name);
    if (h == l) ln << obname << name << ";\n";
    else ln << obname << "[" << dec << h << ":" << l << "] " << name << ";\n";
    glc.AddDeclarator(ln.str());
    printable = 0;
#endif

}

void Signal::output ( const char *  rname )

inline

Definition at line 131 of file vlib.h.

References output().

Referenced by output().

{output(0, 0, rname);};

void Signal::output	(	int	high,
		int	low,
		const char *	rname,
		module *	parent
	)

Definition at line 764 of file vlib.cc.

References module::AddOutReg(), getchange(), getnegedge(), getposedge(), getr(), h, l, mergeVDriftHistosByStation::name, output(), outreg, setchange(), setnegedge(), setposedge(), and setr().

{
    output(high, low, rname);
#ifdef VGEN
    ostringstream ln;
    if (h == l) ln << "reg    " << name << ";\n";
    else ln << "reg    [" << dec << h << ":" << l << "] " << name << ";\n";
    glc.AddDeclarator(ln.str());
#else
    outreg = parent->AddOutReg((Signal)(*this));
    setr(outreg->getr());
    setchange(outreg->getchange());
    setposedge(outreg->getposedge());
    setnegedge(outreg->getnegedge());
#endif
}

void Signal::output	(	const char *	rname,
		module *	parent
	)

Definition at line 781 of file vlib.cc.

References output().

{
    output(0, 0, rname, parent);
}

void Signal::reg	(	int	high,
		int	low,
		const char *	rname
	)

Definition at line 828 of file vlib.cc.

References gather_cfg::cout, h, initreg(), l, and mergeVDriftHistosByStation::name.

Referenced by module::AddOutReg().

{
    initreg(high, low, rname);
#ifdef VGEN
    if (h == l) cout << glc.getmargin() << obname << name << ";\n" << flush;
    else std::cout << glc.getmargin() << obname << "[" << dec << h << ":" << l << "] "<< name << ";\n" << flush;
#endif
}

void Signal::reg ( const char *  rname )

inline

Definition at line 140 of file vlib.h.

References reg().

Referenced by reg().

{reg(0, 0, rname);};

Signal Signal::set

(

Signal

other

)

Definition at line 525 of file vlib.cc.

References asgn().

Referenced by asgn(), and betterConfigParser.BetterConfigParser::getGeneral().

{
#ifdef VGEN
    glc.setprintassign(0);
#endif
    return asgn(other);
}

void Signal::setalwaysn ( int  n )

inline

Definition at line 77 of file vlib.h.

References alwaysn.

Referenced by asgn().

{alwaysn = (n == -1) ? 0 : n;};

void Signal::setchange ( int  ch )

inline

Definition at line 74 of file vlib.h.

References change.

Referenced by module::negedge(), output(), and module::posedge().

{change = ch;};

void Signal::sethlmask ( int  high, int  low, rval  imask  )

inline

Definition at line 68 of file vlib.h.

References h, l, and mask.

Referenced by function::vendfunction().

{h = high; l = low; mask = imask;};

void Signal::setnegedge ( int  ch )

inline

Definition at line 76 of file vlib.h.

References nedge.

Referenced by output().

{nedge = ch;};

void Signal::setposedge ( int  ch )

inline

Definition at line 75 of file vlib.h.

References pedge.

Referenced by output().

{pedge = ch;};

void Signal::setprintable ( int  p )

inline

Definition at line 79 of file vlib.h.

References AlCaHLTBitMon_ParallelJobs::p, and printable.

Referenced by operator<<().

{printable = p;};

void Signal::setr ( rval  rv )

inline

Definition at line 66 of file vlib.h.

References mask, and r.

Referenced by module::AddOutReg(), clock(), input(), output(), memory::reg(), and function::vendfunction().

{r = rv & mask;};

void Signal::setrc ( rval  rv )

inline

Definition at line 67 of file vlib.h.

References mask, and rc.

Referenced by clock(), and input().

{rc = rv & mask;};

void Signal::wire	(	int	high,
		int	low,
		const char *	rname
	)

Definition at line 885 of file vlib.cc.

References change, gather_cfg::cout, globcontrol::getparent(), h, init(), l, mode, mwire, mergeVDriftHistosByStation::name, nedge, obnames, outhost, pedge, r, rc, and module::setchange().

Referenced by wire().

{
    Signal::init(high, low, rname);
    mode = mwire;
    outhost = this;
    change = (r != rc);
    if (change && glc.getparent()) glc.getparent()->setchange(1);
    pedge = (rc == 1 && r == 0);
    nedge = (rc == 0 && r == 1);
    r = rc;
#ifdef VGEN
    obname = obnames[mode];
    if (h == l) cout << glc.getmargin() << obname << name << ";\n" << flush;
    else std::cout << glc.getmargin() << obname << "[" << dec << h << ":" << l << "] "<< name << ";\n" << flush;
#endif
}

void Signal::wire	(	int	high,
		int	low,
		const char *	rname,
		int	i
	)

Definition at line 902 of file vlib.cc.

References i, and wire().

{
#ifdef VGEN
    ostringstream instnamestream;
    instnamestream << rname << dec << i;
//  init(high, low, instnamestream.str().c_str());
    wire(high, low, instnamestream.str().c_str());
#else
    wire(high, low, rname);
#endif
}

void Signal::wire ( const char *  rname )

inline

Definition at line 144 of file vlib.h.

References wire().

Referenced by wire().

{wire(0, 0, rname);};

Friends And Related Function Documentation

std::ostream& operator<< ( std::ostream &  stream, Signal  s  )

friend

Definition at line 616 of file vlib.cc.

{
    stream << s.getr();
    s.setprintable(0);
    return stream;
}

Signal rand ( Signal  arg )

friend

Definition at line 442 of file vlib.cc.

{
    Signal t;
    rval tr;
#ifdef VGEN
    t.name = "&" + arg.lb + arg.name + arg.rb;
    arg.printable = 0;
#else
    t.init("");
#endif
    tr = (arg.getval()) & arg.mask;
    t.r = (tr == arg.mask) ? 1 : 0;
    return t;
}

Signal ror ( Signal  arg )

friend

Definition at line 427 of file vlib.cc.

{
    Signal t;
    rval tr;
#ifdef VGEN
    t.name = "|" + arg.lb + arg.name + arg.rb;
    arg.printable = 0;
#else
    t.init("");
#endif
    tr = (arg.getval()) & arg.mask;
    t.r = (tr != 0) ? 1 : 0;
    return t;
}

Signal rxor ( Signal  arg )

friend

Definition at line 457 of file vlib.cc.

{
    Signal t;
    rval tr;
    int i;
#ifdef VGEN
    t.name = "^" + arg.lb + arg.name + arg.rb;
    arg.printable = 0;
#else
    t.init("");
#endif
    tr = (arg.getval()) & arg.mask;
    t.r = 0;
    for (i = 0; i < arg.h-arg.l+1; ++i) 
    {
        t.r = ((tr & 1) != 0) ? !t.r : t.r;
        tr = tr >> 1;
    }
    t.r = t.r & 1;
    return t;
}

Member Data Documentation

int Signal::alwaysn

protected

Definition at line 167 of file vlib.h.

Referenced by create(), getalwaysn(), and setalwaysn().

Signal* Signal::ca1

protected

Definition at line 161 of file vlib.h.

Referenced by asgn(), create(), and operator,().

Signal* Signal::ca2

protected

Definition at line 162 of file vlib.h.

Referenced by asgn(), create(), and operator,().

int Signal::change

protected

Definition at line 163 of file vlib.h.

Referenced by asgn(), clock(), create(), getchange(), init(), parameter::init(), initreg(), input(), operator||(), setchange(), and wire().

int Signal::h

protected

Definition at line 150 of file vlib.h.

Referenced by asgn(), clock(), create(), geth(), init(), inout(), input(), makemask(), operator,(), output(), reg(), rxor(), sethlmask(), and wire().

Signal* Signal::host

protected

Definition at line 160 of file vlib.h.

Referenced by asgn(), clock(), create(), init(), and input().

int Signal::hostl

protected

Definition at line 151 of file vlib.h.

Referenced by asgn(), create(), inout(), and output().

int Signal::inited

protected

Definition at line 168 of file vlib.h.

Referenced by clock(), create(), init(), input(), and Signal().

int Signal::l

protected

Definition at line 150 of file vlib.h.

Referenced by asgn(), clock(), create(), getl(), init(), inout(), input(), makemask(), operator()(), operator,(), output(), reg(), rxor(), sethlmask(), and wire().

rval Signal::mask

protected

Definition at line 152 of file vlib.h.

Referenced by asgn(), create(), getmask(), init(), makemask(), operator()(), operator,(), operator||(), rand(), rxor(), sethlmask(), setr(), setrc(), and Signal().

int Signal::mode

protected

Definition at line 170 of file vlib.h.

Referenced by asgn(), clock(), create(), initreg(), inout(), input(), operator=(), output(), Signal(), and wire().

int Signal::nedge

protected

Definition at line 163 of file vlib.h.

Referenced by asgn(), clock(), create(), getnegedge(), init(), parameter::init(), initreg(), input(), setnegedge(), and wire().

Signal* Signal::outhost

protected

Definition at line 165 of file vlib.h.

Referenced by asgn(), clock(), create(), input(), and wire().

Signal* Signal::outreg

protected

Definition at line 166 of file vlib.h.

Referenced by asgn(), clock(), create(), input(), operator=(), and output().

int Signal::pedge

protected

Definition at line 163 of file vlib.h.

Referenced by asgn(), clock(), create(), getposedge(), init(), parameter::init(), initreg(), input(), setposedge(), and wire().

int Signal::printable

protected

Definition at line 169 of file vlib.h.

Referenced by clock(), create(), inout(), input(), operator()(), operator,(), operator||(), output(), rand(), ror(), rxor(), and setprintable().

rval Signal::r

protected

Definition at line 144 of file vlib.h.

Referenced by asgn(), clock(), create(), getint(), getr(), getval(), init(), initreg(), input(), parameter::operator int(), operator()(), operator,(), parameter::operator=(), operator||(), rand(), ror(), rxor(), setr(), Signal(), and wire().

rval Signal::rc

protected

Definition at line 149 of file vlib.h.

Referenced by asgn(), clock(), create(), getval(), init(), initreg(), operator()(), setrc(), Signal(), and wire().

Signal* Signal::source

protected

Definition at line 164 of file vlib.h.

Referenced by init(), and operator,().