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SiStripFecCabling Class Reference

#include <SiStripFecCabling.h>

Public Member Functions

void addDevices (const FedChannelConnection &conn)
 
void buildFecCabling (const SiStripFedCabling &)
 
void connections (std::vector< FedChannelConnection > &) const
 
NumberOfDevices countDevices () const
 
const std::vector
< SiStripFecCrate > & 
crates () const
 
void dcuId (const FedChannelConnection &conn)
 
void detId (const FedChannelConnection &conn)
 
const std::vector< SiStripFec > & fecs () const
 
const SiStripModulemodule (const FedChannelConnection &conn) const
 
const SiStripModulemodule (const uint32_t &dcu_id) const
 
void nApvPairs (const FedChannelConnection &conn)
 
void print (std::stringstream &) const
 
 SiStripFecCabling (const SiStripFedCabling &)
 
 SiStripFecCabling ()
 
void terse (std::stringstream &) const
 
 ~SiStripFecCabling ()
 

Private Attributes

std::vector< SiStripFecCratecrates_
 

Detailed Description

Definition at line 24 of file SiStripFecCabling.h.

Constructor & Destructor Documentation

SiStripFecCabling::SiStripFecCabling ( const SiStripFedCabling fed_cabling)

Definition at line 13 of file SiStripFecCabling.cc.

References buildFecCabling(), crates_, LogTrace, and sistrip::mlCabling_.

14  : crates_()
15 {
17  << "[SiStripFecCabling::" << __func__ << "]"
18  << " Constructing object...";
19  crates_.reserve(4);
20  buildFecCabling( fed_cabling );
21 }
std::vector< SiStripFecCrate > crates_
static const char mlCabling_[]
void buildFecCabling(const SiStripFedCabling &)
#define LogTrace(id)
SiStripFecCabling::SiStripFecCabling ( )
inline

Definition at line 33 of file SiStripFecCabling.h.

33 {;}
SiStripFecCabling::~SiStripFecCabling ( )
inline

Definition at line 35 of file SiStripFecCabling.h.

35 {;} //@@ needs implementation!!

Member Function Documentation

void SiStripFecCabling::addDevices ( const FedChannelConnection conn)

Definition at line 63 of file SiStripFecCabling.cc.

References SiStripFecCrate::addDevices(), crates(), crates_, end, and FedChannelConnection::fecCrate().

Referenced by buildFecCabling(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDetIds(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices(), SiStripFedCablingBuilderFromDb::buildFecCablingFromFedConnections(), and SiStripFedCablingFakeESSource::make().

63  {
64  std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin();
65  while ( icrate != crates().end() && (*icrate).fecCrate() != conn.fecCrate() ) { icrate++; }
66  if ( icrate == crates().end() ) {
67  crates_.push_back( SiStripFecCrate( conn ) );
68  } else {
69  const_cast<SiStripFecCrate&>(*icrate).addDevices( conn );
70  }
71 }
const uint16_t & fecCrate() const
std::vector< SiStripFecCrate > crates_
const std::vector< SiStripFecCrate > & crates() const
#define end
Definition: vmac.h:37
void addDevices(const FedChannelConnection &conn)
void SiStripFecCabling::buildFecCabling ( const SiStripFedCabling fed_cabling)

Definition at line 25 of file SiStripFecCabling.cc.

References addDevices(), begin, crates(), SiStripFedCabling::fedConnections(), SiStripFedCabling::fedIds(), sistrip::invalid_, LogTrace, and sistrip::mlCabling_.

Referenced by SiStripFedCablingBuilderFromDb::getFecCabling(), and SiStripFecCabling().

25  {
27  << "[SiStripFecCabling::" << __func__ << "]"
28  << " Building FEC cabling...";
29 
30  // Retrieve and iterate through FED ids
31  auto feds = fed_cabling.fedIds();
32  for ( auto ifed = feds.begin(); ifed != feds.end(); ifed++ ) {
33 
34  // Retrieve and iterate through FED channel connections
35  auto conns = fed_cabling.fedConnections( *ifed );
36  for ( auto iconn = conns.begin(); iconn != conns.end(); iconn++ ) {
37 
38  // Check that FED id is not invalid and add devices
39  if ( iconn->fedId() != sistrip::invalid_ ) { addDevices( *iconn ); }
40 
41  }
42  }
43 
44  // Consistency checks
45  for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
46  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
47  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
48  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
49  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
50  //@@ need consistency checks here!
51  }
52  }
53  }
54  }
55  }
57  << "[SiStripFecCabling::" << __func__ << "]"
58  << " Finished building FEC cabling";
59 }
void addDevices(const FedChannelConnection &conn)
const std::vector< SiStripFecCrate > & crates() const
static const char mlCabling_[]
FedsConstIterRange fedIds() const
#define LogTrace(id)
static const uint16_t invalid_
Definition: Constants.h:16
ConnsConstIterRange fedConnections(uint16_t fed_id) const
#define begin
Definition: vmac.h:30
void SiStripFecCabling::connections ( std::vector< FedChannelConnection > &  conns) const

Definition at line 75 of file SiStripFecCabling.cc.

References begin, crates(), first, LogTrace, sistrip::mlCabling_, and edm::second().

Referenced by SiStripFedCablingBuilderFromDb::getFedCabling(), and SiStripFedCablingFakeESSource::make().

75  {
77  << "[SiStripFecCabling::" << __func__ << "]"
78  << " Building vector of FedChannelConnection objects...";
79  conns.clear();
80  for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
81  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
82  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
83  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
84  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
85  for ( uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++ ) {
86  conns.push_back( FedChannelConnection( icrate->fecCrate(),
87  ifec->fecSlot(),
88  iring->fecRing(),
89  iccu->ccuAddr(),
90  imod->ccuChan(),
91  imod->activeApvPair( imod->lldChannel(ipair) ).first,
92  imod->activeApvPair( imod->lldChannel(ipair) ).second,
93  imod->dcuId(),
94  imod->detId(),
95  imod->nApvPairs(),
96  imod->fedCh(ipair).fedId_,
97  imod->fedCh(ipair).fedCh_,
98  imod->length(),
99  imod->dcu(),
100  imod->pll(),
101  imod->mux(),
102  imod->lld() ) );
103  uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
104  uint16_t fed_slot = imod->fedCh(ipair).fedSlot_;
105  conns.back().fedCrate( fed_crate );
106  conns.back().fedSlot( fed_slot );
107  }
108  }
109  }
110  }
111  }
112  }
113 }
const std::vector< SiStripFecCrate > & crates() const
U second(std::pair< T, U > const &p)
static const char mlCabling_[]
Class containning control, module, detector and connection information, at the level of a FED channel...
bool first
Definition: L1TdeRCT.cc:75
#define LogTrace(id)
#define begin
Definition: vmac.h:30
NumberOfDevices SiStripFecCabling::countDevices ( ) const

Definition at line 183 of file SiStripFecCabling.cc.

References begin, crates(), spr::find(), NumberOfDevices::nApvPairs0_, NumberOfDevices::nApvPairs1_, NumberOfDevices::nApvPairs2_, NumberOfDevices::nApvPairs3_, NumberOfDevices::nApvPairs_, NumberOfDevices::nApvPairsX_, NumberOfDevices::nApvs_, NumberOfDevices::nCcuAddrs_, NumberOfDevices::nCcuChans_, NumberOfDevices::nDcuIds_, NumberOfDevices::nDcus_, NumberOfDevices::nDetIds_, NumberOfDevices::nFecCrates_, NumberOfDevices::nFecRings_, NumberOfDevices::nFecSlots_, NumberOfDevices::nFedChans_, NumberOfDevices::nFedCrates_, NumberOfDevices::nFedIds_, NumberOfDevices::nFedSlots_, NumberOfDevices::nLlds_, NumberOfDevices::nMuxes_, and NumberOfDevices::nPlls_.

Referenced by SiStripFedCablingBuilderFromDb::buildFecCabling(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices(), and SiStripFedCablingFakeESSource::make().

183  {
184 
185  NumberOfDevices num_of_devices; // simple container class used for counting
186 
187  std::vector<uint16_t> fed_crates;
188  std::vector<uint16_t> fed_slots;
189  std::vector<uint16_t> fed_ids;
190  for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
191  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
192  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
193  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
194  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
195 
196  // APVs
197  if ( imod->activeApv(32) ) { num_of_devices.nApvs_++; }
198  if ( imod->activeApv(33) ) { num_of_devices.nApvs_++; }
199  if ( imod->activeApv(34) ) { num_of_devices.nApvs_++; }
200  if ( imod->activeApv(35) ) { num_of_devices.nApvs_++; }
201  if ( imod->activeApv(36) ) { num_of_devices.nApvs_++; }
202  if ( imod->activeApv(37) ) { num_of_devices.nApvs_++; }
203  if ( imod->dcuId() ) { num_of_devices.nDcuIds_++; }
204  if ( imod->detId() ) { num_of_devices.nDetIds_++; }
205 
206  // APV pairs
207  num_of_devices.nApvPairs_ += imod->nApvPairs();
208  if ( imod->nApvPairs() == 0 ) { num_of_devices.nApvPairs0_++; }
209  else if ( imod->nApvPairs() == 1 ) { num_of_devices.nApvPairs1_++; }
210  else if ( imod->nApvPairs() == 2 ) { num_of_devices.nApvPairs2_++; }
211  else if ( imod->nApvPairs() == 3 ) { num_of_devices.nApvPairs3_++; }
212  else { num_of_devices.nApvPairsX_++; }
213 
214  // FED crates, slots, ids, channels
215  for ( uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++ ) {
216 
217  uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
218  uint16_t fed_slot = imod->fedCh(ipair).fedSlot_;
219  uint16_t fed_id = imod->fedCh(ipair).fedId_;
220 
221  if ( fed_id ) {
222 
223  num_of_devices.nFedChans_++;
224 
225  std::vector<uint16_t>::iterator icrate = find( fed_crates.begin(), fed_crates.end(), fed_crate );
226  if ( icrate == fed_crates.end() ) {
227  num_of_devices.nFedCrates_++;
228  fed_crates.push_back(fed_crate);
229  }
230 
231  std::vector<uint16_t>::iterator islot = find( fed_slots.begin(), fed_slots.end(), fed_slot );
232  if ( islot == fed_slots.end() ) {
233  num_of_devices.nFedSlots_++;
234  fed_slots.push_back(fed_slot);
235  }
236 
237  std::vector<uint16_t>::iterator ifed = find( fed_ids.begin(), fed_ids.end(), fed_id );
238  if ( ifed == fed_ids.end() ) {
239  num_of_devices.nFedIds_++;
240  fed_ids.push_back(fed_id);
241  }
242 
243  }
244 
245  }
246 
247  // FE devices
248  if ( imod->dcu() ) { num_of_devices.nDcus_++; }
249  if ( imod->mux() ) { num_of_devices.nMuxes_++; }
250  if ( imod->pll() ) { num_of_devices.nPlls_++; }
251  if ( imod->lld() ) { num_of_devices.nLlds_++; }
252 
253  // FE modules
254  num_of_devices.nCcuChans_++;
255  }
256  num_of_devices.nCcuAddrs_++;
257  }
258  num_of_devices.nFecRings_++;
259  }
260  num_of_devices.nFecSlots_++;
261  }
262  num_of_devices.nFecCrates_++;
263  }
264 
265  return num_of_devices;
266 
267 }
uint32_t nFecCrates_
const std::vector< SiStripFecCrate > & crates() const
void find(edm::Handle< EcalRecHitCollection > &hits, DetId thisDet, std::vector< EcalRecHitCollection::const_iterator > &hit, bool debug=false)
Definition: FindCaloHit.cc:7
uint32_t nApvPairs3_
uint32_t nApvPairsX_
uint32_t nApvPairs0_
Simple container class for counting devices.
uint32_t nApvPairs2_
#define begin
Definition: vmac.h:30
uint32_t nApvPairs1_
uint32_t nFedCrates_
const std::vector< SiStripFecCrate > & SiStripFecCabling::crates ( ) const
inline
void SiStripFecCabling::dcuId ( const FedChannelConnection conn)
inline

Definition at line 87 of file SiStripFecCabling.h.

References FedChannelConnection::dcuId(), and module().

Referenced by SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices().

87  {
88  const_cast<SiStripModule&>(module(conn)).dcuId(conn.dcuId());
89 }
Device and connection information at the level of a front-end module.
Definition: SiStripModule.h:24
const SiStripModule & module(const FedChannelConnection &conn) const
void dcuId(const FedChannelConnection &conn)
const uint32_t & dcuId() const
void SiStripFecCabling::detId ( const FedChannelConnection conn)
inline

Definition at line 91 of file SiStripFecCabling.h.

References FedChannelConnection::detId(), and module().

91  {
92  const_cast<SiStripModule&>(module(conn)).detId(conn.detId());
93 }
Device and connection information at the level of a front-end module.
Definition: SiStripModule.h:24
const SiStripModule & module(const FedChannelConnection &conn) const
const uint32_t & detId() const
void detId(const FedChannelConnection &conn)
const std::vector< SiStripFec > & SiStripFecCabling::fecs ( ) const
inline

Definition at line 81 of file SiStripFecCabling.h.

References crates_.

81  {
82  const static std::vector<SiStripFec> my_fecs;
83  if ( !crates_.empty() ) { return crates_[0].fecs(); }
84  else { return my_fecs; }
85 }
std::vector< SiStripFecCrate > crates_
const SiStripModule & SiStripFecCabling::module ( const FedChannelConnection conn) const

Definition at line 117 of file SiStripFecCabling.cc.

References FedChannelConnection::ccuAddr(), FedChannelConnection::ccuChan(), crates(), end, FedChannelConnection::fecCrate(), FedChannelConnection::fecRing(), FedChannelConnection::fecSlot(), and sistrip::mlCabling_.

Referenced by dcuId(), detId(), SiStripCommissioningSource::fillCablingHistos(), module(), and nApvPairs().

117  {
118 
119  std::stringstream ss;
120  std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin();
121  while ( icrate != crates().end() && icrate->fecCrate() != conn.fecCrate() ) { icrate++; }
122  if ( icrate != crates().end() ) {
123  std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin();
124  while ( ifec != icrate->fecs().end() && ifec->fecSlot() != conn.fecSlot() ) { ifec++; }
125  if ( ifec != icrate->fecs().end() ) {
126  std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin();
127  while ( iring != ifec->rings().end() && iring->fecRing() != conn.fecRing() ) { iring++; }
128  if ( iring != ifec->rings().end() ) {
129  std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin();
130  while ( iccu != iring->ccus().end() && iccu->ccuAddr() != conn.ccuAddr() ) { iccu++; }
131  if ( iccu != iring->ccus().end() ) {
132  std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin();
133  while ( imod != iccu->modules().end() && imod->ccuChan() != conn.ccuChan() ) { imod++; }
134  if ( imod != iccu->modules().end() ) {
135  return *imod;
136  } else {
137  ss << "[SiStripFecCabling::" << __func__ << "]"
138  << " CCU channel " << conn.ccuChan()
139  << " not found!"; }
140  } else {
141  ss << "[SiStripFecCabling::" << __func__ << "]"
142  << " CCU address " << conn.ccuAddr()
143  << " not found!"; }
144  } else {
145  ss << "[SiStripFecCabling::" << __func__ << "]"
146  << " FEC ring " << conn.fecRing()
147  << " not found!"; }
148  } else {
149  ss << "[SiStripFecCabling::" << __func__ << "]"
150  << " FEC slot " << conn.fecSlot()
151  << " not found!"; }
152  } else {
153  ss << "[SiStripFecCabling::" << __func__ << "]"
154  << " FEC crate " << conn.fecCrate()
155  << " not found!";
156  }
157 
158  if ( !ss.str().empty() ) { edm::LogWarning(mlCabling_) << ss.str(); }
159  static const SiStripModule module{FedChannelConnection{}};
160  return module;
161 }
const uint16_t & fecSlot() const
Device and connection information at the level of a front-end module.
Definition: SiStripModule.h:24
const uint16_t & fecCrate() const
const SiStripModule & module(const FedChannelConnection &conn) const
const std::vector< SiStripFecCrate > & crates() const
static const char mlCabling_[]
const uint16_t & fecRing() const
Class containning control, module, detector and connection information, at the level of a FED channel...
const uint16_t & ccuChan() const
#define end
Definition: vmac.h:37
const uint16_t & ccuAddr() const
Definition: vlib.h:208
const SiStripModule & SiStripFecCabling::module ( const uint32_t &  dcu_id) const

Definition at line 165 of file SiStripFecCabling.cc.

References begin, crates(), and module().

165  {
166  for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
167  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
168  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
169  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
170  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
171  if ( (*imod).dcuId() == dcu_id ) { return *imod; }
172  }
173  }
174  }
175  }
176  }
177  static const SiStripModule module{FedChannelConnection{}};
178  return module;
179 }
Device and connection information at the level of a front-end module.
Definition: SiStripModule.h:24
const SiStripModule & module(const FedChannelConnection &conn) const
const std::vector< SiStripFecCrate > & crates() const
Class containning control, module, detector and connection information, at the level of a FED channel...
#define begin
Definition: vmac.h:30
Definition: vlib.h:208
void SiStripFecCabling::nApvPairs ( const FedChannelConnection conn)
inline

Definition at line 95 of file SiStripFecCabling.h.

References module(), and FedChannelConnection::nApvPairs().

95  {
96  const_cast<SiStripModule&>(module(conn)).nApvPairs(conn.nApvPairs());
97 }
Device and connection information at the level of a front-end module.
Definition: SiStripModule.h:24
void nApvPairs(const FedChannelConnection &conn)
const SiStripModule & module(const FedChannelConnection &conn) const
const uint16_t & nApvPairs() const
void SiStripFecCabling::print ( std::stringstream &  ss) const

Definition at line 271 of file SiStripFecCabling.cc.

References begin, crates(), cuy::ii, sistrip::invalid_, findQualityFiles::jj, pileupDistInMC::total, and TrackValidation_HighPurity_cff::valid.

Referenced by operator<<().

271  {
272  uint32_t valid = 0;
273  uint32_t total = 0;
274  ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
275  ss << "Printing cabling for " << crates().size() << " crates" << std::endl;
276  for ( std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); icrate++ ) {
277  ss << "Printing cabling for " << icrate->fecs().size() << " FECs for crate " << icrate->fecCrate() << std::endl;
278  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
279  ss << "Printing cabling for " << ifec->rings().size() << " rings for FEC " << ifec->fecSlot() << std::endl;
280  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
281  ss << "Printing cabling for " << iring->ccus().size() << " CCUs for ring " << iring->fecRing() << std::endl;
282  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
283  ss << "Printing cabling for " << iccu->modules().size() << " modules for CCU " << iccu->ccuAddr() << std::endl;
284  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
285 
286  SiStripModule::FedCabling conns = imod->fedChannels();
287  SiStripModule::FedCabling::const_iterator ii = conns.begin();
288  SiStripModule::FedCabling::const_iterator jj = conns.end();
289  for ( ; ii != jj; ++ii ) {
290  if ( ii->second.fedId_ != sistrip::invalid_ &&
291  ii->second.fedCh_ != sistrip::invalid_ ) { valid++; }
292  total++;
293  }
294  ss << *imod << std::endl;
295  }
296  }
297  }
298  }
299  }
300  ss << "Number of connected: " << valid << std::endl
301  << "Number of connections: " << total << std::endl;
302 }
const std::vector< SiStripFecCrate > & crates() const
int ii
Definition: cuy.py:588
static const uint16_t invalid_
Definition: Constants.h:16
#define begin
Definition: vmac.h:30
std::map< uint16_t, FedChannel > FedCabling
Definition: SiStripModule.h:59
void SiStripFecCabling::terse ( std::stringstream &  ss) const

Definition at line 306 of file SiStripFecCabling.cc.

References begin, and crates().

306  {
307  ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
308  for ( std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); icrate++ ) {
309  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
310  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
311  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
312  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
313  imod->terse(ss);
314  ss << std::endl;
315  }
316  }
317  }
318  }
319  }
320 }
const std::vector< SiStripFecCrate > & crates() const
#define begin
Definition: vmac.h:30

Member Data Documentation

std::vector<SiStripFecCrate> SiStripFecCabling::crates_
private

Definition at line 72 of file SiStripFecCabling.h.

Referenced by addDevices(), crates(), fecs(), and SiStripFecCabling().