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CSCTMBScope.cc
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1 //_________________________________________________________
2 //
3 // CSCTMBScope 9/11/03 B.Mohr
4 // Unpacks TMB Logic Analyzer and stores in CSCTMBScope.h
5 //_________________________________________________________
6 //
9 #include <iostream>
10 
11 bool CSCTMBScope::debug = false;
12 
13 CSCTMBScope::CSCTMBScope(unsigned short *buf,int b05Line,int e05Line) {
14 
15  size_ = UnpackScope(buf,b05Line,e05Line);
16 
17 } //CSCTMBScope
18 
19 
20 int CSCTMBScope::UnpackScope(unsigned short *buf,int b05Line,int e05Line) {
21 
22  int pretrig_chan[4]={0,0,0,0};
23  unsigned int tbin_strt,tbin_stop;
24  unsigned int ibit,jbit,itbin,ich,iram,iline,iadr;
25  unsigned int lct_bxn;
26 
27 
28  if(debug) {
29  LogTrace("CSCTMBScope|CSCRawToDigi") << " .....TMBHeader -- unpacking Logic Analyzer......";
30  }
31 
32  if((e05Line-b05Line) == 1537) {
33 
34  if(debug)
35  LogTrace("CSCTMBScope|CSCRawToDigi") << "Scope data found";
36 
37  //load scope_ram from raw-hits format readout
38  iline = b05Line + 1;
39  for(iram=0;iram<6;iram++){
40  for(iadr=0;iadr<256;iadr++) {
41  itbin = iadr; //ram_sel*256
42  scope_ram[itbin][iram] = buf[iline];
43  iline++;
44  }
45  }
46 
47  for(ich=0;ich<51;ich++) data[ich]=0; //clear all data
48 
49 
50  //----- find pretrig chan offset -----------------
51  pretrig_chan[0] = GetPretrig(0);
52  pretrig_chan[1] = GetPretrig(32);
53  pretrig_chan[2] = GetPretrig(48);
54  pretrig_chan[3] = GetPretrig(64);
55 
56  //----- ram 1 ------------------------------------
57  tbin_strt = pretrig_chan[0]-7;
58  tbin_stop = pretrig_chan[0]+24;
59 
60  for(ich=0;ich<=14;ich++) {
61  iram=ich/16;
62  jbit=0;
63  for(itbin=tbin_strt;itbin<=tbin_stop;itbin++) {
64  ibit = (scope_ram[itbin][iram] >> (ich%16) ) & 1;
65  data[ich] = (ibit << jbit) | data[ich];
66  jbit++;
67  }
68  }
69 
70  //----- ram 2 ------------------------------------
71  for(ich=16;ich<=30;ich++) {
72  iram=ich/16;
73  jbit=0;
74  for(itbin=tbin_strt;itbin<=tbin_stop;itbin++) {
75  ibit = (scope_ram[itbin][iram] >> (ich%16) ) & 1;
76  data[ich-1] = (ibit << jbit) | data[ich-1];
77  jbit++;
78  }
79  }
80 
81  //----- ram 3 ------------------------------------
82  tbin_strt = pretrig_chan[1]-7;
83  tbin_stop = pretrig_chan[1]+24;
84 
85  for(ich=32;ich<=36;ich++) {
86  iram=ich/16;
87  jbit=0;
88  for(itbin=tbin_strt;itbin<=tbin_stop;itbin++) {
89  ibit = (scope_ram[itbin][iram] >> (ich%16) ) & 1;
90  data[ich-2] = (ibit << jbit) | data[ich-2];
91  jbit++;
92  }
93  }
94 
95  tbin_strt = pretrig_chan[1]-7+120;
96  tbin_stop = pretrig_chan[1]+24+120;
97 
98  for(ich=37;ich<=40;ich++) {
99  iram=ich/16;
100  jbit=0;
101  for(itbin=tbin_strt;itbin<=tbin_stop;itbin++) {
102  ibit = (scope_ram[itbin][iram] >> (ich%16) ) & 1;
103  data[ich-2] = (ibit << jbit) | data[ich-2];
104  jbit++;
105  }
106  }
107 
108  tbin_strt = pretrig_chan[1]-7;
109  tbin_stop = pretrig_chan[1]+24;
110 
111  for(ich=41;ich<=46;ich++) {
112  iram=ich/16;
113  jbit=0;
114  for(itbin=tbin_strt;itbin<=tbin_stop;itbin++) {
115  ibit = (scope_ram[itbin][iram] >> (ich%16) ) & 1;
116  data[ich-2] = (ibit << jbit) | data[ich-2];
117  jbit++;
118  }
119  }
120 
121  //----- ram 4 ------------------------------------
122  tbin_strt = pretrig_chan[2]-7;
123  tbin_stop = pretrig_chan[2]+24;
124 
125  for(ich=48;ich<=53;ich++) {
126  iram=ich/16;
127  jbit=0;
128  for(itbin=tbin_strt;itbin<=tbin_stop;itbin++) {
129  ibit = (scope_ram[itbin][iram] >> (ich%16) ) & 1;
130  data[ich-3] = (ibit << jbit) | data[ich-3];
131  jbit++;
132  }
133  }
134 
135  //----- ram 5 - bxn ------------------------------
136  lct_bxn = 0;
137  jbit=0;
138 
139  for(ich=65;ich<=76;ich++) {
140  iram=ich/16;
141  itbin = pretrig_chan[3];
142  ibit = (scope_ram[itbin][iram] >> (ich%16) ) & 1;
143  lct_bxn = (ibit << jbit) | lct_bxn;
144  jbit++;
145  }
146  data[51]=lct_bxn;
147 
148  if(debug)
149  LogTrace("CSCTMBScope|CSCRawToDigi") << "Scope bxn at LCT (seq_pretrig): "
150  << lct_bxn;
151 
152  //----- now read back decoded scope data ---------
153  if(debug) {
154  for(ich=0;ich<=50;ich++) {
155  for(itbin=0;itbin<32;itbin++) {
156  ibit = (data[ich] >> itbin ) & 1;
157  if(ibit == 0) LogTrace("CSCTMBScope|CSCRawToDigi") << "_"; //display symbol for logic 0
158  if(ibit == 1) LogTrace("CSCTMBScope|CSCRawToDigi") << "-"; //display symbol for logic 1
159  }
160  }
161  }
162 
163  } //end if(b05-e05)
164 
165 
166  //-------------- if no scope data: fill everything with 0 --------------------
167  else {
168  for(ich=0;ich<51;ich++) data[ich]=0;
169  lct_bxn = 0xff0000; //value not possible for real data (short)
170  data[51] = lct_bxn;
171 
172  if(debug)
173  LogTrace("CSCTMBScope|CSCRawToDigi") << "No scope data found: wrdcnt: "
174  << (e05Line-b05Line);
175  }
176 
177  if(debug) {
178  LogTrace("CSCTMBScope|CSCRawToDigi") << " .....END -- unpacking Logic Analyzer...........";
179  }
180 
181  return (e05Line - b05Line + 1);
182 
183 } //UnpackScope
184 
185 
187 
188  unsigned int ibit,itbin,iram;
189  int value = 0;
190 
191  ibit=0;
192  itbin=0;
193  iram=ich/16;
194  while(!ibit) {
195  ibit = (scope_ram[itbin][iram] >> (ich%16) ) & 1;
196  value = itbin;
197  itbin++;
198  }
199 
200  if(debug)
201  LogTrace("CSCTMBScope|CSCRawToDigi") << "TMB SCOPE: ------- Pretrig value: " << value;
202  return value;
203 
204 } //GetPretrig
int UnpackScope(unsigned short *buf, int b05Line, int e05Line)
Definition: CSCTMBScope.cc:20
unsigned short size_
Definition: CSCTMBScope.h:28
#define LogTrace(id)
static bool debug
Definition: CSCTMBScope.h:29
unsigned int data[52]
Definition: CSCTMBScope.h:18
int GetPretrig(int ich)
Definition: CSCTMBScope.cc:186
unsigned int scope_ram[256][6]
Definition: CSCTMBScope.h:27