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L1GtHwValidation.cc
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1 
16 // this class header
17 #include "DQM/L1TMonitor/interface/L1GtHwValidation.h"
18 
19 // system include files
20 #include <memory>
21 #include <iostream>
22 #include <iomanip>
23 
24 // user include files
25 #include "DataFormats/L1GlobalTrigger/interface/L1GlobalTriggerReadoutSetup.h"
26 #include "DataFormats/L1GlobalTrigger/interface/L1GlobalTriggerReadoutRecord.h"
27 #include "DataFormats/L1GlobalTrigger/interface/L1GlobalTriggerEvmReadoutRecord.h"
28 
29 #include "FWCore/MessageLogger/interface/MessageLogger.h"
30 #include "FWCore/ServiceRegistry/interface/Service.h"
31 
32 #include "FWCore/Framework/interface/EventSetup.h"
33 #include "FWCore/Framework/interface/ESHandle.h"
34 #include "FWCore/Framework/interface/Run.h"
35 
36 #include "CondFormats/L1TObjects/interface/L1GtTriggerMenu.h"
37 #include "CondFormats/DataRecord/interface/L1GtTriggerMenuRcd.h"
38 
39 #include "CondFormats/L1TObjects/interface/L1GtPrescaleFactors.h"
40 #include "CondFormats/DataRecord/interface/L1GtPrescaleFactorsAlgoTrigRcd.h"
41 #include "CondFormats/DataRecord/interface/L1GtPrescaleFactorsTechTrigRcd.h"
42 
43 #include "CondFormats/L1TObjects/interface/L1GtTriggerMask.h"
44 #include "CondFormats/DataRecord/interface/L1GtTriggerMaskAlgoTrigRcd.h"
45 #include "CondFormats/DataRecord/interface/L1GtTriggerMaskTechTrigRcd.h"
46 
47 #include "TH1.h"
48 #include "TH2.h"
49 #include "TTree.h"
50 
51 // constructor(s)
52 L1GtHwValidation::L1GtHwValidation(const edm::ParameterSet& paramSet) :
53  //
54  // input tag for the L1 GT hardware DAQ record
55  m_l1GtDataDaqInputTag(paramSet.getParameter<edm::InputTag>(
56  "L1GtDataDaqInputTag")),
57  // input tag for the L1 GT hardware EVM record
58  m_l1GtDataEvmInputTag(paramSet.getParameter<edm::InputTag>(
59  "L1GtDataEvmInputTag")),
60  // input tag for the L1 GT emulator DAQ record
61  m_l1GtEmulDaqInputTag(paramSet.getParameter<edm::InputTag>(
62  "L1GtEmulDaqInputTag")),
63  // input tag for the L1 GT emulator EVM record
64  m_l1GtEmulEvmInputTag(paramSet.getParameter<edm::InputTag>(
65  "L1GtEmulEvmInputTag")),
66  // input tag for the L1 GCT hardware record
67  m_l1GctDataInputTag(paramSet.getParameter<edm::InputTag>(
68  "L1GctDataInputTag")),
69  //
70  m_dirName(paramSet.getUntrackedParameter("DirName", std::string(
71  "L1TEMU/GTexpert"))),
72  //
73  m_excludeCondCategTypeObject(paramSet.getParameter<std::vector<edm::ParameterSet> >(
74  "ExcludeCondCategTypeObject")),
75  //
76  m_excludeAlgoTrigByName(paramSet.getParameter<std::vector<std::string> >(
77  "ExcludeAlgoTrigByName")),
78  //
79  m_excludeAlgoTrigByBit(paramSet.getParameter<std::vector<int> >(
80  "ExcludeAlgoTrigByBit")),
81  //
82  // initialize counters
83  m_nrDataEventError(0),
84  m_nrEmulEventError(0),
85  // cache
86  m_l1GtMenuCacheID(0ULL), m_l1GtPfAlgoCacheID(0ULL),
87  m_l1GtPfTechCacheID(0ULL), m_l1GtTmAlgoCacheID(0ULL),
88  m_l1GtTmTechCacheID(0ULL),
89  //
90  m_dbe(0),
91  m_agree(true),
92  m_dataOnly(false),
93  m_emulOnly(false),
94  m_dataOnlyMask(false),
95  m_emulOnlyMask(false),
96  //
97  m_nrEvJob(0), m_nrEvRun(0) {
98 
99 
100  for (std::vector<edm::ParameterSet>::const_iterator
101  itExclud = m_excludeCondCategTypeObject.begin();
102  itExclud != m_excludeCondCategTypeObject.end();
103  ++itExclud) {
104 
105  if (!(itExclud->getParameter<std::string> ("ExcludedCondCategory")).empty()) {
106 
107  m_excludedCondCategory.push_back(l1GtConditionCategoryStringToEnum(
108  itExclud->getParameter<std::string>("ExcludedCondCategory")));
109 
110  } else {
111  m_excludedCondCategory.push_back(CondNull);
112  }
113 
114  if (!(itExclud->getParameter<std::string>("ExcludedCondType")).empty() ) {
115 
116  m_excludedCondType.push_back(l1GtConditionTypeStringToEnum(
117  itExclud->getParameter<std::string> ("ExcludedCondType")));
118 
119  } else {
120  m_excludedCondType.push_back(TypeNull);
121  }
122 
123  if (!(itExclud->getParameter<std::string>("ExcludedL1GtObject")).empty() ) {
124 
125  m_excludedL1GtObject.push_back(l1GtObjectStringToEnum(
126  itExclud->getParameter<std::string> ("ExcludedL1GtObject")));
127 
128  } else {
129  m_excludedL1GtObject.push_back(ObjNull);
130  }
131  }
132 
133 
134  LogDebug("L1GtHwValidation")
135  << "\nInput tag for the L1 GT DAQ hardware record: "
136  << m_l1GtDataDaqInputTag
137  << "\nInput tag for the L1 GT EVM hardware record: "
138  << m_l1GtDataEvmInputTag
139  << "\nInput tag for the L1 GT DAQ emulator records: "
140  << m_l1GtEmulDaqInputTag
141  << "\nInput tag for the L1 GT EVM emulator records: "
142  << m_l1GtEmulEvmInputTag
143  << "\nInput tag for the L1 GCT hardware record: "
144  << m_l1GctDataInputTag << std::endl;
145 
146  // FIXME print in debug mode ExcludeCondCategTypeObject, ExcludeAlgoTrigByName, etc
147 
148  m_dbe = edm::Service<DQMStore>().operator->();
149  if (m_dbe == 0) {
150  edm::LogInfo("L1GtHwValidation")
151  << "\n Unable to get DQMStore service.";
152  } else {
153 
154  if (paramSet.getUntrackedParameter<bool>("DQMStore", false)) {
155  m_dbe->setVerbose(0);
156  }
157 
158  m_dbe->setCurrentFolder(m_dirName);
159 
160  }
161 
162  //set Token(-s)
163  m_l1GtDataDaqInputToken_ = consumes<L1GlobalTriggerReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtDataDaqInputTag"));
164  m_l1GtEmulDaqInputToken_ = consumes<L1GlobalTriggerReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtEmulDaqInputTag"));
165  m_l1GtDataEvmInputToken_ = consumes<L1GlobalTriggerEvmReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtDataEvmInputTag"));
166  m_l1GtEmulEvmInputToken_ = consumes<L1GlobalTriggerEvmReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtEmulEvmInputTag"));
167 }
168 
169 // destructor
170 L1GtHwValidation::~L1GtHwValidation() {
171  // empty
172 }
173 
174 // member functions
175 
176 // method called once each job just before starting event loop
177 void L1GtHwValidation::beginJob() {
178 
179  DQMStore* dbe = 0;
180  dbe = edm::Service<DQMStore>().operator->();
181 
182  // clean up directory
183  if (dbe) {
184  dbe->setCurrentFolder(m_dirName);
185  if (dbe->dirExists(m_dirName)) {
186  dbe->rmdir(m_dirName);
187  }
188  dbe->setCurrentFolder(m_dirName);
189  }
190 
191  // book histograms
192  bookHistograms();
193 
194 }
195 
196 void L1GtHwValidation::beginRun(const edm::Run& iRun,
197  const edm::EventSetup& evSetup) {
198 
199  m_nrEvRun = 0;
200 
201  // get / update the trigger menu from the EventSetup
202  // local cache & check on cacheIdentifier
203 
204  unsigned long long l1GtMenuCacheID =
205  evSetup.get<L1GtTriggerMenuRcd>().cacheIdentifier();
206 
207  if (m_l1GtMenuCacheID != l1GtMenuCacheID) {
208 
209  edm::ESHandle<L1GtTriggerMenu> l1GtMenu;
210  evSetup.get<L1GtTriggerMenuRcd>().get(l1GtMenu);
211  m_l1GtMenu = l1GtMenu.product();
212 
213  // compute the list of algorithms excluded from the computing of the agreement flag
214  m_excludedAlgoList.clear();
215  excludedAlgoList();
216 
217  m_l1GtMenuCacheID = l1GtMenuCacheID;
218 
219  }
220 
221 
222 
223  // FIXME when the menu changes, make a copy of histograms, and clear the old one
224  // otherwise the labels are wrong
225 
226  LogDebug("L1GtHwValidation") << "\nUsing L1 menu: \n "
227  << m_l1GtMenu->gtTriggerMenuImplementation() << "\n"
228  << std::endl;
229 
230  const AlgorithmMap& algorithmMap = m_l1GtMenu->gtAlgorithmMap();
231 
232  for (CItAlgo itAlgo = algorithmMap.begin(); itAlgo != algorithmMap.end(); itAlgo++) {
233 
234  const int algBitNumber = (itAlgo->second).algoBitNumber();
235 
236  std::stringstream ss;
237  std::string algBitString;
238  ss << std::uppercase << algBitNumber;
239  ss >> algBitString;
240 
241  const std::string& aName = algBitString + " " + itAlgo->first;
242  const char* algName = aName.c_str();
243 
244  for (int iRec = 0; iRec < NumberOfGtRecords; ++iRec) {
245  for (int iBxInEvent = 0; iBxInEvent < TotalBxInEvent; ++iBxInEvent) {
246 
247 
248  // convert [0, TotalBxInEvent] to [-X, +X]
249  int iIndex = iBxInEvent - ((TotalBxInEvent + 1) / 2 - 1);
250  int hIndex = (iIndex + 16) % 16;
251 
252  std::stringstream ss;
253  std::string str;
254  ss << std::uppercase << std::hex << hIndex;
255  ss >> str;
256 
257  if (iRec == 0) {
258  if (m_dbe) {
259  m_dbe->setCurrentFolder(m_dirName + "/DAQ/BxInEvent_" + str);
260  }
261 
262  } else {
263  if (m_dbe) {
264  m_dbe->setCurrentFolder(m_dirName + "/EVM/BxInEvent_" + str);
265  }
266  }
267 
268 
269  m_fdlDataAlgoDecision[iBxInEvent][iRec]->setBinLabel(
270  algBitNumber + 1, algName, 1);
271  m_fdlDataAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(
272  algBitNumber + 1, algName, 1);
273  m_fdlDataAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(
274  algBitNumber + 1, algName, 1);
275  m_fdlDataAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(
276  algBitNumber + 1, algName, 1);
277  m_fdlDataAlgoDecision_NoMatch[iBxInEvent][iRec]->setBinLabel(
278  algBitNumber + 1, algName, 1);
279 
280  m_fdlEmulAlgoDecision[iBxInEvent][iRec]->setBinLabel(
281  algBitNumber + 1, algName, 1);
282  m_fdlEmulAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(
283  algBitNumber + 1, algName, 1);
284  m_fdlEmulAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(
285  algBitNumber + 1, algName, 1);
286  m_fdlEmulAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(
287  algBitNumber + 1, algName, 1);
288  m_fdlEmulAlgoDecision_NoMatch[iBxInEvent][iRec]->setBinLabel(
289  algBitNumber + 1, algName, 1);
290 
291  m_fdlDataEmulAlgoDecision[iBxInEvent][iRec]->setBinLabel(
292  algBitNumber + 1, algName, 1);
293  m_fdlDataEmulAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(
294  algBitNumber + 1, algName, 1);
295  m_fdlDataEmulAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(
296  algBitNumber + 1, algName, 1);
297  m_fdlDataEmulAlgoDecisionUnprescaledAllowed[iBxInEvent][iRec]->setBinLabel(
298  algBitNumber + 1, algName, 1);
299  m_fdlDataEmulAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(
300  algBitNumber + 1, algName, 1);
301  }
302 
303 
304  if (iRec == 0) {
305  if (m_dbe) {
306  m_dbe->setCurrentFolder(m_dirName + "/DAQ/");
307  }
308 
309  } else {
310  if (m_dbe) {
311  m_dbe->setCurrentFolder(m_dirName + "/EVM/");
312  }
313  }
314 
315 
316  m_fdlDataAlgoDecision_Err[iRec]->setBinLabel(algBitNumber + 1,
317  algName, 1);
318 
319  m_fdlEmulAlgoDecision_Err[iRec]->setBinLabel(algBitNumber + 1,
320  algName, 1);
321 
322  m_fdlDataEmulAlgoDecision_Err[iRec]->setBinLabel(algBitNumber
323  + 1, algName, 1);
324  }
325 
326  //
327  for (std::vector<int>::const_iterator itAlgo = m_excludedAlgoList.begin(); itAlgo
328  != m_excludedAlgoList.end(); ++itAlgo) {
329 
330  if (algBitNumber == *itAlgo) {
331  m_excludedAlgorithmsAgreement->setBinLabel(algBitNumber
332  + 1, algName, 1);
333  }
334  }
335 
336 
337  }
338 
339  // get / update the prescale factors from the EventSetup
340  // local cache & check on cacheIdentifier
341 
342  unsigned long long l1GtPfAlgoCacheID = evSetup.get<
343  L1GtPrescaleFactorsAlgoTrigRcd>().cacheIdentifier();
344 
345  if (m_l1GtPfAlgoCacheID != l1GtPfAlgoCacheID) {
346 
347  edm::ESHandle<L1GtPrescaleFactors> l1GtPfAlgo;
348  evSetup.get<L1GtPrescaleFactorsAlgoTrigRcd>().get(l1GtPfAlgo);
349  m_l1GtPfAlgo = l1GtPfAlgo.product();
350 
351  m_prescaleFactorsAlgoTrig = &(m_l1GtPfAlgo->gtPrescaleFactors());
352 
353  m_l1GtPfAlgoCacheID = l1GtPfAlgoCacheID;
354 
355  }
356 
357  unsigned long long l1GtPfTechCacheID = evSetup.get<
358  L1GtPrescaleFactorsTechTrigRcd>().cacheIdentifier();
359 
360  if (m_l1GtPfTechCacheID != l1GtPfTechCacheID) {
361 
362  edm::ESHandle<L1GtPrescaleFactors> l1GtPfTech;
363  evSetup.get<L1GtPrescaleFactorsTechTrigRcd>().get(l1GtPfTech);
364  m_l1GtPfTech = l1GtPfTech.product();
365 
366  m_prescaleFactorsTechTrig = &(m_l1GtPfTech->gtPrescaleFactors());
367 
368  m_l1GtPfTechCacheID = l1GtPfTechCacheID;
369 
370  }
371 
372  // get / update the trigger mask from the EventSetup
373  // local cache & check on cacheIdentifier
374 
375  unsigned long long l1GtTmAlgoCacheID = evSetup.get<
376  L1GtTriggerMaskAlgoTrigRcd>().cacheIdentifier();
377 
378  if (m_l1GtTmAlgoCacheID != l1GtTmAlgoCacheID) {
379 
380  edm::ESHandle<L1GtTriggerMask> l1GtTmAlgo;
381  evSetup.get<L1GtTriggerMaskAlgoTrigRcd>().get(l1GtTmAlgo);
382  m_l1GtTmAlgo = l1GtTmAlgo.product();
383 
384  m_triggerMaskAlgoTrig = m_l1GtTmAlgo->gtTriggerMask();
385 
386  m_l1GtTmAlgoCacheID = l1GtTmAlgoCacheID;
387 
388  }
389 
390  unsigned long long l1GtTmTechCacheID = evSetup.get<
391  L1GtTriggerMaskTechTrigRcd>().cacheIdentifier();
392 
393  if (m_l1GtTmTechCacheID != l1GtTmTechCacheID) {
394 
395  edm::ESHandle<L1GtTriggerMask> l1GtTmTech;
396  evSetup.get<L1GtTriggerMaskTechTrigRcd>().get(l1GtTmTech);
397  m_l1GtTmTech = l1GtTmTech.product();
398 
399  m_triggerMaskTechTrig = m_l1GtTmTech->gtTriggerMask();
400 
401  m_l1GtTmTechCacheID = l1GtTmTechCacheID;
402 
403  }
404 
405 }
406 
407 //compare the GTFE board
408 void L1GtHwValidation::compareGTFE(const edm::Event& iEvent,
409  const edm::EventSetup& evSetup, const L1GtfeWord& gtfeBlockData,
410  const L1GtfeWord& gtfeBlockEmul, const int iRec) {
411 
412  std::string recString;
413  if (iRec == 0) {
414  recString = "DAQ";
415  if (m_dbe) {
416  m_dbe->setCurrentFolder(m_dirName + "/DAQ/");
417  }
418  } else {
419  recString = "EVM";
420  if (m_dbe) {
421  m_dbe->setCurrentFolder(m_dirName + "/EVM/");
422  }
423  }
424 
425  if (gtfeBlockData == gtfeBlockEmul) {
426  m_myCoutStream << "\n" << recString
427  << " Data and emulated GTFE blocks: identical.\n";
428  gtfeBlockData.print(m_myCoutStream);
429  } else {
430  m_myCoutStream << "\n" << recString
431  << " Data and emulated GTFE blocks: different.\n";
432 
433  m_myCoutStream << "\nData: GTFE block\n";
434  gtfeBlockData.print(m_myCoutStream);
435 
436  m_myCoutStream << "\nEmul: GTFE block\n";
437  gtfeBlockEmul.print(m_myCoutStream);
438 
439  }
440 
441  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
442 
443  m_myCoutStream.str("");
444  m_myCoutStream.clear();
445 
446  // get BoardId value
447  const boost::uint16_t boardIdData = gtfeBlockData.boardId();
448  const boost::uint16_t boardIdEmul = gtfeBlockEmul.boardId();
449 
450  if (boardIdData == boardIdEmul) {
451  m_myCoutStream << "\n" << recString
452  << " Data and emulated GTFE boardId identical.";
453  m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4)
454  << std::setfill('0') << boardIdData << std::setfill(' ')
455  << std::dec;
456  m_myCoutStream << "\n";
457 
458  } else {
459  m_myCoutStream << "\n" << recString
460  << " Data and emulated GTFE boardId different.";
461  m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x"
462  << std::setw(4) << std::setfill('0') << boardIdData
463  << std::setfill(' ') << std::dec;
464  m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x"
465  << std::setw(4) << std::setfill('0') << boardIdEmul
466  << std::setfill(' ') << std::dec;
467  m_myCoutStream << "\n";
468  m_gtfeDataEmul[iRec]->Fill(0);
469 
470  }
471 
473  const boost::uint16_t recordLength1Data = gtfeBlockData.recordLength1();
474  const boost::uint16_t recordLength1Emul = gtfeBlockEmul.recordLength1();
475 
476  if (recordLength1Data == recordLength1Emul) {
477  m_myCoutStream << "\n" << recString
478  << " Data and emulated GTFE recordLength for alternative 1 identical.";
479  m_myCoutStream << "\n recordLength1() = " << recordLength1Data;
480  m_myCoutStream << "\n";
481 
482  } else {
483  m_myCoutStream << "\n" << recString
484  << " Data and emulated GTFE recordLength for alternative 1 different.";
485  m_myCoutStream << "\n Data: recordLength1() = " << recordLength1Data;
486  m_myCoutStream << "\n Emul: recordLength1() = " << recordLength1Emul;
487  m_myCoutStream << "\n";
488  m_gtfeDataEmul[iRec]->Fill(1);
489 
490  }
491 
493  const boost::uint16_t recordLengthData = gtfeBlockData.recordLength();
494  const boost::uint16_t recordLengthEmul = gtfeBlockEmul.recordLength();
495 
496  if (recordLengthData == recordLengthEmul) {
497  m_myCoutStream << "\n" << recString
498  << " Data and emulated GTFE recordLength for alternative 0 identical.";
499  m_myCoutStream << "\n recordLength() = " << recordLengthData;
500  m_myCoutStream << "\n";
501 
502  } else {
503  m_myCoutStream << "\n" << recString
504  << " Data and emulated GTFE recordLength for alternative 1 different.";
505  m_myCoutStream << "\n Data: recordLength() = " << recordLengthData;
506  m_myCoutStream << "\n Emul: recordLength() = " << recordLengthEmul;
507  m_myCoutStream << "\n";
508  m_gtfeDataEmul[iRec]->Fill(2);
509 
510  }
511 
513  const boost::uint16_t bxNrData = gtfeBlockData.bxNr();
514  const boost::uint16_t bxNrEmul = gtfeBlockEmul.bxNr();
515 
516  if (bxNrData == bxNrEmul) {
517  m_myCoutStream << "\n" << recString
518  << " Data and emulated GTFE bxNr identical.";
519  m_myCoutStream << "\n bxNr() = " << bxNrData;
520  m_myCoutStream << "\n";
521 
522  } else {
523  m_myCoutStream << "\n" << recString
524  << " Data and emulated GTFE bxNr different.";
525  m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
526  m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
527  m_myCoutStream << "\n";
528  m_gtfeDataEmul[iRec]->Fill(3);
529 
530  }
531 
533  const boost::uint32_t setupVersionData = gtfeBlockData.setupVersion();
534  const boost::uint32_t setupVersionEmul = gtfeBlockEmul.setupVersion();
535 
536  if (setupVersionData == setupVersionEmul) {
537  m_myCoutStream << "\n" << recString
538  << " Data and emulated GTFE setupVersion identical.";
539  m_myCoutStream << "\n setupVersion() = " << setupVersionData;
540  m_myCoutStream << "\n";
541 
542  } else {
543  m_myCoutStream << "\n" << recString
544  << " Data and emulated GTFE setupVersion different.";
545  m_myCoutStream << "\n Data: setupVersion() = " << setupVersionData;
546  m_myCoutStream << "\n Emul: setupVersion() = " << setupVersionEmul;
547  m_myCoutStream << "\n";
548  m_gtfeDataEmul[iRec]->Fill(4);
549 
550  }
551 
553  const boost::uint16_t activeBoardsData = gtfeBlockData.activeBoards();
554  const boost::uint16_t activeBoardsEmul = gtfeBlockEmul.activeBoards();
555 
556  if (activeBoardsData == activeBoardsEmul) {
557  m_myCoutStream << "\n" << recString
558  << " Data and emulated GTFE activeBoards identical.";
559  m_myCoutStream << "\n activeBoards() = " << std::hex << "0x"
560  << std::setw(4) << std::setfill('0') << activeBoardsData
561  << std::setfill(' ') << std::dec;
562  m_myCoutStream << "\n";
563 
564  } else {
565  m_myCoutStream << "\n" << recString
566  << " Data and emulated GTFE activeBoards different.";
567  m_myCoutStream << "\n Data: activeBoards() = " << std::hex << "0x"
568  << std::setw(4) << std::setfill('0') << activeBoardsData
569  << std::setfill(' ') << std::dec;
570  m_myCoutStream << "\n Emul: activeBoards() = " << std::hex << "0x"
571  << std::setw(4) << std::setfill('0') << activeBoardsEmul
572  << std::setfill(' ') << std::dec;
573  m_myCoutStream << "\n";
574  m_gtfeDataEmul[iRec]->Fill(5);
575 
576  }
581  const boost::uint16_t altNrBxBoardData = gtfeBlockData.altNrBxBoard();
582  const boost::uint16_t altNrBxBoardEmul = gtfeBlockEmul.altNrBxBoard();
583 
584  if (altNrBxBoardData == altNrBxBoardEmul) {
585  m_myCoutStream << "\n" << recString
586  << " Data and emulated GTFE altNrBxBoard identical.";
587  m_myCoutStream << "\n altNrBxBoard() = " << altNrBxBoardData;
588  m_myCoutStream << "\n";
589 
590  } else {
591  m_myCoutStream << "\n" << recString
592  << " Data and emulated GTFE altNrBxBoard different.";
593  m_myCoutStream << "\n Data: altNrBxBoard() = " << altNrBxBoardData;
594  m_myCoutStream << "\n Emul: altNrBxBoard() = " << altNrBxBoardEmul;
595  m_myCoutStream << "\n";
596  m_gtfeDataEmul[iRec]->Fill(6);
597 
598  }
599 
601  const boost::uint32_t totalTriggerNrData = gtfeBlockData.totalTriggerNr();
602  const boost::uint32_t totalTriggerNrEmul = gtfeBlockEmul.totalTriggerNr();
603 
604  if (totalTriggerNrData == totalTriggerNrEmul) {
605  m_myCoutStream << "\n" << recString
606  << " Data and emulated GTFE totalTriggerNr identical.";
607  m_myCoutStream << "\n totalTriggerNr() = " << totalTriggerNrData;
608  m_myCoutStream << "\n";
609 
610  } else {
611  m_myCoutStream << "\n" << recString
612  << " Data and emulated GTFE totalTriggerNr different.";
613  m_myCoutStream << "\n Data: totalTriggerNr() = " << totalTriggerNrData;
614  m_myCoutStream << "\n Emul: totalTriggerNr() = " << totalTriggerNrEmul;
615  m_myCoutStream << "\n";
616  m_gtfeDataEmul[iRec]->Fill(7);
617 
618  }
619 
620  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
621  m_myCoutStream.str("");
622  m_myCoutStream.clear();
623 
624 }
625 
626 //compare the FDL board
627 void L1GtHwValidation::compareFDL(const edm::Event& iEvent,
628  const edm::EventSetup& evSetup, const L1GtFdlWord& fdlBlockData,
629  const L1GtFdlWord& fdlBlockEmul, const int iRec) {
630 
631  // index of physics partition
632  int PhysicsPartition = 0;
633 
634  //
635  std::string recString;
636  if (iRec == 0) {
637  recString = "DAQ";
638  if (m_dbe) {
639  m_dbe->setCurrentFolder(m_dirName + "/DAQ/");
640  }
641  } else {
642  recString = "EVM";
643  if (m_dbe) {
644  m_dbe->setCurrentFolder(m_dirName + "/EVM/");
645  }
646  }
647 
648  if (fdlBlockData == fdlBlockEmul) {
649  m_myCoutStream << "\n" << recString
650  << " Data and emulated FDL blocks: identical.\n";
651  fdlBlockData.print(m_myCoutStream);
652 
653  } else {
654  m_myCoutStream << "\n" << recString
655  << " Data and emulated FDL blocks: different.\n";
656 
657  m_myCoutStream << "\nData: FDL block\n";
658  fdlBlockData.print(m_myCoutStream);
659 
660  m_myCoutStream << "\nEmul: FDL block\n";
661  fdlBlockEmul.print(m_myCoutStream);
662 
663  }
664 
665  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
666 
667  m_myCoutStream.str("");
668  m_myCoutStream.clear();
669 
670  // get bunch cross in the GT event record -
671  // move it first as histograms are BxInEvent dependent
672  const int bxInEventData = fdlBlockData.bxInEvent();
673  const int bxInEventEmul = fdlBlockEmul.bxInEvent();
674 
675  bool matchBxInEvent = false;
676 
677  if (bxInEventData == bxInEventEmul) {
678  m_myCoutStream << "\n" << recString
679  << " Data and emulated FDL bxInEvent identical.";
680  m_myCoutStream << "\n bxInEvent() = " << bxInEventData;
681  m_myCoutStream << "\n";
682  matchBxInEvent = true;
683 
684  } else {
685  m_myCoutStream << "\n" << recString
686  << " Data and emulated FDL bxInEvent different.";
687  m_myCoutStream << "\n Data: bxInEvent() = " << bxInEventData;
688  m_myCoutStream << "\n Emul: bxInEvent() = " << bxInEventEmul;
689  m_myCoutStream << "\n";
690 
691  m_fdlDataEmul_Err[iRec]->Fill(1);
692 
693  if (iRec == 0) {
694  m_agree = false;
695 
696  m_myCoutStream << "\nDisagreement data versus emulator: "
697  << "\n Data and emulated FDL bxInEvent different \n";
698  }
699 
700  }
701 
702  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
703  m_myCoutStream.str("");
704  m_myCoutStream.clear();
705 
706  // symmetrize
707  bool validBxInEvent = false;
708  int histIndex = bxInEventData + (TotalBxInEvent + 1) / 2 - 1;
709  LogDebug("L1GtHwValidation") << "\n Convert bxInEvent = " << bxInEventData
710  << " to histIndex = " << histIndex << std::endl;
711  if ((histIndex <= TotalBxInEvent) && (histIndex >= 0)) {
712  validBxInEvent = true;
713  }
714 
715  // loop over algorithms and increase the corresponding counters
716 
717  // get BoardId value
718  const boost::uint16_t boardIdData = fdlBlockData.boardId();
719  const boost::uint16_t boardIdEmul = fdlBlockEmul.boardId();
720 
721  if (boardIdData == boardIdEmul) {
722  m_myCoutStream << "\n" << recString
723  << " Data and emulated FDL boardId identical.";
724  m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4)
725  << std::setfill('0') << boardIdData << std::setfill(' ')
726  << std::dec;
727  m_myCoutStream << "\n";
728 
729  } else {
730  m_myCoutStream << "\n" << recString
731  << " Data and emulated FDL boardId different.";
732  m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x"
733  << std::setw(4) << std::setfill('0') << boardIdData
734  << std::setfill(' ') << std::dec;
735  m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x"
736  << std::setw(4) << std::setfill('0') << boardIdEmul
737  << std::setfill(' ') << std::dec;
738  m_myCoutStream << "\n";
739 
740  if (matchBxInEvent && validBxInEvent) {
741  m_fdlDataEmul[histIndex][iRec]->Fill(0);
742  } else {
743  m_fdlDataEmul_Err[iRec]->Fill(0);
744  }
745 
746  }
747 
748  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
749  m_myCoutStream.str("");
750  m_myCoutStream.clear();
751 
752  // get BxNr - bunch cross number of the actual bx
753  const boost::uint16_t bxNrData = fdlBlockData.bxNr();
754  const boost::uint16_t bxNrEmul = fdlBlockEmul.bxNr();
755 
756  if (bxNrData == bxNrEmul) {
757  m_myCoutStream << "\n" << recString
758  << " Data and emulated FDL bxNr identical.";
759  m_myCoutStream << "\n bxNr() = " << bxNrData;
760  m_myCoutStream << "\n";
761 
762  } else {
763  m_myCoutStream << "\n" << recString
764  << " Data and emulated FDL bxNr different.";
765  m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
766  m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
767  m_myCoutStream << "\n";
768 
769  if (matchBxInEvent && validBxInEvent) {
770  m_fdlDataEmul[histIndex][iRec]->Fill(2);
771  } else {
772  m_fdlDataEmul_Err[iRec]->Fill(2);
773  }
774  }
775 
776  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
777  m_myCoutStream.str("");
778  m_myCoutStream.clear();
779 
780  // get event number since last L1 reset generated in FDL
781  const boost::uint32_t eventNrData = fdlBlockData.eventNr();
782  const boost::uint32_t eventNrEmul = fdlBlockEmul.eventNr();
783 
784  if (eventNrData == eventNrEmul) {
785  m_myCoutStream << "\n" << recString
786  << " Data and emulated FDL eventNr identical.";
787  m_myCoutStream << "\n eventNr() = " << eventNrData;
788  m_myCoutStream << "\n";
789 
790  } else {
791  m_myCoutStream << "\n" << recString
792  << " Data and emulated FDL eventNr different.";
793  m_myCoutStream << "\n Data: eventNr() = " << eventNrData;
794  m_myCoutStream << "\n Emul: eventNr() = " << eventNrEmul;
795  m_myCoutStream << "\n";
796 
797  if (matchBxInEvent && validBxInEvent) {
798  m_fdlDataEmul[histIndex][iRec]->Fill(3);
799  } else {
800  m_fdlDataEmul_Err[iRec]->Fill(3);
801  }
802 
803  }
804 
805  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
806  m_myCoutStream.str("");
807  m_myCoutStream.clear();
808 
809  // get technical trigger bits
810  const TechnicalTriggerWord& gtTechnicalTriggerWordData =
811  fdlBlockData.gtTechnicalTriggerWord();
812  const TechnicalTriggerWord& gtTechnicalTriggerWordEmul =
813  fdlBlockEmul.gtTechnicalTriggerWord();
814 
815  int nTechBits = gtTechnicalTriggerWordData.size();
816 
817  TechnicalTriggerWord gtTechnicalTriggerWordDataMask(nTechBits);
818  TechnicalTriggerWord gtTechnicalTriggerWordEmulMask(nTechBits);
819 
820  unsigned int bitValue = 0;
821 
822  if (matchBxInEvent && validBxInEvent) {
823  for (int iBit = 0; iBit < nTechBits; ++iBit) {
824 
825  unsigned int triggerMask = (m_triggerMaskTechTrig.at(iBit)) & (1
826  << PhysicsPartition);
827 
828  if (gtTechnicalTriggerWordData[iBit]) {
829  m_fdlDataTechDecision[histIndex][iRec]->Fill(iBit);
830 
831  bitValue = (triggerMask) ? 0 : 1;
832  gtTechnicalTriggerWordDataMask[iBit] = bitValue;
833  if (bitValue) {
834  m_fdlDataTechDecisionMask[histIndex][iRec]->Fill(iBit);
835  }
836  }
837 
838  if (gtTechnicalTriggerWordEmul.at(iBit)) {
839  m_fdlEmulTechDecision[histIndex][iRec]->Fill(iBit);
840 
841  bitValue = (triggerMask) ? 0 : 1;
842  gtTechnicalTriggerWordEmulMask[iBit] = bitValue;
843  if (bitValue) {
844  m_fdlEmulTechDecisionMask[histIndex][iRec]->Fill(iBit);
845  }
846  }
847  }
848  } else {
849  for (int iBit = 0; iBit < nTechBits; ++iBit) {
850 
851  if (gtTechnicalTriggerWordData[iBit]) {
852  m_fdlDataTechDecision_Err[iRec]->Fill(iBit);
853  }
854 
855  if (gtTechnicalTriggerWordEmul.at(iBit)) {
856  m_fdlEmulTechDecision_Err[iRec]->Fill(iBit);
857  }
858  }
859  }
860 
861  if (gtTechnicalTriggerWordData == gtTechnicalTriggerWordEmul) {
862  m_myCoutStream << "\n" << recString
863  << " Data and emulated FDL gtTechnicalTriggerWord identical.\n";
864  fdlBlockData.printGtTechnicalTriggerWord(m_myCoutStream);
865  m_myCoutStream << "\n";
866 
867  } else {
868  m_myCoutStream << "\n" << recString
869  << " Data and emulated FDL gtTechnicalTriggerWord different.";
870  m_myCoutStream << "\n Data: ";
871  fdlBlockData.printGtTechnicalTriggerWord(m_myCoutStream);
872  m_myCoutStream << "\n Emul: ";
873  fdlBlockEmul.printGtTechnicalTriggerWord(m_myCoutStream);
874  m_myCoutStream << "\n";
875 
876  if (matchBxInEvent && validBxInEvent) {
877  m_fdlDataEmul[histIndex][iRec]->Fill(4);
878  } else {
879  m_fdlDataEmul_Err[iRec]->Fill(4);
880  }
881 
882  if (matchBxInEvent && validBxInEvent) {
883  for (int iBit = 0; iBit < nTechBits; ++iBit) {
884  if (gtTechnicalTriggerWordData[iBit]
885  != gtTechnicalTriggerWordEmul.at(iBit)) {
886  m_fdlDataEmulTechDecision[histIndex][iRec]->Fill(iBit);
887  }
888  }
889  } else {
890  for (int iBit = 0; iBit < nTechBits; ++iBit) {
891  if (gtTechnicalTriggerWordData[iBit]
892  != gtTechnicalTriggerWordEmul.at(iBit)) {
893  m_fdlDataEmulTechDecision_Err[iRec]->Fill(iBit);
894  }
895  }
896  }
897  }
898 
899  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
900  m_myCoutStream.str("");
901  m_myCoutStream.clear();
902 
903  if (gtTechnicalTriggerWordDataMask == gtTechnicalTriggerWordEmulMask) {
904  m_myCoutStream << "\n" << recString
905  << " Data and emulated FDL gtTechnicalTriggerWord after mask identical.\n";
906  m_myCoutStream << "\n";
907 
908  } else {
909  m_myCoutStream << "\n" << recString
910  << " Data and emulated FDL gtTechnicalTriggerWord after mask different.";
911  m_myCoutStream << "\n Data: ";
912  m_myCoutStream << "\n Emul: ";
913  m_myCoutStream << "\n";
914 
915  if (matchBxInEvent && validBxInEvent) {
916  m_fdlDataEmul[histIndex][iRec]->Fill(5);
917  } else {
918  m_fdlDataEmul_Err[iRec]->Fill(5);
919  }
920 
921  if (matchBxInEvent && validBxInEvent) {
922  for (int iBit = 0; iBit < nTechBits; ++iBit) {
923  if (gtTechnicalTriggerWordData[iBit]
924  != gtTechnicalTriggerWordEmul.at(iBit)) {
925  m_fdlDataEmulTechDecisionMask[histIndex][iRec]->Fill(iBit);
926  }
927  }
928  }
929  }
930 
931  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
932  m_myCoutStream.str("");
933  m_myCoutStream.clear();
934 
935  // get algorithms bits (decision word)
936  const DecisionWord& gtDecisionWordData = fdlBlockData.gtDecisionWord();
937  const DecisionWord& gtDecisionWordEmul = fdlBlockEmul.gtDecisionWord();
938 
939  int nAlgoBits = gtDecisionWordData.size();
940 
941  DecisionWord gtDecisionWordDataMask(nAlgoBits);
942  DecisionWord gtDecisionWordEmulMask(nAlgoBits);
943 
944  // get the index of the prescale factor set from data
945  int iPfSet = fdlBlockData.gtPrescaleFactorIndexAlgo();
946 
947  // check that the prescale factor is not out of range for the prescale factor
948  // record retrieved from event setup
949  size_t pfSetsSize = (*m_prescaleFactorsAlgoTrig).size();
950 
951  if (iPfSet < 0) {
952 
953  LogDebug("L1GtHwValidation")
954  << "\nError: index of prescale factor set retrieved from the data \n"
955  << "less than zero."
956  << "\n Value of index retrieved from data = " << iPfSet
957  << std::endl;
958 
959  // FIXME add a histogram to be used for a quality test
960 
961  return;
962 
963  } else if (iPfSet >= (static_cast<int>(pfSetsSize))) {
964 
965  LogDebug("L1GtHwValidation")
966  << "\nError: index of prescale factor set retrieved from the data \n"
967  << "greater than the size of the vector of prescale factor sets."
968  << "\n Value of index retrieved from data = " << iPfSet
969  << "\n Vector size = " << pfSetsSize << std::endl;
970 
971  // FIXME add a histogram to be used for a quality test
972 
973  return;
974 
975  }
976 
977  const std::vector<int>& prescaleFactorsAlgoTrig =
978  (*m_prescaleFactorsAlgoTrig).at(iPfSet);
979 
980 
981  if (matchBxInEvent && validBxInEvent) {
982 
983  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
984 
985  unsigned int triggerMask = (m_triggerMaskAlgoTrig.at(iBit)) & (1
986  << PhysicsPartition);
987 
988  int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
989 
990  LogTrace("L1GtHwValidation") << "Bit " << iBit
991  << ": prescale factor = " << prescaleFactor
992  << " trigger mask = " << triggerMask << std::endl;
993 
994  if (gtDecisionWordData[iBit]) {
995  m_fdlDataAlgoDecision[histIndex][iRec]->Fill(iBit);
996 
997  if (prescaleFactor == 1) {
998  m_fdlDataAlgoDecisionUnprescaled[histIndex][iRec]->Fill(
999  iBit);
1000  } else {
1001  m_fdlDataAlgoDecisionPrescaled[histIndex][iRec]->Fill(iBit);
1002  }
1003 
1004  bitValue = (triggerMask) ? 0 : 1;
1005  gtDecisionWordDataMask[iBit] = bitValue;
1006  if (bitValue) {
1007  m_fdlDataAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
1008  }
1009  }
1010 
1011  if (gtDecisionWordEmul.at(iBit)) {
1012  m_fdlEmulAlgoDecision[histIndex][iRec]->Fill(iBit);
1013 
1014  bitValue = (triggerMask) ? 0 : 1;
1015  gtDecisionWordEmulMask[iBit] = bitValue;
1016  if (bitValue) {
1017  m_fdlEmulAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
1018  }
1019  }
1020  }
1021  } else {
1022  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1023  if (gtDecisionWordData[iBit]) {
1024  m_fdlDataAlgoDecision_Err[iRec]->Fill(iBit);
1025  }
1026  }
1027 
1028  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1029  if (gtDecisionWordEmul.at(iBit)) {
1030  m_fdlEmulAlgoDecision_Err[iRec]->Fill(iBit);
1031  }
1032  }
1033 
1034  if (iRec == 0) {
1035  m_agree = false;
1036 
1037  m_myCoutStream << "\nDisagreement data versus emulator: "
1038  << "\n matchBxInEvent && validBxInEvent false \n";
1039  }
1040 
1041  }
1042 
1043  if (gtDecisionWordData == gtDecisionWordEmul) {
1044  m_myCoutStream << "\n" << recString
1045  << " Data and emulated FDL gtDecisionWord identical.";
1046  fdlBlockData.printGtDecisionWord(m_myCoutStream);
1047  m_myCoutStream << "\n";
1048 
1049  } else {
1050  m_myCoutStream << "\n" << recString
1051  << " Data and emulated FDL gtDecisionWord different.";
1052  m_myCoutStream << "\n Data: ";
1053  fdlBlockData.printGtDecisionWord(m_myCoutStream);
1054  m_myCoutStream << "\n Emul: ";
1055  fdlBlockEmul.printGtDecisionWord(m_myCoutStream);
1056  m_myCoutStream << "\n";
1057 
1058  if (matchBxInEvent && validBxInEvent) {
1059  m_fdlDataEmul[histIndex][iRec]->Fill(6);
1060  } else {
1061  m_fdlDataEmul_Err[iRec]->Fill(6);
1062  }
1063 
1064  if (matchBxInEvent && validBxInEvent) {
1065  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1066 
1067  int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
1068 
1069  if (gtDecisionWordData[iBit] != gtDecisionWordEmul.at(iBit)) {
1070 
1071  m_fdlDataEmulAlgoDecision[histIndex][iRec]->Fill(iBit);
1072 
1073  // for excluded algorithms, fill mismatch for BxInEvent = 0 and DAQ record only
1074  if (excludedAlgo(iBit) && (bxInEventData == 0) && (iRec
1075  == 0)) {
1076  m_excludedAlgorithmsAgreement->Fill(iBit);
1077  }
1078 
1079  if (prescaleFactor == 1) {
1080  m_fdlDataEmulAlgoDecisionUnprescaled[histIndex][iRec]->Fill(
1081  iBit);
1082 
1083  // fill a histogram for allowed algorithm triggers only
1084  if (!excludedAlgo(iBit)) {
1085  m_fdlDataEmulAlgoDecisionUnprescaledAllowed[histIndex][iRec]->Fill(
1086  iBit);
1087  }
1088 
1089  } else {
1090  m_fdlDataEmulAlgoDecisionPrescaled[histIndex][iRec]->Fill(
1091  iBit);
1092  }
1093 
1094  if (gtDecisionWordData[iBit]) {
1095  m_fdlDataAlgoDecision_NoMatch[histIndex][iRec]->Fill(
1096  iBit);
1097 
1098  if (prescaleFactor == 1) {
1099  m_fdlDataAlgoDecisionUnprescaled_NoMatch[histIndex][iRec]->Fill(
1100  iBit);
1101 
1102  // compare for agreement only unprescaled algorithms and algorithms which
1103  // are not excluded from comparison
1104  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1105  && (iRec == 0)) {
1106  m_agree = false;
1107  m_dataOnly = true;
1108 
1109  m_myCoutStream
1110  << "\nDisagreement data versus emulator: "
1111  << "result before mask for algorithm with bit number "
1112  << iBit
1113  << "\n Data: true, emulator: false \n";
1114  }
1115 
1116  } else {
1117  m_fdlDataAlgoDecisionPrescaled_NoMatch[histIndex][iRec]->Fill(
1118  iBit);
1119  }
1120 
1121  } else {
1122  m_fdlEmulAlgoDecision_NoMatch[histIndex][iRec]->Fill(
1123  iBit);
1124 
1125  if (prescaleFactor == 1) {
1126  m_fdlEmulAlgoDecisionUnprescaled_NoMatch[histIndex][iRec]->Fill(
1127  iBit);
1128 
1129  // compare for agreement only unprescaled algorithms and algorithms which
1130  // are not excluded from comparison
1131  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1132  && (iRec == 0)) {
1133  m_agree = false;
1134  m_emulOnly = true;
1135 
1136  m_myCoutStream
1137  << "\nDisagreement data versus emulator: "
1138  << "result before mask for algorithm with bit number "
1139  << iBit
1140  << "\n Data: false, emulator: true \n";
1141  }
1142 
1143  } else {
1144  m_fdlEmulAlgoDecisionPrescaled_NoMatch[histIndex][iRec]->Fill(
1145  iBit);
1146  }
1147  }
1148  }
1149  }
1150  } else {
1151  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1152  if (gtDecisionWordData[iBit] != gtDecisionWordEmul.at(iBit)) {
1153  m_fdlDataEmulAlgoDecision_Err[iRec]->Fill(iBit);
1154  }
1155  }
1156 
1157  if (iRec == 0) {
1158  m_agree = false;
1159 
1160  m_myCoutStream << "\nDisagreement data versus emulator: "
1161  << "\n matchBxInEvent && validBxInEvent false \n";
1162  }
1163  }
1164 
1165  }
1166 
1167  if (gtDecisionWordDataMask == gtDecisionWordEmulMask) {
1168  m_myCoutStream << "\n" << recString
1169  << " Data and emulated FDL gtDecisionWord after mask identical.";
1170  m_myCoutStream << "\n";
1171 
1172  } else {
1173  m_myCoutStream << "\n" << recString
1174  << " Data and emulated FDL gtDecisionWord after mask different.";
1175  m_myCoutStream << "\n Data: ";
1176  m_myCoutStream << "\n Emul: ";
1177  m_myCoutStream << "\n";
1178 
1179  if (matchBxInEvent && validBxInEvent) {
1180  m_fdlDataEmul[histIndex][iRec]->Fill(7);
1181  } else {
1182  m_fdlDataEmul_Err[iRec]->Fill(7);
1183  }
1184 
1185  if (matchBxInEvent && validBxInEvent) {
1186  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1187  if (gtDecisionWordDataMask[iBit] != gtDecisionWordEmulMask.at(
1188  iBit)) {
1189  m_fdlDataEmulAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
1190 
1191 
1192  int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
1193 
1194  if (gtDecisionWordDataMask[iBit]) {
1195  m_fdlDataAlgoDecisionMask_NoMatch[histIndex][iRec]->Fill(
1196  iBit);
1197 
1198  if (prescaleFactor == 1) {
1199  m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[histIndex][iRec]->Fill(
1200  iBit);
1201 
1202  // compare for agreement only unprescaled algorithms and algorithms which
1203  // are not excluded from comparison
1204  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1205  && (iRec == 0)) {
1206  m_agree = false;
1207  m_dataOnlyMask = true;
1208 
1209  m_myCoutStream
1210  << "\nDisagreement data versus emulator: "
1211  << "result after mask for algorithm with bit number "
1212  << iBit
1213  << " different in data versus emulator "
1214  << "\n Data: true, emulator: false \n";
1215  }
1216 
1217  } else {
1218  m_fdlDataAlgoDecisionPrescaledMask_NoMatch[histIndex][iRec]->Fill(
1219  iBit);
1220  }
1221 
1222  } else {
1223  m_fdlEmulAlgoDecisionMask_NoMatch[histIndex][iRec]->Fill(
1224  iBit);
1225 
1226  if (prescaleFactor == 1) {
1227  m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[histIndex][iRec]->Fill(
1228  iBit);
1229 
1230  // compare for agreement only unprescaled algorithms and algorithms which
1231  // are not excluded from comparison
1232  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1233  && (iRec == 0)) {
1234  m_agree = false;
1235  m_emulOnlyMask = true;
1236 
1237  m_myCoutStream
1238  << "\nDisagreement data versus emulator: "
1239  << "result after mask for algorithm with bit number "
1240  << iBit
1241  << " different in data versus emulator "
1242  << "\n Data: false, emulator: true \n";
1243  }
1244 
1245  } else {
1246  m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[histIndex][iRec]->Fill(
1247  iBit);
1248  }
1249  }
1250 
1251 
1252  }
1253  }
1254  }
1255 
1256  }
1257 
1258  // get extended algorithms bits (extended decision word)
1259  const DecisionWordExtended gtDecisionWordExtendedData =
1260  fdlBlockData.gtDecisionWordExtended();
1261  const DecisionWordExtended gtDecisionWordExtendedEmul =
1262  fdlBlockEmul.gtDecisionWordExtended();
1263 
1264  if (gtDecisionWordExtendedData == gtDecisionWordExtendedEmul) {
1265  m_myCoutStream << "\n" << recString
1266  << " Data and emulated FDL gtDecisionWordExtended identical.\n";
1267  fdlBlockData.printGtDecisionWordExtended(m_myCoutStream);
1268  m_myCoutStream << "\n";
1269 
1270  } else {
1271  m_myCoutStream << "\n" << recString
1272  << " Data and emulated FDL gtDecisionWordExtended different.\n";
1273  m_myCoutStream << "\n Data: ";
1274  fdlBlockData.printGtDecisionWordExtended(m_myCoutStream);
1275  m_myCoutStream << "\n Emul: ";
1276  fdlBlockEmul.printGtDecisionWordExtended(m_myCoutStream);
1277  m_myCoutStream << "\n";
1278 
1279  if (matchBxInEvent && validBxInEvent) {
1280  m_fdlDataEmul[histIndex][iRec]->Fill(8);
1281  } else {
1282  m_fdlDataEmul_Err[iRec]->Fill(8);
1283  }
1284 
1285  }
1286 
1287  // get NoAlgo
1288  const boost::uint16_t noAlgoData = fdlBlockData.noAlgo();
1289  const boost::uint16_t noAlgoEmul = fdlBlockEmul.noAlgo();
1290 
1291  if (noAlgoData == noAlgoEmul) {
1292  m_myCoutStream << "\n" << recString
1293  << " Data and emulated FDL noAlgo identical.";
1294  m_myCoutStream << "\n noAlgo() = " << noAlgoData;
1295  m_myCoutStream << "\n";
1296 
1297  } else {
1298  m_myCoutStream << "\n" << recString
1299  << " Data and emulated FDL noAlgo different.";
1300  m_myCoutStream << "\n Data: noAlgo() = " << noAlgoData;
1301  m_myCoutStream << "\n Emul: noAlgo() = " << noAlgoEmul;
1302  m_myCoutStream << "\n";
1303 
1304  if (matchBxInEvent && validBxInEvent) {
1305  m_fdlDataEmul[histIndex][iRec]->Fill(9);
1306  } else {
1307  m_fdlDataEmul_Err[iRec]->Fill(9);
1308  }
1309 
1310  }
1311 
1312  // get "Final OR" bits
1313  const boost::uint16_t finalORData = fdlBlockData.finalOR();
1314  const boost::uint16_t finalOREmul = fdlBlockEmul.finalOR();
1315 
1316  if (finalORData == finalOREmul) {
1317  m_myCoutStream << "\n" << recString
1318  << " Data and emulated FDL finalOR identical.";
1319  m_myCoutStream << "\n finalOR() = " << std::hex << "0x" << std::setw(2)
1320  << std::setfill('0') << finalORData << std::setfill(' ')
1321  << std::dec;
1322  m_myCoutStream << "\n";
1323 
1324  } else {
1325  m_myCoutStream << "\n" << recString
1326  << " Data and emulated FDL finalOR different.";
1327  m_myCoutStream << "\n Data: finalOR() = " << std::hex << "0x"
1328  << std::setw(2) << std::setfill('0') << finalORData
1329  << std::setfill(' ') << std::dec;
1330  m_myCoutStream << "\n Emul: finalOR() = " << std::hex << "0x"
1331  << std::setw(2) << std::setfill('0') << finalOREmul
1332  << std::setfill(' ') << std::dec;
1333  m_myCoutStream << "\n";
1334 
1335  if (matchBxInEvent && validBxInEvent) {
1336  m_fdlDataEmul[histIndex][iRec]->Fill(10);
1337  } else {
1338  m_fdlDataEmul_Err[iRec]->Fill(10);
1339  }
1340 
1341  }
1342 
1343  // get "Final OR" for physics partition
1344  const int finalORPhysData = finalORData & (1 << PhysicsPartition);
1345  const int finalORPhysEmul = finalOREmul & (1 << PhysicsPartition);
1346 
1347  if (finalORPhysData == finalORPhysEmul) {
1348  m_myCoutStream << "\n" << recString
1349  << " Data and emulated FDL finalOR for the physics partition identical.";
1350  m_myCoutStream << "\n finalOR() = " << finalORPhysData;
1351  m_myCoutStream << "\n";
1352 
1353  } else {
1354  m_myCoutStream << "\n" << recString
1355  << " Data and emulated FDL finalOR for the physics partition different.";
1356  m_myCoutStream << "\n Data: finalOR() = " << finalORPhysData;
1357  m_myCoutStream << "\n Emul: finalOR() = " << finalORPhysEmul;
1358  m_myCoutStream << "\n";
1359 
1360  if (matchBxInEvent && validBxInEvent) {
1361  m_fdlDataEmul[histIndex][iRec]->Fill(11);
1362  } else {
1363  m_fdlDataEmul_Err[iRec]->Fill(11);
1364  }
1365 
1366  }
1367 
1368  // get local bunch cross number of the actual bx
1369  const boost::uint16_t localBxNrData = fdlBlockData.localBxNr();
1370  const boost::uint16_t localBxNrEmul = fdlBlockEmul.localBxNr();
1371 
1372  if (localBxNrData == localBxNrEmul) {
1373  m_myCoutStream << "\n" << recString
1374  << " Data and emulated FDL localBxNr identical.";
1375  m_myCoutStream << "\n localBxNr() = " << localBxNrData;
1376  m_myCoutStream << "\n";
1377 
1378  } else {
1379  m_myCoutStream << "\n" << recString
1380  << " Data and emulated FDL localBxNr different.";
1381  m_myCoutStream << "\n Data: localBxNr() = " << localBxNrData;
1382  m_myCoutStream << "\n Emul: localBxNr() = " << localBxNrEmul;
1383  m_myCoutStream << "\n";
1384 
1385  if (matchBxInEvent && validBxInEvent) {
1386  m_fdlDataEmul[histIndex][iRec]->Fill(12);
1387  } else {
1388  m_fdlDataEmul_Err[iRec]->Fill(12);
1389  }
1390 
1391  }
1392 
1393  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1394  m_myCoutStream.str("");
1395  m_myCoutStream.clear();
1396 
1397 }
1398 
1399 //compare the PSB board
1400 void L1GtHwValidation::comparePSB(const edm::Event& iEvent,
1401  const edm::EventSetup& evSetup, const L1GtPsbWord& psbBlockData,
1402  const L1GtPsbWord& psbBlockEmul) {
1403 
1404  if (psbBlockData == psbBlockEmul) {
1405  m_myCoutStream << "\nData and emulated PSB blocks: identical.\n";
1406  psbBlockData.print(m_myCoutStream);
1407 
1408  } else {
1409  m_myCoutStream << "\nData and emulated PSB blocks: different.\n";
1410 
1411  m_myCoutStream << "\nData: PSB block\n";
1412  psbBlockData.print(m_myCoutStream);
1413 
1414  m_myCoutStream << "\nEmul: PSB block\n";
1415  psbBlockEmul.print(m_myCoutStream);
1416 
1417  }
1418 
1419  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1420 
1421  m_myCoutStream.str("");
1422  m_myCoutStream.clear();
1423 
1424  // get BoardId value
1425  const boost::uint16_t boardIdData = psbBlockData.boardId();
1426  const boost::uint16_t boardIdEmul = psbBlockEmul.boardId();
1427 
1428  if (boardIdData == boardIdEmul) {
1429  m_myCoutStream << "\nData and emulated PSB boardId identical.";
1430  m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4)
1431  << std::setfill('0') << boardIdData << std::setfill(' ')
1432  << std::dec;
1433  m_myCoutStream << "\n";
1434 
1435  } else {
1436  m_myCoutStream << "\nData and emulated PSB boardId different.";
1437  m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x"
1438  << std::setw(4) << std::setfill('0') << boardIdData
1439  << std::setfill(' ') << std::dec;
1440  m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x"
1441  << std::setw(4) << std::setfill('0') << boardIdEmul
1442  << std::setfill(' ') << std::dec;
1443  m_myCoutStream << "\n";
1444 
1445  }
1446 
1447  // get bunch cross in the GT event record
1448  const int bxInEventData = psbBlockData.bxInEvent();
1449  const int bxInEventEmul = psbBlockEmul.bxInEvent();
1450 
1451  if (bxInEventData == bxInEventEmul) {
1452  m_myCoutStream << "\nData and emulated PSB bxInEvent identical.";
1453  m_myCoutStream << "\n bxInEvent() = " << bxInEventData;
1454  m_myCoutStream << "\n";
1455 
1456  } else {
1457  m_myCoutStream << "\nData and emulated PSB bxInEvent different.";
1458  m_myCoutStream << "\n Data: bxInEvent() = " << bxInEventData;
1459  m_myCoutStream << "\n Emul: bxInEvent() = " << bxInEventEmul;
1460  m_myCoutStream << "\n";
1461 
1462  }
1463 
1464  // get BxNr - bunch cross number of the actual bx
1465  const boost::uint16_t bxNrData = psbBlockData.bxNr();
1466  const boost::uint16_t bxNrEmul = psbBlockEmul.bxNr();
1467 
1468  if (bxNrData == bxNrEmul) {
1469  m_myCoutStream << "\nData and emulated PSB bxNr identical.";
1470  m_myCoutStream << "\n bxNr() = " << bxNrData;
1471  m_myCoutStream << "\n";
1472 
1473  } else {
1474  m_myCoutStream << "\nData and emulated PSB bxNr different.";
1475  m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
1476  m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
1477  m_myCoutStream << "\n";
1478 
1479  }
1480 
1481  // get event number since last L1 reset generated in FDL
1482  const boost::uint32_t eventNrData = psbBlockData.eventNr();
1483  const boost::uint32_t eventNrEmul = psbBlockEmul.eventNr();
1484 
1485  if (eventNrData == eventNrEmul) {
1486  m_myCoutStream << "\nData and emulated PSB eventNr identical.";
1487  m_myCoutStream << "\n eventNr() = " << eventNrData;
1488  m_myCoutStream << "\n";
1489 
1490  } else {
1491  m_myCoutStream << "\nData and emulated PSB eventNr different.";
1492  m_myCoutStream << "\n Data: eventNr() = " << eventNrData;
1493  m_myCoutStream << "\n Emul: eventNr() = " << eventNrEmul;
1494  m_myCoutStream << "\n";
1495 
1496  }
1497 
1499  boost::uint16_t valData;
1500  boost::uint16_t valEmul;
1501 
1502  for (int iA = 0; iA < psbBlockData.NumberAData; ++iA) {
1503  valData = psbBlockData.aData(iA);
1504  valEmul = psbBlockEmul.aData(iA);
1505 
1506  if (valData == valEmul) {
1507  m_myCoutStream << "\nData and emulated PSB aData(" << iA
1508  << ") identical.";
1509  m_myCoutStream << "\n aData(iA) = " << std::hex << "0x"
1510  << std::setw(4) << std::setfill('0') << valData
1511  << std::setfill(' ') << std::dec;
1512  m_myCoutStream << "\n";
1513 
1514  } else {
1515  m_myCoutStream << "\nData and emulated PSB aData(" << iA
1516  << ") different.";
1517  m_myCoutStream << "\n Data: aData(iA) = " << std::hex << "0x"
1518  << std::setw(4) << std::setfill('0') << valData
1519  << std::setfill(' ') << std::dec;
1520  m_myCoutStream << "\n Emul: aData(iA) = " << std::hex << "0x"
1521  << std::setw(4) << std::setfill('0') << valEmul
1522  << std::setfill(' ') << std::dec;
1523  m_myCoutStream << "\n";
1524 
1525  }
1526 
1527  }
1528 
1530  for (int iB = 0; iB < psbBlockData.NumberBData; ++iB) {
1531  valData = psbBlockData.bData(iB);
1532  valEmul = psbBlockEmul.bData(iB);
1533 
1534  if (valData == valEmul) {
1535  m_myCoutStream << "\nData and emulated PSB bData(" << iB
1536  << ") identical.";
1537  m_myCoutStream << "\n bData(iA) = " << std::hex << "0x"
1538  << std::setw(4) << std::setfill('0') << valData
1539  << std::setfill(' ') << std::dec;
1540  m_myCoutStream << "\n";
1541 
1542  } else {
1543  m_myCoutStream << "\nData and emulated PSB bData(" << iB
1544  << ") different.";
1545  m_myCoutStream << "\n Data: bData(iA) = " << std::hex << "0x"
1546  << std::setw(4) << std::setfill('0') << valData
1547  << std::setfill(' ') << std::dec;
1548  m_myCoutStream << "\n Emul: bData(iA) = " << std::hex << "0x"
1549  << std::setw(4) << std::setfill('0') << valEmul
1550  << std::setfill(' ') << std::dec;
1551  m_myCoutStream << "\n";
1552 
1553  }
1554 
1555  }
1556 
1557  // get local bunch cross number of the actual bx
1558  const boost::uint16_t localBxNrData = psbBlockData.localBxNr();
1559  const boost::uint16_t localBxNrEmul = psbBlockEmul.localBxNr();
1560 
1561  if (localBxNrData == localBxNrEmul) {
1562  m_myCoutStream << "\nData and emulated PSB localBxNr identical.";
1563  m_myCoutStream << "\n localBxNr() = " << localBxNrData;
1564  m_myCoutStream << "\n";
1565 
1566  } else {
1567  m_myCoutStream << "\nData and emulated PSB localBxNr different.";
1568  m_myCoutStream << "\n Data: localBxNr() = " << localBxNrData;
1569  m_myCoutStream << "\n Emul: localBxNr() = " << localBxNrEmul;
1570  m_myCoutStream << "\n";
1571 
1572  }
1573 
1574  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1575  m_myCoutStream.str("");
1576  m_myCoutStream.clear();
1577 
1578 }
1579 
1580 //compare the TCS board
1581 void L1GtHwValidation::compareTCS(const edm::Event& iEvent,
1582  const edm::EventSetup& evSetup, const L1TcsWord&, const L1TcsWord&) {
1583  // empty
1584 }
1585 
1586 //L1 GT DAQ record comparison
1587 void L1GtHwValidation::compareDaqRecord(const edm::Event& iEvent,
1588  const edm::EventSetup& evSetup) {
1589 
1590  // formal index for DAQ record
1591  int iRec = 0;
1592 
1593  // reset the flags - they are used for DAQ recor only
1594  m_agree = true;
1595  m_dataOnly = false;
1596  m_emulOnly = false;
1597  m_dataOnlyMask = false;
1598  m_emulOnlyMask = false;
1599 
1600 
1601  // get the L1 GT hardware DAQ record L1GlobalTriggerReadoutRecord
1602  edm::Handle<L1GlobalTriggerReadoutRecord> gtReadoutRecordData;
1603  iEvent.getByToken(m_l1GtDataDaqInputToken_, gtReadoutRecordData);
1604 
1605  bool validData = false;
1606 
1607  if (!gtReadoutRecordData.isValid()) {
1608  m_nrDataEventError++;
1609  } else {
1610  validData = true;
1611  }
1612 
1613  // get the L1 GT emulator DAQ record L1GlobalTriggerReadoutRecord
1614  edm::Handle<L1GlobalTriggerReadoutRecord> gtReadoutRecordEmul;
1615  iEvent.getByToken(m_l1GtEmulDaqInputToken_, gtReadoutRecordEmul);
1616 
1617  bool validEmul = false;
1618 
1619  if (!gtReadoutRecordEmul.isValid()) {
1620  m_nrEmulEventError++;
1621  } else {
1622  validEmul = true;
1623  }
1624 
1625  if ((!validData) || (!validEmul)) {
1626  edm::LogWarning("L1GtHwValidation")
1627  << "\n No valid product found: DAQ L1GlobalTriggerReadoutRecord"
1628  << "\n Data validity [1 = true; 0 = false]: " << validData
1629  << "\n Emulator validity: [1 = true; 0 = false]: "
1630  << validEmul << "\n DAQ histograms will not be filled.\n"
1631  << std::endl;
1632 
1633  return;
1634  }
1635 
1636  // compare GTFE
1637  const L1GtfeWord& gtfeBlockData = gtReadoutRecordData->gtfeWord();
1638  const L1GtfeWord& gtfeBlockEmul = gtReadoutRecordEmul->gtfeWord();
1639 
1640  compareGTFE(iEvent, evSetup, gtfeBlockData, gtfeBlockEmul, iRec);
1641 
1642  // FDL comparison
1643  const std::vector<L1GtFdlWord>& gtFdlVectorData =
1644  gtReadoutRecordData->gtFdlVector();
1645  const std::vector<L1GtFdlWord>& gtFdlVectorEmul =
1646  gtReadoutRecordEmul->gtFdlVector();
1647 
1648  int gtFdlVectorDataSize = gtFdlVectorData.size();
1649  int gtFdlVectorEmulSize = gtFdlVectorEmul.size();
1650 
1651  if (gtFdlVectorDataSize == gtFdlVectorEmulSize) {
1652  m_myCoutStream << "\nData and emulated FDL vector size: identical.\n";
1653  m_myCoutStream << " Size: " << gtFdlVectorDataSize << std::endl;
1654 
1655  for (int iFdl = 0; iFdl < gtFdlVectorDataSize; ++iFdl) {
1656 
1657  const L1GtFdlWord& fdlBlockData = gtFdlVectorData[iFdl];
1658  const L1GtFdlWord& fdlBlockEmul = gtFdlVectorEmul[iFdl];
1659 
1660  compareFDL(iEvent, evSetup, fdlBlockData, fdlBlockEmul, iRec);
1661  }
1662  } else {
1663  m_myCoutStream << "\nData and emulated FDL vector size: different.\n";
1664  m_myCoutStream << " Data: size = " << gtFdlVectorDataSize << std::endl;
1665  m_myCoutStream << " Emul: size = " << gtFdlVectorEmulSize << std::endl;
1666 
1667  }
1668 
1669  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1670 
1671  m_myCoutStream.str("");
1672  m_myCoutStream.clear();
1673 
1674  // PSB comparison
1675  const std::vector<L1GtPsbWord>& gtPsbVectorData =
1676  gtReadoutRecordData->gtPsbVector();
1677  const std::vector<L1GtPsbWord>& gtPsbVectorEmul =
1678  gtReadoutRecordEmul->gtPsbVector();
1679 
1680  int gtPsbVectorDataSize = gtPsbVectorData.size();
1681  int gtPsbVectorEmulSize = gtPsbVectorEmul.size();
1682 
1683  if (gtPsbVectorDataSize == gtPsbVectorEmulSize) {
1684  m_myCoutStream << "\nData and emulated PSB vector size: identical.\n";
1685  m_myCoutStream << " Size: " << gtPsbVectorDataSize << std::endl;
1686  } else {
1687  m_myCoutStream << "\nData and emulated PSB vector size: different.\n";
1688  m_myCoutStream << " Data: size = " << gtPsbVectorDataSize << std::endl;
1689  m_myCoutStream << " Emul: size = " << gtPsbVectorEmulSize << std::endl;
1690 
1691  }
1692 
1693  // the order of PSB block in the gtPsbVector is different in emulator and in data
1694  // in emulator: all active PSB in one BxInEvent, ordered L1A-1, L1A, L1A+1
1695  // in unpacker: every PSB in all BxInEvent
1696  for (int iPsb = 0; iPsb < gtPsbVectorDataSize; ++iPsb) {
1697 
1698  const L1GtPsbWord& psbBlockData = gtPsbVectorData[iPsb];
1699  const boost::uint16_t boardIdData = psbBlockData.boardId();
1700  const int bxInEventData = psbBlockData.bxInEvent();
1701 
1702  // search the corresponding PSB in the emulated record using the
1703  // BoardId and the BxInEvent
1704 
1705  bool foundPSB = false;
1706 
1707  for (int iPsbF = 0; iPsbF < gtPsbVectorEmulSize; ++iPsbF) {
1708 
1709  const L1GtPsbWord& psbBlockEmul = gtPsbVectorEmul[iPsbF];
1710  const boost::uint16_t boardIdEmul = psbBlockEmul.boardId();
1711  const int bxInEventEmul = psbBlockEmul.bxInEvent();
1712 
1713  if ((boardIdEmul == boardIdData)
1714  && (bxInEventData == bxInEventEmul)) {
1715 
1716  foundPSB = true;
1717 
1718  // compare the boards
1719  comparePSB(iEvent, evSetup, psbBlockData, psbBlockEmul);
1720  }
1721 
1722  }
1723 
1724  if (!foundPSB) {
1725  m_myCoutStream << "\nNo emulated PSB with boardId() = " << std::hex
1726  << "0x" << std::setw(4) << std::setfill('0') << boardIdData
1727  << std::setfill(' ') << std::dec << " and BxInEvent = "
1728  << bxInEventData << " was found";
1729 
1730  }
1731 
1732  }
1733 
1734  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1735 
1736  m_myCoutStream.str("");
1737  m_myCoutStream.clear();
1738 
1739  // fill the m_gtErrorFlag histogram (only for L1 GT DAQ record)
1740 
1741 
1742  if (m_dbe) {
1743  m_dbe->setCurrentFolder(m_dirName);
1744  }
1745 
1746 
1747  if (m_agree) {
1748  m_gtErrorFlag->Fill(0.0001);
1749  }
1750 
1751  if (m_dataOnly || m_dataOnlyMask) {
1752  m_gtErrorFlag->Fill(3.0001);
1753  }
1754 
1755  if (m_emulOnly || m_emulOnlyMask) {
1756  m_gtErrorFlag->Fill(4.0001);
1757  }
1758 
1759 }
1760 
1761 // L1 GT EVM record comparison
1762 void L1GtHwValidation::compareEvmRecord(const edm::Event& iEvent,
1763  const edm::EventSetup& evSetup) {
1764 
1765  // formal index for EVM record
1766  int iRec = 1;
1767 
1768  // get the L1 GT hardware EVM record L1GlobalTriggerEvmReadoutRecord
1769  edm::Handle<L1GlobalTriggerEvmReadoutRecord> gtReadoutRecordData;
1770  iEvent.getByToken(m_l1GtDataEvmInputToken_, gtReadoutRecordData);
1771 
1772  bool validData = false;
1773 
1774  if (!gtReadoutRecordData.isValid()) {
1775  m_nrDataEventError++;
1776  } else {
1777  validData = true;
1778  }
1779 
1780  // get the L1 GT emulator EVM record L1GlobalTriggerEvmReadoutRecord
1781  edm::Handle<L1GlobalTriggerEvmReadoutRecord> gtReadoutRecordEmul;
1782  iEvent.getByToken(m_l1GtEmulEvmInputToken_, gtReadoutRecordEmul);
1783 
1784  bool validEmul = false;
1785 
1786  if (!gtReadoutRecordEmul.isValid()) {
1787  m_nrEmulEventError++;
1788  } else {
1789  validEmul = true;
1790  }
1791 
1792  if ((!validData) || (!validEmul)) {
1793  edm::LogWarning("L1GtHwValidation")
1794  << "\n No valid product found: EVM L1GlobalTriggerEvmReadoutRecord"
1795  << "\n Data validity [1 = true; 0 = false]: " << validData
1796  << "\n Emulator validity: [1 = true; 0 = false]: "
1797  << validEmul << "\n EVM histograms will not be filled.\n"
1798  << std::endl;
1799 
1800  return;
1801  }
1802 
1803  // compare GTFE
1804  const L1GtfeWord& gtfeBlockData = gtReadoutRecordData->gtfeWord();
1805  const L1GtfeWord& gtfeBlockEmul = gtReadoutRecordEmul->gtfeWord();
1806 
1807  compareGTFE(iEvent, evSetup, gtfeBlockData, gtfeBlockEmul, iRec);
1808 
1809  // FDL comparison
1810  const std::vector<L1GtFdlWord>& gtFdlVectorData =
1811  gtReadoutRecordData->gtFdlVector();
1812  const std::vector<L1GtFdlWord>& gtFdlVectorEmul =
1813  gtReadoutRecordEmul->gtFdlVector();
1814 
1815  int gtFdlVectorDataSize = gtFdlVectorData.size();
1816  int gtFdlVectorEmulSize = gtFdlVectorEmul.size();
1817 
1818  if (gtFdlVectorDataSize == gtFdlVectorEmulSize) {
1819  m_myCoutStream << "\nData and emulated FDL vector size: identical.\n";
1820  m_myCoutStream << " Size: " << gtFdlVectorDataSize << std::endl;
1821 
1822  for (int iFdl = 0; iFdl < gtFdlVectorDataSize; ++iFdl) {
1823 
1824  const L1GtFdlWord& fdlBlockData = gtFdlVectorData[iFdl];
1825  const L1GtFdlWord& fdlBlockEmul = gtFdlVectorEmul[iFdl];
1826 
1827  compareFDL(iEvent, evSetup, fdlBlockData, fdlBlockEmul, iRec);
1828  }
1829  } else {
1830  m_myCoutStream << "\nData and emulated FDL vector size: different.\n";
1831  m_myCoutStream << " Data: size = " << gtFdlVectorDataSize << std::endl;
1832  m_myCoutStream << " Emul: size = " << gtFdlVectorEmulSize << std::endl;
1833 
1834  }
1835 
1836  // FIXME compare TCS
1837 
1838  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1839 
1840  m_myCoutStream.str("");
1841  m_myCoutStream.clear();
1842 
1843  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1844 
1845  m_myCoutStream.str("");
1846  m_myCoutStream.clear();
1847 
1848 }
1849 
1850 // compare the GCT collections obtained from L1 GT PSB with the input
1851 // GCT collections
1852 void L1GtHwValidation::compareGt_Gct(const edm::Event& iEvent,
1853  const edm::EventSetup&) {
1854 
1855  // FIXME
1856 
1857 }
1858 
1859 // analyze each event: event loop
1860 void L1GtHwValidation::analyze(const edm::Event& iEvent,
1861  const edm::EventSetup& evSetup) {
1862 
1863  ++m_nrEvJob;
1864  ++m_nrEvRun;
1865 
1866  // L1 GT DAQ record comparison
1867  compareDaqRecord(iEvent, evSetup);
1868 
1869  // L1 GT EVM record comparison
1870  compareEvmRecord(iEvent, evSetup);
1871 
1872  // GCT collections from L1 GT PSB versus unpacked GCT
1873  compareGt_Gct(iEvent, evSetup);
1874 
1875 }
1876 
1877 // book all histograms for the module
1878 void L1GtHwValidation::bookHistograms() {
1879 
1880  // histograms
1881 
1882  const unsigned int numberTechTriggers =
1883  L1GlobalTriggerReadoutSetup::NumberTechnicalTriggers;
1884 
1885  const unsigned int numberAlgoTriggers =
1886  L1GlobalTriggerReadoutSetup::NumberPhysTriggers;
1887 
1888  for (int iRec = 0; iRec < NumberOfGtRecords; ++iRec) {
1889 
1890  std::string recString;
1891  if (iRec == 0) {
1892  recString = "Daq_";
1893  if (m_dbe) {
1894  m_dbe->setCurrentFolder(m_dirName + "/DAQ/");
1895  }
1896 
1897  } else {
1898  recString = "Evm_";
1899  if (m_dbe) {
1900  m_dbe->setCurrentFolder(m_dirName + "/EVM/");
1901  }
1902  }
1903 
1904  std::string hName;
1905  const char* histName;
1906 
1907  hName = recString + "gtfeDataEmul";
1908  histName = hName.c_str();
1909 
1910  // GTFE histograms
1911  m_gtfeDataEmul[iRec] = m_dbe->book1D(histName,
1912  "GTFE data vs emul mismatch", 8, 0., 7.);
1913  m_gtfeDataEmul[iRec]->setBinLabel(1, "BoardId", 1);
1914  m_gtfeDataEmul[iRec]->setBinLabel(2, "RecordLength1", 1);
1915  m_gtfeDataEmul[iRec]->setBinLabel(3, "RecordLength0", 1);
1916  m_gtfeDataEmul[iRec]->setBinLabel(4, "BxNr", 1);
1917  m_gtfeDataEmul[iRec]->setBinLabel(5, "SetupVersion", 1);
1918  m_gtfeDataEmul[iRec]->setBinLabel(6, "DaqActiveBoards", 1);
1919  m_gtfeDataEmul[iRec]->setBinLabel(7, "AltNrBxBoard", 1);
1920  m_gtfeDataEmul[iRec]->setBinLabel(8, "TotalTriggerNr", 1);
1921 
1922  // FDL histograms
1923 
1924  for (int iHist = 0; iHist < TotalBxInEvent; ++iHist) {
1925 
1926  // convert [0, TotalBxInEvent] to [-X, +X] and add to histogram name
1927  int iIndex = iHist - ((TotalBxInEvent + 1) / 2 - 1);
1928  int hIndex = (iIndex + 16) % 16;
1929 
1930  std::stringstream ss;
1931  std::string str;
1932  ss << std::uppercase << std::hex << hIndex;
1933  ss >> str;
1934 
1935  if (iRec == 0) {
1936  if (m_dbe) {
1937  m_dbe->setCurrentFolder(m_dirName + "/DAQ/BxInEvent_" + str);
1938  }
1939 
1940  } else {
1941  if (m_dbe) {
1942  m_dbe->setCurrentFolder(m_dirName + "/EVM/BxInEvent_" + str);
1943  }
1944  }
1945 
1946  hName = recString + "FdlDataEmul_" + str;
1947  histName = hName.c_str();
1948 
1949  std::string hTitle = "FDL data vs emul mismatch for BxInEvent = "
1950  + str;
1951  const char* histTitle = hTitle.c_str();
1952 
1953  //
1954 
1955  m_fdlDataEmul[iHist][iRec] = m_dbe->book1D(histName, histTitle, 13,
1956  0., 13.);
1957  m_fdlDataEmul[iHist][iRec]->setBinLabel(1, "BoardId", 1);
1958  m_fdlDataEmul[iHist][iRec]->setBinLabel(2, "BxInEvent", 1);
1959  m_fdlDataEmul[iHist][iRec]->setBinLabel(3, "BxNr", 1);
1960  m_fdlDataEmul[iHist][iRec]->setBinLabel(4, "EventNr", 1);
1961  m_fdlDataEmul[iHist][iRec]->setBinLabel(5, "TechTrigger", 1);
1962  m_fdlDataEmul[iHist][iRec]->setBinLabel(6, "TechTriggerMask", 1);
1963  m_fdlDataEmul[iHist][iRec]->setBinLabel(7, "AlgoTrigger", 1);
1964  m_fdlDataEmul[iHist][iRec]->setBinLabel(8, "AlgoTriggerMask", 1);
1965  m_fdlDataEmul[iHist][iRec]->setBinLabel(9, "AlgoExtend", 1);
1966  m_fdlDataEmul[iHist][iRec]->setBinLabel(10, "NoAlgo", 1);
1967  m_fdlDataEmul[iHist][iRec]->setBinLabel(11, "FinalORAllParts", 1);
1968  m_fdlDataEmul[iHist][iRec]->setBinLabel(12, "FinalORPhysPart", 1);
1969  m_fdlDataEmul[iHist][iRec]->setBinLabel(13, "LocalBxNr", 1);
1970 
1971  // algorithm decision
1972  // data
1973  hName = recString + "Data_AlgoDecision_" + str;
1974  histName = hName.c_str();
1975 
1976  hTitle = "Data: algorithm decision word for BxInEvent = " + str;
1977  histTitle = hTitle.c_str();
1978 
1979  m_fdlDataAlgoDecision[iHist][iRec] = m_dbe->book1D(histName,
1980  histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
1981 
1982  // emul
1983  hName = recString + "Emul_AlgoDecision_" + str;
1984  histName = hName.c_str();
1985 
1986  hTitle = "Emul: algorithm decision word for BxInEvent = " + str;
1987  histTitle = hTitle.c_str();
1988 
1989  m_fdlEmulAlgoDecision[iHist][iRec] = m_dbe->book1D(histName,
1990  histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
1991 
1992  // algorithm decision for prescaled algorithms
1993  // data
1994  hName = recString + "Data_AlgoDecision_Prescaled_" + str;
1995  histName = hName.c_str();
1996 
1997  hTitle
1998  = "Data: prescaled algorithms: algorithm decision for BxInEvent = "
1999  + str;
2000  histTitle = hTitle.c_str();
2001 
2002  m_fdlDataAlgoDecisionPrescaled[iHist][iRec] = m_dbe->book1D(
2003  histName, histTitle, numberAlgoTriggers, 0.,
2004  numberAlgoTriggers);
2005 
2006  // emul
2007  hName = recString + "Emul_AlgoDecision_Prescaled_" + str;
2008  histName = hName.c_str();
2009 
2010  hTitle
2011  = "Emul: prescaled algorithms: algorithm decision for BxInEvent = "
2012  + str;
2013  histTitle = hTitle.c_str();
2014 
2015  m_fdlEmulAlgoDecisionPrescaled[iHist][iRec] = m_dbe->book1D(
2016  histName, histTitle, numberAlgoTriggers, 0.,
2017  numberAlgoTriggers);
2018 
2019  // algorithm decision for unprescaled algorithms
2020  // data
2021  hName = recString + "Data_AlgoDecision_Unprescaled_" + str;
2022  histName = hName.c_str();
2023 
2024  hTitle
2025  = "Data: unprescaled algorithms: algorithm decision for BxInEvent = "
2026  + str;
2027  histTitle = hTitle.c_str();
2028 
2029  m_fdlDataAlgoDecisionUnprescaled[iHist][iRec] = m_dbe->book1D(
2030  histName, histTitle, numberAlgoTriggers, 0.,
2031  numberAlgoTriggers);
2032 
2033  // emul
2034  hName = recString + "Emul_AlgoDecision_Unprescaled_" + str;
2035  histName = hName.c_str();
2036 
2037  hTitle
2038  = "Emul: unprescaled algorithms: algorithm decision for BxInEvent = "
2039  + str;
2040  histTitle = hTitle.c_str();
2041 
2042  m_fdlEmulAlgoDecisionUnprescaled[iHist][iRec] = m_dbe->book1D(
2043  histName, histTitle, numberAlgoTriggers, 0.,
2044  numberAlgoTriggers);
2045 
2046  // algorithm decision after masking (partition physics)
2047  // data
2048  hName = recString + "Data_AlgoDecisionAfterMask_" + str;
2049  histName = hName.c_str();
2050 
2051  hTitle
2052  = "Data, physics partition: algorithm decision word after mask for BxInEvent = "
2053  + str;
2054  histTitle = hTitle.c_str();
2055 
2056  m_fdlDataAlgoDecisionMask[iHist][iRec] = m_dbe->book1D(histName,
2057  histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
2058 
2059  // emul
2060  hName = recString + "Emul_AlgoDecisionAfterMask_" + str;
2061  histName = hName.c_str();
2062 
2063  hTitle
2064  = "Emul, physics partition: algorithm decision word after mask for BxInEvent = "
2065  + str;
2066  histTitle = hTitle.c_str();
2067 
2068  m_fdlEmulAlgoDecisionMask[iHist][iRec] = m_dbe->book1D(histName,
2069  histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
2070 
2071  //
2072  hName = recString + "DataEmul_AlgoDecision_" + str;
2073  histName = hName.c_str();
2074 
2075  hTitle
2076  = "Data vs emul: non-matching algorithm decision word for BxInEvent = "
2077  + str;
2078  histTitle = hTitle.c_str();
2079 
2080  m_fdlDataEmulAlgoDecision[iHist][iRec] = m_dbe->book1D(histName,
2081  histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
2082 
2083  //
2084  hName = recString + "DataEmul_AlgoDecision_Prescaled_" + str;
2085  histName = hName.c_str();
2086 
2087  hTitle
2088  = "Data vs emul: prescaled algorithms with non-matching decision for BxInEvent = "
2089  + str;
2090  histTitle = hTitle.c_str();
2091 
2092  m_fdlDataEmulAlgoDecisionPrescaled[iHist][iRec] = m_dbe->book1D(
2093  histName, histTitle, numberAlgoTriggers, 0.,
2094  numberAlgoTriggers);
2095 
2096  //
2097  hName = recString + "DataEmul_AlgoDecision_Unprescaled_" + str;
2098  histName = hName.c_str();
2099 
2100  hTitle
2101  = "Data vs emul: unprescaled algorithms with non-matching decision for BxInEvent = "
2102  + str;
2103  histTitle = hTitle.c_str();
2104 
2105  m_fdlDataEmulAlgoDecisionUnprescaled[iHist][iRec] = m_dbe->book1D(
2106  histName, histTitle, numberAlgoTriggers, 0.,
2107  numberAlgoTriggers);
2108 
2109  //
2110  hName = recString + "DataEmul_AlgoDecision_Unprescaled_Allowed_" + str;
2111  histName = hName.c_str();
2112 
2113  hTitle
2114  = "Data vs emul: unprescaled algorithms not excluded with non-matching decision for BxInEvent = "
2115  + str;
2116  histTitle = hTitle.c_str();
2117 
2118  m_fdlDataEmulAlgoDecisionUnprescaledAllowed[iHist][iRec] = m_dbe->book1D(
2119  histName, histTitle, numberAlgoTriggers, 0.,
2120  numberAlgoTriggers);
2121 
2122  //
2123  hName = recString + "Data_AlgoDecision_NoMatch_" + str;
2124  histName = hName.c_str();
2125 
2126  hTitle
2127  = "Data: algorithm decision for non-matching cases for BxInEvent = "
2128  + str;
2129  histTitle = hTitle.c_str();
2130 
2131  m_fdlDataAlgoDecision_NoMatch[iHist][iRec] = m_dbe->book1D(
2132  histName, histTitle, numberAlgoTriggers, 0.,
2133  numberAlgoTriggers);
2134 
2135  //
2136  hName = recString + "Emul_AlgoDecision_NoMatch_" + str;
2137  histName = hName.c_str();
2138 
2139  hTitle
2140  = "Emul: algorithm decision for non-matching cases for BxInEvent = "
2141  + str;
2142  histTitle = hTitle.c_str();
2143 
2144  m_fdlEmulAlgoDecision_NoMatch[iHist][iRec] = m_dbe->book1D(
2145  histName, histTitle, numberAlgoTriggers, 0.,
2146  numberAlgoTriggers);
2147 
2148  // prescaled algorithms
2149  hName = recString + "Data_AlgoDecision_Prescaled_NoMatch_" + str;
2150  histName = hName.c_str();
2151 
2152  hTitle
2153  = "Data: prescaled algorithms: non-matching algorithm decision for BxInEvent = "
2154  + str;
2155  histTitle = hTitle.c_str();
2156 
2157  m_fdlDataAlgoDecisionPrescaled_NoMatch[iHist][iRec]
2158  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2159  0., numberAlgoTriggers);
2160 
2161  //
2162  hName = recString + "Emul_AlgoDecision_Prescaled_NoMatch_" + str;
2163  histName = hName.c_str();
2164 
2165  hTitle
2166  = "Emul: prescaled algorithms: non-matching algorithm decision for BxInEvent = "
2167  + str;
2168  histTitle = hTitle.c_str();
2169 
2170  m_fdlEmulAlgoDecisionPrescaled_NoMatch[iHist][iRec]
2171  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2172  0., numberAlgoTriggers);
2173 
2174 
2175  // unprescaled algorithms - non-matching
2176  hName = recString + "Data_AlgoDecision_Unprescaled_NoMatch_" + str;
2177  histName = hName.c_str();
2178 
2179  hTitle
2180  = "Data: unprescaled algorithms: non-matching algorithm decision for BxInEvent = "
2181  + str;
2182  histTitle = hTitle.c_str();
2183 
2184  m_fdlDataAlgoDecisionUnprescaled_NoMatch[iHist][iRec]
2185  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2186  0., numberAlgoTriggers);
2187 
2188  //
2189  hName = recString + "Emul_AlgoDecision_Unprescaled_NoMatch_" + str;
2190  histName = hName.c_str();
2191 
2192  hTitle
2193  = "Emul: unprescaled algorithms: non-matching algorithm decision for BxInEvent = "
2194  + str;
2195  histTitle = hTitle.c_str();
2196 
2197  m_fdlEmulAlgoDecisionUnprescaled_NoMatch[iHist][iRec]
2198  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2199  0., numberAlgoTriggers);
2200 
2201 
2202 
2203  //
2204  hName = recString + "Data_AlgoDecisionMask_NoMatch_" + str;
2205  histName = hName.c_str();
2206 
2207  hTitle
2208  = "Data: algorithm decision for non-matching cases after mask for BxInEvent = "
2209  + str;
2210  histTitle = hTitle.c_str();
2211 
2212  m_fdlDataAlgoDecisionMask_NoMatch[iHist][iRec] = m_dbe->book1D(
2213  histName, histTitle, numberAlgoTriggers, 0.,
2214  numberAlgoTriggers);
2215 
2216  //
2217  hName = recString + "Emul_AlgoDecisionMask_NoMatch_" + str;
2218  histName = hName.c_str();
2219 
2220  hTitle
2221  = "Emul: algorithm decision for non-matching cases after mask for BxInEvent = "
2222  + str;
2223  histTitle = hTitle.c_str();
2224 
2225  m_fdlEmulAlgoDecisionMask_NoMatch[iHist][iRec] = m_dbe->book1D(
2226  histName, histTitle, numberAlgoTriggers, 0.,
2227  numberAlgoTriggers);
2228 
2229  // prescaled algorithms
2230  hName = recString + "Data_AlgoDecisionMask_Prescaled_NoMatch_" + str;
2231  histName = hName.c_str();
2232 
2233  hTitle
2234  = "Data: prescaled algorithms: non-matching algorithm decision after mask for BxInEvent = "
2235  + str;
2236  histTitle = hTitle.c_str();
2237 
2238  m_fdlDataAlgoDecisionPrescaledMask_NoMatch[iHist][iRec]
2239  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2240  0., numberAlgoTriggers);
2241 
2242  //
2243  hName = recString + "Emul_AlgoDecision_PrescaledMask_NoMatch_" + str;
2244  histName = hName.c_str();
2245 
2246  hTitle
2247  = "Emul: prescaled algorithms: non-matching algorithm decision after mask for BxInEvent = "
2248  + str;
2249  histTitle = hTitle.c_str();
2250 
2251  m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[iHist][iRec]
2252  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2253  0., numberAlgoTriggers);
2254 
2255 
2256  // unprescaled algorithms - non-matching
2257  hName = recString + "Data_AlgoDecision_UnprescaledMask_NoMatch_" + str;
2258  histName = hName.c_str();
2259 
2260  hTitle
2261  = "Data: unprescaled algorithms: non-matching algorithm decision after mask for BxInEvent = "
2262  + str;
2263  histTitle = hTitle.c_str();
2264 
2265  m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[iHist][iRec]
2266  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2267  0., numberAlgoTriggers);
2268 
2269  //
2270  hName = recString + "Emul_AlgoDecision_UnprescaledMask_NoMatch_" + str;
2271  histName = hName.c_str();
2272 
2273  hTitle
2274  = "Emul: unprescaled algorithms: non-matching algorithm decision after mask for BxInEvent = "
2275  + str;
2276  histTitle = hTitle.c_str();
2277 
2278  m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[iHist][iRec]
2279  = m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
2280  0., numberAlgoTriggers);
2281 
2282 
2283 
2284  //
2285  hName = recString + "DataEmul_AlgoDecisionAfterMask_" + str;
2286  histName = hName.c_str();
2287 
2288  hTitle
2289  = "Data vs emul, physics partition: non-matching algorithm decision word after mask for BxInEvent = "
2290  + str;
2291  histTitle = hTitle.c_str();
2292 
2293  m_fdlDataEmulAlgoDecisionMask[iHist][iRec] = m_dbe->book1D(
2294  histName, histTitle, numberAlgoTriggers, 0.,
2295  numberAlgoTriggers);
2296 
2297  // technical trigger decision
2298  // data
2299  hName = recString + "Data_TechDecision_" + str;
2300  histName = hName.c_str();
2301 
2302  hTitle = "Data technical trigger decision word for BxInEvent = "
2303  + str;
2304  histTitle = hTitle.c_str();
2305 
2306  m_fdlDataTechDecision[iHist][iRec] = m_dbe->book1D(histName,
2307  histTitle, numberTechTriggers, 0., numberTechTriggers);
2308 
2309  // emul
2310  hName = recString + "Emul_TechDecision_" + str;
2311  histName = hName.c_str();
2312 
2313  hTitle = "Emul: technical trigger decision word for BxInEvent = "
2314  + str;
2315  histTitle = hTitle.c_str();
2316 
2317  m_fdlEmulTechDecision[iHist][iRec] = m_dbe->book1D(histName,
2318  histTitle, numberTechTriggers, 0., numberTechTriggers);
2319 
2320  // technical trigger decision after masking (partition physics)
2321  hName = recString + "Data_TechDecisionAfterMask_" + str;
2322  histName = hName.c_str();
2323 
2324  hTitle
2325  = "Data technical trigger decision word after mask for BxInEvent = "
2326  + str;
2327  histTitle = hTitle.c_str();
2328 
2329  m_fdlDataTechDecisionMask[iHist][iRec] = m_dbe->book1D(histName,
2330  histTitle, numberTechTriggers, 0., numberTechTriggers);
2331 
2332  //
2333  hName = recString + "Emul_TechDecisionAfterMask_" + str;
2334  histName = hName.c_str();
2335 
2336  hTitle
2337  = "Emul: technical trigger decision word after mask for BxInEvent = "
2338  + str;
2339  histTitle = hTitle.c_str();
2340 
2341  m_fdlEmulTechDecisionMask[iHist][iRec] = m_dbe->book1D(histName,
2342  histTitle, numberTechTriggers, 0., numberTechTriggers);
2343 
2344  //
2345  hName = recString + "DataEmul_TechDecision_" + str;
2346  histName = hName.c_str();
2347 
2348  hTitle
2349  = "Data vs emul: non-matching technical trigger decision word for BxInEvent = "
2350  + str;
2351  histTitle = hTitle.c_str();
2352 
2353  m_fdlDataEmulTechDecision[iHist][iRec] = m_dbe->book1D(histName,
2354  histTitle, numberTechTriggers, 0., numberTechTriggers);
2355 
2356  hName = recString + "DataEmul_TechDecisionAfterMask_" + str;
2357  histName = hName.c_str();
2358 
2359  hTitle
2360  = "Data vs emul: non-matching technical trigger decision word after mask for BxInEvent = "
2361  + str;
2362  histTitle = hTitle.c_str();
2363 
2364  m_fdlDataEmulTechDecisionMask[iHist][iRec] = m_dbe->book1D(
2365  histName, histTitle, numberTechTriggers, 0.,
2366  numberTechTriggers);
2367 
2368  }
2369 
2370  if (iRec == 0) {
2371  if (m_dbe) {
2372  m_dbe->setCurrentFolder(m_dirName + "/DAQ/");
2373  }
2374 
2375  } else {
2376  if (m_dbe) {
2377  m_dbe->setCurrentFolder(m_dirName + "/EVM/");
2378  }
2379  }
2380 
2381  hName = recString + "FdlDataEmul_Err";
2382  histName = hName.c_str();
2383 
2384  m_fdlDataEmul_Err[iRec]
2385  = m_dbe->book1D(
2386  histName,
2387  "FDL data vs emul mismatch for non-matching BxInEvent in FDL payload",
2388  13, 0., 13.);
2389  m_fdlDataEmul_Err[iRec]->setBinLabel(1, "BoardId", 1);
2390  m_fdlDataEmul_Err[iRec]->setBinLabel(2, "BxInEvent", 1);
2391  m_fdlDataEmul_Err[iRec]->setBinLabel(3, "BxNr", 1);
2392  m_fdlDataEmul_Err[iRec]->setBinLabel(4, "EventNr", 1);
2393  m_fdlDataEmul_Err[iRec]->setBinLabel(5, "TechTrigger", 1);
2394  m_fdlDataEmul_Err[iRec]->setBinLabel(6, "TechTriggerMask", 1);
2395  m_fdlDataEmul_Err[iRec]->setBinLabel(7, "AlgoTrigger", 1);
2396  m_fdlDataEmul_Err[iRec]->setBinLabel(8, "AlgoTriggerMask", 1);
2397  m_fdlDataEmul_Err[iRec]->setBinLabel(9, "AlgoExtend", 1);
2398  m_fdlDataEmul_Err[iRec]->setBinLabel(10, "NoAlgo", 1);
2399  m_fdlDataEmul_Err[iRec]->setBinLabel(11, "FinalORAllParts", 1);
2400  m_fdlDataEmul_Err[iRec]->setBinLabel(12, "FinalORPhysPart", 1);
2401  m_fdlDataEmul_Err[iRec]->setBinLabel(13, "LocalBxNr", 1);
2402 
2403  hName = recString + "FdlDataAlgoDecision_Err";
2404  histName = hName.c_str();
2405 
2406  m_fdlDataAlgoDecision_Err[iRec]
2407  = m_dbe->book1D(
2408  histName,
2409  "Data: algorithm trigger decision word, non-matching BxInEvent",
2410  numberAlgoTriggers, 0., numberAlgoTriggers);
2411 
2412  //
2413  hName = recString + "Emul_AlgoDecision_Err";
2414  histName = hName.c_str();
2415 
2416  m_fdlEmulAlgoDecision_Err[iRec]
2417  = m_dbe->book1D(
2418  histName,
2419  "Emul: algorithm trigger decision word, non-matching BxInEvent",
2420  numberAlgoTriggers, 0., numberAlgoTriggers);
2421 
2422  hName = recString + "DataEmul_AlgoDecision_Err";
2423  histName = hName.c_str();
2424 
2425  m_fdlDataEmulAlgoDecision_Err[iRec]
2426  = m_dbe->book1D(
2427  histName,
2428  "Data vs emul: algorithm trigger decision word, non-matching BxInEvent",
2429  numberAlgoTriggers, 0., numberAlgoTriggers);
2430 
2431  //
2432  hName = recString + "Data_TechDecision_Err";
2433  histName = hName.c_str();
2434 
2435  m_fdlDataTechDecision_Err[iRec]
2436  = m_dbe->book1D(
2437  histName,
2438  "Data: technical trigger decision word, non-matching BxInEvent",
2439  numberTechTriggers, 0., numberTechTriggers);
2440 
2441  hName = recString + "Emul_TechDecision_Err";
2442  histName = hName.c_str();
2443 
2444  m_fdlEmulTechDecision_Err[iRec]
2445  = m_dbe->book1D(
2446  histName,
2447  "Emul: technical trigger decision word, non-matching BxInEvent",
2448  numberTechTriggers, 0., numberTechTriggers);
2449 
2450  hName = recString + "DataEmul_TechDecision_Err";
2451  histName = hName.c_str();
2452 
2453  m_fdlDataEmulTechDecision_Err[iRec]
2454  = m_dbe->book1D(
2455  histName,
2456  "Data vs emul: technical trigger decision word, non-matching BxInEvent",
2457  numberTechTriggers, 0., numberTechTriggers);
2458 
2459  }
2460 
2461  if (m_dbe) {
2462  m_dbe->setCurrentFolder(m_dirName);
2463  }
2464 
2465  //
2466  m_excludedAlgorithmsAgreement = m_dbe->book1D(
2467  "ExcludedAlgorithmsFromAgreement",
2468  "Algorithms excluded from data versus emulator agreement flag",
2469  numberAlgoTriggers, 0., numberAlgoTriggers);
2470 
2471  //
2472 
2473  m_gtErrorFlag = m_dbe->book1D("GTErrorFlag",
2474  "L1 GT error flag for data versus emulator comparison", 5, 0., 5);
2475 
2476  m_gtErrorFlag->setBinLabel(1, "Agree", 1);
2477  m_gtErrorFlag->setBinLabel(2, "", 1);
2478  m_gtErrorFlag->setBinLabel(3, "", 1);
2479  m_gtErrorFlag->setBinLabel(4, "Data only", 1);
2480  m_gtErrorFlag->setBinLabel(5, "Emul only", 1);
2481 
2482 
2483 }
2484 
2485 bool L1GtHwValidation::matchCondCategory(
2486  const L1GtConditionCategory& conditionCategory,
2487  const L1GtConditionCategory& excludedCategory) {
2488 
2489  bool matchValue = false;
2490 
2491  if (excludedCategory == CondNull) {
2492  matchValue = true;
2493  } else {
2494  if (conditionCategory == excludedCategory) {
2495  matchValue = true;
2496  }
2497  }
2498 
2499  return matchValue;
2500 }
2501 
2502 
2503 bool L1GtHwValidation::matchCondType(const L1GtConditionType& conditionType,
2504  const L1GtConditionType& excludedType) {
2505 
2506  bool matchValue = false;
2507 
2508  if (excludedType == TypeNull) {
2509  matchValue = true;
2510  } else {
2511  if (conditionType == excludedType) {
2512  matchValue = true;
2513  }
2514  }
2515 
2516  return matchValue;
2517 }
2518 
2519 
2520 bool L1GtHwValidation::matchCondL1GtObject(
2521  const std::vector<L1GtObject>& condObjects,
2522  const L1GtObject& excludedObject) {
2523 
2524  bool matchValue = false;
2525 
2526  if (excludedObject == ObjNull) {
2527 
2528  matchValue = true;
2529 
2530  } else {
2531 
2532  for (std::vector<L1GtObject>::const_iterator itCondObj =
2533  condObjects.begin(); itCondObj != condObjects.end(); ++itCondObj) {
2534 
2535  if ((*itCondObj) == excludedObject) {
2536 
2537  matchValue = true;
2538 
2539  }
2540  }
2541  }
2542 
2543  return matchValue;
2544 
2545 }
2546 
2547 
2548 void L1GtHwValidation::excludedAlgoList() {
2549 
2550 
2551  const AlgorithmMap& algorithmMap = m_l1GtMenu->gtAlgorithmMap();
2552  (const_cast<L1GtTriggerMenu*> (m_l1GtMenu))->buildGtConditionMap(); //...ugly
2553 
2554  for (CItAlgo itAlgo = algorithmMap.begin(); itAlgo != algorithmMap.end(); itAlgo++) {
2555 
2556  const std::string& algName = itAlgo->first;
2557  const int algBitNumber = (itAlgo->second).algoBitNumber();
2558  const int chipNr = (itAlgo->second).algoChipNumber();
2559 
2560  const ConditionMap& conditionMap = (m_l1GtMenu->gtConditionMap()).at(
2561  chipNr);
2562 
2563  const std::vector<L1GtLogicParser::TokenRPN>& aRpnVector =
2564  (itAlgo->second).algoRpnVector();
2565  size_t aRpnVectorSize = aRpnVector.size();
2566 
2567  bool algWithExcludedCondition = false;
2568  bool algWithConditionNotInMap = false;
2569 
2570  // loop over RpnVector and check each conditions against list of excluded conditions
2571  for (size_t opI = 0; opI < aRpnVectorSize; ++opI) {
2572 
2573  const std::string& cndName = (aRpnVector[opI]).operand;
2574 
2575  if (!cndName.empty()) {
2576  bool foundCond = false;
2577 
2578  CItCond itCond = conditionMap.find(cndName);
2579  if (itCond != conditionMap.end()) {
2580 
2581  const L1GtConditionCategory& cCateg = (itCond->second)->condCategory();
2582  const L1GtConditionType& cType = (itCond->second)->condType();
2583  const std::vector<L1GtObject>& objType = (itCond->second)->objectType();
2584 
2585  // condition index in the m_excludedCondCategory, m_excludedCondType, m_excludedL1GtObject vectors
2586  int iCond = -1;
2587 
2588  for (std::vector<L1GtConditionCategory>::const_iterator
2589  itCateg = m_excludedCondCategory.begin();
2590  itCateg != m_excludedCondCategory.end(); ++itCateg) {
2591 
2592  iCond++;
2593 
2594  bool matchCondCategoryValue = matchCondCategory(cCateg, (*itCateg));
2595  bool matchCondTypeValue = matchCondType(cType, m_excludedCondType.at(iCond));
2596  bool matchCondL1GtObjectValue = matchCondL1GtObject(objType, m_excludedL1GtObject.at(iCond));
2597 
2598  LogTrace("L1GtHwValidation")
2599  << "\n "
2600  << "Algorithm: " << algName
2601  << " Condition: " << cndName
2602  << "\n "
2603  << "Category: " << l1GtConditionCategoryEnumToString(cCateg)
2604  << "; excluded: " << l1GtConditionCategoryEnumToString((*itCateg))
2605  << "\n "
2606  << "Type: " << l1GtConditionTypeEnumToString(cType)
2607  << "; excluded: " << l1GtConditionTypeEnumToString(m_excludedCondType.at(iCond))
2608  << "\n "
2609  << "Object excluded: " << l1GtObjectEnumToString(m_excludedL1GtObject.at(iCond))
2610  << std::endl;
2611 
2612 
2613  if (matchCondCategoryValue && matchCondTypeValue && matchCondL1GtObjectValue) {
2614 
2615  algWithExcludedCondition = true;
2616 
2617  }
2618 
2619  }
2620 
2621  foundCond = true;
2622  }
2623 
2624  if (!foundCond) {
2625  // it should never be happen, all conditions are in the maps
2626 
2627  algWithConditionNotInMap = true;
2628 
2629  LogTrace("L1GtHwValidation") << "\n Error: condition "
2630  << cndName << " not found in condition map!"
2631  << "\n Add algorithm " << algName
2632  << " (bit number " << algBitNumber << ") "
2633  << "\n to list of algorithms excluded from comparison"
2634  << "\n data versus emulator." << std::endl;
2635  }
2636 
2637  }
2638  }
2639 
2640  if (algWithConditionNotInMap) {
2641  // it should never be happen, all conditions are in the maps
2642 
2643  m_excludedAlgoList.push_back(algBitNumber);
2644 
2645  LogTrace("L1GtHwValidation")
2646  << "\n Error: one or more conditions from algorithm "
2647  << algName << " (bit number " << algBitNumber << ") "
2648  << " not found in condition map!"
2649  << "\n Add it to list of algorithms excluded from comparison"
2650  << "\n data versus emulator." << std::endl;
2651  }
2652 
2653  if (algWithExcludedCondition) {
2654 
2655  m_excludedAlgoList.push_back(algBitNumber);
2656 
2657  LogTrace("L1GtHwValidation") << "\n Algorithm " << algName
2658  << " (bit number " << algBitNumber
2659  << ") contains an excluded condition."
2660  << "\n Add it to list of algorithms excluded from comparison"
2661  << "\n data versus emulator." << std::endl;
2662 
2663  }
2664 
2665  // add algorithm triggers from ExcludeAlgoTrigByName
2666  for (std::vector<std::string>::const_iterator
2667  itExcl = m_excludeAlgoTrigByName.begin();
2668  itExcl!= m_excludeAlgoTrigByName.end(); ++itExcl) {
2669 
2670  if ((*itExcl) == algName) {
2671 
2672  m_excludedAlgoList.push_back(algBitNumber);
2673 
2674  LogTrace("L1GtHwValidation") << "\n Algorithm " << algName
2675  << " (bit number " << algBitNumber
2676  << ")\n added to list of algorithms excluded from comparison"
2677  << " \n data versus emulator by ExcludeAlgoTrigByName." << std::endl;
2678  }
2679 
2680  }
2681 
2682 
2683  // add algorithm triggers from ExcludeAlgoTrigByBit
2684  for (std::vector<int>::const_iterator
2685  itExcl = m_excludeAlgoTrigByBit.begin();
2686  itExcl!= m_excludeAlgoTrigByBit.end(); ++itExcl) {
2687 
2688  if ((*itExcl) == algBitNumber) {
2689 
2690  m_excludedAlgoList.push_back(algBitNumber);
2691 
2692  LogTrace("L1GtHwValidation") << "\n Algorithm " << algName
2693  << " (bit number " << algBitNumber
2694  << ")\n added to list of algorithms excluded from comparison"
2695  << " \n data versus emulator by ExcludeAlgoTrigByBit." << std::endl;
2696  }
2697 
2698  }
2699 
2700  }
2701 
2702 }
2703 
2704 bool L1GtHwValidation::excludedAlgo(const int& iBit) const {
2705 
2706  for (std::vector<int>::const_iterator itAlgo = m_excludedAlgoList.begin(); itAlgo
2707  != m_excludedAlgoList.end(); ++itAlgo) {
2708 
2709  if (iBit == *itAlgo) {
2710  return true;
2711  }
2712  }
2713 
2714  return false;
2715 
2716 }
2717 
2718 
2719 void L1GtHwValidation::endRun(const edm::Run& run,
2720  const edm::EventSetup& evSetup) {
2721 
2722  LogDebug("L1GtHwValidation") << "\n\n endRun: " << run.id()
2723  << "\n Number of events analyzed in this run: " << m_nrEvRun
2724  << "\n Total number of events analyzed in this job: " << m_nrEvJob
2725  << "\n" << std::endl;
2726 
2727 }
2728 
2729 // method called once each job just after ending the event loop
2730 void L1GtHwValidation::endJob() {
2731 
2732  edm::LogInfo("L1GtHwValidation")
2733  << "\n\nTotal number of events analyzed in this job: " << m_nrEvJob
2734  << "\n" << std::endl;
2735 
2736  return;
2737 
2738 }
2739 
2740 //define this as a plug-in
2741 DEFINE_FWK_MODULE( L1GtHwValidation);
LogDebug
#define LogDebug(id)
Definition: MessageLogger.h:501
edm::ParameterSet::getParameter
T getParameter(std::string const &) const
L1GtPsbWord::bData
const cms_uint16_t bData(int iB) const
get/set B_DATA_CH_IB
Definition: L1GtPsbWord.cc:323
L1GtHwValidation::m_fdlDataEmulAlgoDecision
MonitorElement * m_fdlDataEmulAlgoDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:244
edm::ParameterSet::getUntrackedParameter
T getUntrackedParameter(std::string const &, T const &) const
L1GtHwValidation::m_fdlDataAlgoDecisionPrescaledMask_NoMatch
MonitorElement * m_fdlDataAlgoDecisionPrescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:227
L1GtPsbWord::bxNr
const cms_uint16_t bxNr() const
get/set bunch cross number of the actual bx
Definition: L1GtPsbWord.h:108
L1GtFdlWord::gtTechnicalTriggerWord
const TechnicalTriggerWord & gtTechnicalTriggerWord() const
get/set technical trigger bits
Definition: L1GtFdlWord.h:149
L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaled_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionUnprescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:237
L1GtHwValidation::m_l1GtTmTech
const L1GtTriggerMask * m_l1GtTmTech
Definition: L1GtHwValidation.h:188
L1GtPsbWord::boardId
const cms_uint16_t boardId() const
get/set board ID
Definition: L1GtPsbWord.h:66
edm::RunBase::id
RunID const & id() const
Definition: RunBase.h:41
L1GtHwValidation::m_fdlDataAlgoDecision_Err
MonitorElement * m_fdlDataAlgoDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:229
L1GtFdlWord::noAlgo
const cms_uint16_t noAlgo() const
get/set NoAlgo
Definition: L1GtFdlWord.h:286
L1GtHwValidation::m_l1GtDataEvmInputToken_
edm::EDGetTokenT< L1GlobalTriggerEvmReadoutRecord > m_l1GtDataEvmInputToken_
Definition: L1GtHwValidation.h:285
L1GtHwValidation::compareGTFE
virtual void compareGTFE(const edm::Event &, const edm::EventSetup &, const L1GtfeWord &, const L1GtfeWord &, const int)
compare the GTFE board
Definition: L1GtHwValidation.cc:408
L1GtHwValidation::matchCondCategory
bool matchCondCategory(const L1GtConditionCategory &, const L1GtConditionCategory &)
Definition: L1GtHwValidation.cc:2485
L1GtHwValidation::analyze
virtual void analyze(const edm::Event &, const edm::EventSetup &)
Definition: L1GtHwValidation.cc:1860
L1GtHwValidation::comparePSB
virtual void comparePSB(const edm::Event &, const edm::EventSetup &, const L1GtPsbWord &, const L1GtPsbWord &)
compare the PSB board
Definition: L1GtHwValidation.cc:1400
DQMStore::book1D
MonitorElement * book1D(const char *name, const char *title, int nchX, double lowX, double highX)
Book 1D histogram.
Definition: DQMStore.cc:872
L1GtfeWord::print
virtual void print(std::ostream &myCout) const
pretty print the content of a L1GtfeWord
Definition: L1GtfeWord.cc:321
DQMStore::rmdir
void rmdir(const std::string &fullpath)
Definition: DQMStore.cc:2730
L1GtHwValidation::m_prescaleFactorsAlgoTrig
const std::vector< std::vector< int > > * m_prescaleFactorsAlgoTrig
Definition: L1GtHwValidation.h:181
L1GtHwValidation::m_gtErrorFlag
MonitorElement * m_gtErrorFlag
PSB.
Definition: L1GtHwValidation.h:272
edm::Event::getByToken
bool getByToken(EDGetToken token, Handle< PROD > &result) const
Definition: Event.h:434
ConditionMap
std::map< std::string, L1GtCondition * > ConditionMap
map containing the conditions
Definition: L1GtTriggerMenuFwd.h:28
DEFINE_FWK_MODULE
#define DEFINE_FWK_MODULE(type)
Definition: MakerMacros.h:17
AlgorithmMap
std::map< std::string, L1GtAlgorithm > AlgorithmMap
map containing the algorithms
Definition: L1GtTriggerMenuFwd.h:31
L1GlobalTriggerReadoutSetup::NumberTechnicalTriggers
static const unsigned int NumberTechnicalTriggers
Definition: L1GlobalTriggerReadoutSetup.h:41
L1GtHwValidation::m_fdlEmulTechDecision
MonitorElement * m_fdlEmulTechDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:257
CItCond
ConditionMap::const_iterator CItCond
iterators through map containing the conditions
Definition: L1GtTriggerMenuFwd.h:34
L1GtHwValidation::m_excludedCondType
std::vector< L1GtConditionType > m_excludedCondType
excluded condition types
Definition: L1GtHwValidation.h:155
MonitorElement::setBinLabel
void setBinLabel(int bin, const std::string &label, int axis=1)
set bin label for x, y or z axis (axis=1, 2, 3 respectively)
Definition: MonitorElement.cc:901
L1GtHwValidation::m_fdlDataEmulAlgoDecisionPrescaled
MonitorElement * m_fdlDataEmulAlgoDecisionPrescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:245
L1GtTriggerMenu::gtTriggerMenuImplementation
const std::string & gtTriggerMenuImplementation() const
Definition: L1GtTriggerMenu.h:104
L1GtHwValidation::m_fdlDataEmulAlgoDecisionUnprescaledAllowed
MonitorElement * m_fdlDataEmulAlgoDecisionUnprescaledAllowed[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:247
L1GtHwValidation::excludedAlgoList
void excludedAlgoList()
exclude from comparison some bits with known disagreement - bit list
Definition: L1GtHwValidation.cc:2548
L1GtHwValidation::bookHistograms
void bookHistograms()
book all histograms for the module
Definition: L1GtHwValidation.cc:1878
L1GtHwValidation::m_fdlDataAlgoDecisionUnprescaledMask_NoMatch
MonitorElement * m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:228
l1GtConditionCategoryEnumToString
std::string l1GtConditionCategoryEnumToString(const L1GtConditionCategory &)
Definition: L1GtDefinitions.cc:248
L1GtHwValidation::m_l1GtEmulEvmInputTag
edm::InputTag m_l1GtEmulEvmInputTag
input tag for the L1 GT emulator EVM record
Definition: L1GtHwValidation.h:130
L1GtHwValidation::m_fdlEmulAlgoDecisionMask
MonitorElement * m_fdlEmulAlgoDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:234
L1GtConditionType
L1GtConditionType
Definition: L1GtDefinitions.h:99
L1GtTriggerMenu::gtConditionMap
const std::vector< ConditionMap > & gtConditionMap() const
get / set / build the condition maps
Definition: L1GtTriggerMenu.h:82
L1GtHwValidation::m_fdlDataAlgoDecisionUnprescaled
MonitorElement * m_fdlDataAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:221
L1GtHwValidation::m_l1GtMenuCacheID
unsigned long long m_l1GtMenuCacheID
Definition: L1GtHwValidation.h:172
L1GtHwValidation::m_l1GtPfTech
const L1GtPrescaleFactors * m_l1GtPfTech
Definition: L1GtHwValidation.h:178
l1GtObjectEnumToString
std::string l1GtObjectEnumToString(const L1GtObject &)
Definition: L1GtObject.cc:74
L1GtHwValidation::m_fdlEmulAlgoDecisionPrescaledMask_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:239
L1GtHwValidation::compareFDL
virtual void compareFDL(const edm::Event &, const edm::EventSetup &, const L1GtFdlWord &, const L1GtFdlWord &, const int)
compare the FDL board
Definition: L1GtHwValidation.cc:627
L1GtfeWord::altNrBxBoard
const cms_uint16_t altNrBxBoard() const
get/set alternative for number of BX per board
Definition: L1GtfeWord.h:187
L1GtHwValidation::matchCondL1GtObject
bool matchCondL1GtObject(const std::vector< L1GtObject > &, const L1GtObject &)
Definition: L1GtHwValidation.cc:2520
AlCaHLTBitMon_QueryRunRegistry.string
string string
Definition: AlCaHLTBitMon_QueryRunRegistry.py:255
L1GtHwValidation::m_excludeAlgoTrigByBit
std::vector< int > m_excludeAlgoTrigByBit
exclude algorithm triggers from comparison data - emulator by algorithm bit number ...
Definition: L1GtHwValidation.h:146
L1GtHwValidation::compareTCS
virtual void compareTCS(const edm::Event &, const edm::EventSetup &, const L1TcsWord &, const L1TcsWord &)
compare the TCS board
Definition: L1GtHwValidation.cc:1581
L1GtHwValidation::m_dbe
DQMStore * m_dbe
internal members
Definition: L1GtHwValidation.h:198
MonitorElement::Fill
void Fill(long long x)
Definition: MonitorElement.h:161
CItAlgo
AlgorithmMap::const_iterator CItAlgo
iterators through map containing the algorithms
Definition: L1GtTriggerMenuFwd.h:38
L1GtHwValidation::m_l1GtTmAlgoCacheID
unsigned long long m_l1GtTmAlgoCacheID
Definition: L1GtHwValidation.h:186
L1GtHwValidation::m_fdlEmulTechDecisionMask
MonitorElement * m_fdlEmulTechDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:258
L1GtFdlWord::bxNr
const cms_uint16_t bxNr() const
get/set BxNr - bunch cross number of the actual bx
Definition: L1GtFdlWord.h:110
L1GtHwValidation::m_fdlDataAlgoDecisionPrescaled
MonitorElement * m_fdlDataAlgoDecisionPrescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:220
L1GtFdlWord::boardId
const cms_uint16_t boardId() const
get/set board ID
Definition: L1GtFdlWord.h:69
L1GtHwValidation::m_fdlDataAlgoDecisionMask_NoMatch
MonitorElement * m_fdlDataAlgoDecisionMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:226
L1GtFdlWord::printGtDecisionWord
void printGtDecisionWord(std::ostream &myCout) const
Definition: L1GtFdlWord.cc:345
L1GtfeWord::recordLength
const cms_uint16_t recordLength() const
get/set record length for alternative 0
Definition: L1GtfeWord.h:104
L1GtFdlWord::eventNr
const cms_uint32_t eventNr() const
get/set event number since last L1 reset generated in FDL
Definition: L1GtFdlWord.h:130
L1GtHwValidation::m_gtfeDataEmul
MonitorElement * m_gtfeDataEmul[NumberOfGtRecords]
histograms
Definition: L1GtHwValidation.h:214
l1GtConditionTypeStringToEnum
L1GtConditionType l1GtConditionTypeStringToEnum(const std::string &)
Definition: L1GtDefinitions.cc:195
L1GtHwValidation::m_fdlDataAlgoDecisionUnprescaled_NoMatch
MonitorElement * m_fdlDataAlgoDecisionUnprescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:225
DecisionWordExtended
std::vector< bool > DecisionWordExtended
Definition: L1GlobalTriggerReadoutSetupFwd.h:38
L1GtHwValidation::beginRun
void beginRun(const edm::Run &run, const edm::EventSetup &c)
Definition: L1GtHwValidation.cc:196
L1GtHwValidation::m_triggerMaskTechTrig
std::vector< unsigned int > m_triggerMaskTechTrig
Definition: L1GtHwValidation.h:192
iEvent
int iEvent
Definition: GenABIO.cc:243
L1GtHwValidation::~L1GtHwValidation
virtual ~L1GtHwValidation()
Definition: L1GtHwValidation.cc:170
L1GtHwValidation::m_fdlDataEmulAlgoDecisionMask
MonitorElement * m_fdlDataEmulAlgoDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:248
l1GtObjectStringToEnum
L1GtObject l1GtObjectStringToEnum(const std::string &)
Definition: L1GtObject.cc:24
L1GtPsbWord::aData
const cms_uint16_t aData(int iA) const
get/set A_DATA_CH_IA
Definition: L1GtPsbWord.cc:228
L1GtHwValidation::m_excludedL1GtObject
std::vector< L1GtObject > m_excludedL1GtObject
excluded L1 GT objects
Definition: L1GtHwValidation.h:158
L1GtHwValidation::m_fdlDataAlgoDecisionPrescaled_NoMatch
MonitorElement * m_fdlDataAlgoDecisionPrescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:224
L1GtTriggerMask::gtTriggerMask
const std::vector< unsigned int > & gtTriggerMask() const
get the trigger mask
Definition: L1GtTriggerMask.h:49
L1GtHwValidation::m_excludeAlgoTrigByName
std::vector< std::string > m_excludeAlgoTrigByName
exclude algorithm triggers from comparison data - emulator by algorithm name
Definition: L1GtHwValidation.h:143
DecisionWord
std::vector< bool > DecisionWord
typedefs
Definition: L1GlobalTriggerReadoutSetupFwd.h:34
L1GtHwValidation::m_excludedAlgorithmsAgreement
MonitorElement * m_excludedAlgorithmsAgreement
Definition: L1GtHwValidation.h:265
L1GtHwValidation::m_l1GtTmAlgo
const L1GtTriggerMask * m_l1GtTmAlgo
trigger masks
Definition: L1GtHwValidation.h:185
L1GtHwValidation::m_l1GtEmulDaqInputTag
edm::InputTag m_l1GtEmulDaqInputTag
input tag for the L1 GT emulator DAQ record
Definition: L1GtHwValidation.h:127
L1GtHwValidation::m_fdlDataEmulTechDecision
MonitorElement * m_fdlDataEmulTechDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:261
L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:240
L1GtFdlWord::bxInEvent
const int bxInEvent() const
get/set bunch cross in the GT event record
Definition: L1GtFdlWord.h:90
L1GtfeWord::totalTriggerNr
const cms_uint32_t totalTriggerNr() const
get/set total number of L1A sent since start of run
Definition: L1GtfeWord.h:211
L1GtFdlWord::printGtDecisionWordExtended
void printGtDecisionWordExtended(std::ostream &myCout) const
Definition: L1GtFdlWord.cc:503
L1GtHwValidation::endRun
void endRun(const edm::Run &run, const edm::EventSetup &c)
Definition: L1GtHwValidation.cc:2719
L1GtConditionCategory
L1GtConditionCategory
condition categories
Definition: L1GtDefinitions.h:128
L1GtHwValidation::compareEvmRecord
virtual void compareEvmRecord(const edm::Event &, const edm::EventSetup &)
L1 GT EVM record comparison.
Definition: L1GtHwValidation.cc:1762
L1GtHwValidation::m_fdlDataTechDecision_Err
MonitorElement * m_fdlDataTechDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:255
L1GtHwValidation::matchCondType
bool matchCondType(const L1GtConditionType &, const L1GtConditionType &)
Definition: L1GtHwValidation.cc:2503
L1GtHwValidation::m_fdlDataAlgoDecision
MonitorElement * m_fdlDataAlgoDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:219
TechnicalTriggerWord
std::vector< bool > TechnicalTriggerWord
technical trigger bits (64 bits)
Definition: L1GlobalTriggerReadoutSetupFwd.h:41
L1GtHwValidation::L1GtHwValidation
L1GtHwValidation(const edm::ParameterSet &)
Definition: L1GtHwValidation.cc:52
L1GlobalTriggerReadoutSetup::NumberPhysTriggers
static const unsigned int NumberPhysTriggers
Definition: L1GlobalTriggerReadoutSetup.h:39
l1GtConditionCategoryStringToEnum
L1GtConditionCategory l1GtConditionCategoryStringToEnum(const std::string &)
Definition: L1GtDefinitions.cc:229
L1GtHwValidation::m_l1GtDataDaqInputToken_
edm::EDGetTokenT< L1GlobalTriggerReadoutRecord > m_l1GtDataDaqInputToken_
Definition: L1GtHwValidation.h:283
DQMStore::setVerbose
void setVerbose(unsigned level)
Definition: DQMStore.cc:548
L1GtHwValidation::TotalBxInEvent
static const int TotalBxInEvent
Definition: L1GtHwValidation.h:208
L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaled
MonitorElement * m_fdlEmulAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:233
L1GtPsbWord::localBxNr
const cms_uint16_t localBxNr() const
get/set local bunch cross number of the actual bx
Definition: L1GtPsbWord.h:178
edm::HandleBase::isValid
bool isValid() const
Definition: HandleBase.h:76
L1GtfeWord::activeBoards
const cms_uint16_t activeBoards() const
get/set boards contributing to EVM respectively DAQ record
Definition: L1GtfeWord.h:163
LogTrace
#define LogTrace(id)
Definition: MessageLogger.h:502
L1GtHwValidation::m_l1GtMenu
const L1GtTriggerMenu * m_l1GtMenu
trigger menu
Definition: L1GtHwValidation.h:171
L1GtHwValidation::m_fdlEmulAlgoDecision_Err
MonitorElement * m_fdlEmulAlgoDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:241
L1GtfeWord::bxNr
const cms_uint16_t bxNr() const
get/set bunch cross number as counted in the GTFE board
Definition: L1GtfeWord.h:122
L1GtHwValidation::m_l1GtEmulEvmInputToken_
edm::EDGetTokenT< L1GlobalTriggerEvmReadoutRecord > m_l1GtEmulEvmInputToken_
Definition: L1GtHwValidation.h:286
L1GtFdlWord::print
void print(std::ostream &myCout) const
pretty print the content of a L1GtFdlWord
Definition: L1GtFdlWord.cc:766
L1GtPsbWord::print
void print(std::ostream &myCout) const
pretty print
Definition: L1GtPsbWord.cc:453
dtDQMClient_cfg.prescaleFactor
tuple prescaleFactor
Definition: dtDQMClient_cfg.py:51
DQMStore::dirExists
bool dirExists(const std::string &path) const
true if directory exists
Definition: DQMStore.cc:648
l1GtConditionTypeEnumToString
std::string l1GtConditionTypeEnumToString(const L1GtConditionType &)
Definition: L1GtDefinitions.cc:215
L1GtfeWord::boardId
const cms_uint16_t boardId() const
get/set board ID
Definition: L1GtfeWord.h:65
L1GtHwValidation::m_l1GtPfAlgoCacheID
unsigned long long m_l1GtPfAlgoCacheID
Definition: L1GtHwValidation.h:176
L1GtPsbWord::eventNr
const cms_uint32_t eventNr() const
get/set event number since last L1 reset generated in PSB
Definition: L1GtPsbWord.h:129
L1GtHwValidation::m_fdlDataTechDecisionMask
MonitorElement * m_fdlDataTechDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:254
L1GtHwValidation::m_l1GtDataDaqInputTag
edm::InputTag m_l1GtDataDaqInputTag
input tag for the L1 GT hardware DAQ record
Definition: L1GtHwValidation.h:121
L1GtHwValidation::m_fdlDataAlgoDecision_NoMatch
MonitorElement * m_fdlDataAlgoDecision_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:223
L1GtHwValidation::m_fdlDataEmul
MonitorElement * m_fdlDataEmul[TotalBxInEvent][NumberOfGtRecords]
FDL (0 for DAQ, 1 for EVM record)
Definition: L1GtHwValidation.h:217
L1GtFdlWord::gtPrescaleFactorIndexAlgo
const cms_uint16_t gtPrescaleFactorIndexAlgo() const
Definition: L1GtFdlWord.h:267
L1GtHwValidation::m_fdlDataEmul_Err
MonitorElement * m_fdlDataEmul_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:250
L1GtPrescaleFactors::gtPrescaleFactors
const std::vector< std::vector< int > > & gtPrescaleFactors() const
get the prescale factors by reference
Definition: L1GtPrescaleFactors.h:47
L1GtHwValidation::m_l1GtEmulDaqInputToken_
edm::EDGetTokenT< L1GlobalTriggerReadoutRecord > m_l1GtEmulDaqInputToken_
Definition: L1GtHwValidation.h:284
L1GtHwValidation::m_excludedCondCategory
std::vector< L1GtConditionCategory > m_excludedCondCategory
excluded condition categories
Definition: L1GtHwValidation.h:152
L1GtHwValidation::m_myCoutStream
std::ostringstream m_myCoutStream
Definition: L1GtHwValidation.h:162
L1GtPsbWord::NumberBData
static const int NumberBData
Definition: L1GtPsbWord.h:35
L1GtHwValidation::beginJob
virtual void beginJob()
Definition: L1GtHwValidation.cc:177
L1GtHwValidation::m_nrDataEventError
int m_nrDataEventError
counters
Definition: L1GtHwValidation.h:165
edm::EventSetup::get
const T & get() const
Definition: EventSetup.h:55
edm::ESHandle::product
T const * product() const
Definition: ESHandle.h:62
L1GtHwValidation::m_fdlEmulAlgoDecisionMask_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:238
L1GtPsbWord::bxInEvent
const int bxInEvent() const
get/set bunch cross in the GT event record
Definition: L1GtPsbWord.h:87
L1GtFdlWord::gtDecisionWord
const DecisionWord & gtDecisionWord() const
get/set/print algorithms bits (decision word)
Definition: L1GtFdlWord.h:171
L1GtHwValidation::m_l1GtTmTechCacheID
unsigned long long m_l1GtTmTechCacheID
Definition: L1GtHwValidation.h:189
L1GtHwValidation::compareGt_Gct
virtual void compareGt_Gct(const edm::Event &, const edm::EventSetup &)
Definition: L1GtHwValidation.cc:1852
L1GtHwValidation::m_fdlEmulTechDecision_Err
MonitorElement * m_fdlEmulTechDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:259
L1GtPsbWord::NumberAData
static const int NumberAData
Definition: L1GtPsbWord.h:34
L1GtHwValidation::m_l1GctDataInputTag
edm::InputTag m_l1GctDataInputTag
input tag for the L1 GCT hardware record
Definition: L1GtHwValidation.h:133
L1GtHwValidation::m_excludeCondCategTypeObject
std::vector< edm::ParameterSet > m_excludeCondCategTypeObject
Definition: L1GtHwValidation.h:140
L1GtFdlWord::printGtTechnicalTriggerWord
void printGtTechnicalTriggerWord(std::ostream &myCout) const
Definition: L1GtFdlWord.cc:271
L1GtHwValidation::m_fdlDataEmulAlgoDecision_Err
MonitorElement * m_fdlDataEmulAlgoDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:249
L1GtfeWord::setupVersion
const cms_uint32_t setupVersion() const
get/set setup version
Definition: L1GtfeWord.h:140
L1GtTriggerMenu::gtAlgorithmMap
const AlgorithmMap & gtAlgorithmMap() const
get / set the algorithm map (by name)
Definition: L1GtTriggerMenu.h:239
L1GtHwValidation::NumberOfGtRecords
static const int NumberOfGtRecords
Definition: L1GtHwValidation.h:209
L1GtHwValidation::m_fdlDataTechDecision
MonitorElement * m_fdlDataTechDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:253
L1GtHwValidation::m_fdlEmulAlgoDecision
MonitorElement * m_fdlEmulAlgoDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:231
L1GtHwValidation::m_prescaleFactorsTechTrig
const std::vector< std::vector< int > > * m_prescaleFactorsTechTrig
Definition: L1GtHwValidation.h:182
edm::false
volatile std::atomic< bool > shutdown_flag false
Definition: UnixSignalHandlers.cc:22
L1GtHwValidation::m_fdlEmulAlgoDecision_NoMatch
MonitorElement * m_fdlEmulAlgoDecision_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:235
L1GtFdlWord::gtDecisionWordExtended
const DecisionWordExtended & gtDecisionWordExtended() const
get/set extended algorithms bits (extended decision word)
Definition: L1GtFdlWord.h:203
L1GtHwValidation::m_fdlDataEmulTechDecisionMask
MonitorElement * m_fdlDataEmulTechDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:262
L1GtHwValidation::m_fdlDataAlgoDecisionMask
MonitorElement * m_fdlDataAlgoDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:222
L1GtHwValidation::compareDaqRecord
virtual void compareDaqRecord(const edm::Event &, const edm::EventSetup &)
L1 GT DAQ record comparison.
Definition: L1GtHwValidation.cc:1587
L1GtfeWord::recordLength1
const cms_uint16_t recordLength1() const
get/set record length for alternative 1
Definition: L1GtfeWord.h:85
L1GtHwValidation::m_triggerMaskAlgoTrig
std::vector< unsigned int > m_triggerMaskAlgoTrig
Definition: L1GtHwValidation.h:191
L1GtHwValidation::m_excludedAlgoList
std::vector< int > m_excludedAlgoList
Definition: L1GtHwValidation.h:280
L1GtHwValidation::m_fdlDataEmulTechDecision_Err
MonitorElement * m_fdlDataEmulTechDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:263
L1GtHwValidation::m_fdlEmulAlgoDecisionPrescaled_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionPrescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:236
DQMStore::setCurrentFolder
void setCurrentFolder(const std::string &fullpath)
Definition: DQMStore.cc:584
L1GtFdlWord::localBxNr
const cms_uint16_t localBxNr() const
get/set local bunch cross number of the actual bx
Definition: L1GtFdlWord.h:372
L1GtHwValidation::m_l1GtPfAlgo
const L1GtPrescaleFactors * m_l1GtPfAlgo
prescale factors
Definition: L1GtHwValidation.h:175
L1GtHwValidation::m_l1GtDataEvmInputTag
edm::InputTag m_l1GtDataEvmInputTag
input tag for the L1 GT hardware EVM record
Definition: L1GtHwValidation.h:124
edm::Run
Definition: Run.h:41
L1GtFdlWord::finalOR
const cms_uint16_t finalOR() const
get/set &quot;Final OR&quot; bits
Definition: L1GtFdlWord.h:306
L1GtHwValidation::m_l1GtPfTechCacheID
unsigned long long m_l1GtPfTechCacheID
Definition: L1GtHwValidation.h:179
asciidump.at
list at
Definition: asciidump.py:428
L1GtHwValidation::m_fdlEmulAlgoDecisionPrescaled
MonitorElement * m_fdlEmulAlgoDecisionPrescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:232
L1GtHwValidation::excludedAlgo
bool excludedAlgo(const int &) const
exclusion status for algorithm with bit i
Definition: L1GtHwValidation.cc:2704
L1GtHwValidation::m_dirName
std::string m_dirName
directory name for L1Extra plots
Definition: L1GtHwValidation.h:136
L1GtHwValidation::endJob
virtual void endJob()
Definition: L1GtHwValidation.cc:2730
L1GtHwValidation::m_fdlDataEmulAlgoDecisionUnprescaled
MonitorElement * m_fdlDataEmulAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:246
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