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Enumerations

/afs/cern.ch/work/a/aaltunda/public/www/CMSSW_6_2_5/src/EventFilter/EcalRawToDigi/interface/DCCRawDataDefinitions.h File Reference

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Enumerations

enum  dccFOVs { dcc_FOV_0 = 0, dcc_FOV_1 = 1, dcc_FOV_2 = 2 }
enum  detailedTriggerTypeFields {
  H_DCCID_B = 0, H_DCCID_MASK = 0x3F, H_WAVEL_B = 6, H_WAVEL_MASK = 0x3,
  H_TR_TYPE_B = 8, H_TR_TYPE_MASK = 0x7, H_HALF_B = 11, H_HALF_MASK = 0x1
}
enum  globalFieds {
  BLOCK_UNPACKED = 0, SKIP_BLOCK_UNPACKING = 1, STOP_EVENT_UNPACKING = 2, B_MASK = 1,
  HEADERLENGTH = 9, HEADERSIZE = 72, EMPTYEVENTSIZE = 32, PHYSICTRIGGER = 1,
  CALIBRATIONTRIGGER = 2, TESTTRIGGER = 3, TECHNICALTRIGGER = 4, CH_ENABLED = 0,
  CH_DISABLED = 1, CH_TIMEOUT = 2, CH_HEADERERR = 3, CH_LINKERR = 5,
  CH_LENGTHERR = 6, CH_SUPPRESS = 7, CH_IFIFOFULL = 8, CH_L1AIFIFOFULL = 0xC,
  CH_FORCEDZS1 = 0xF, SRP_NUMBFLAGS = 68, SRP_BLOCKLENGTH = 6, SRP_EB_NUMBFLAGS = 68,
  BOEVALUE = 0x5, ERROR_EMPTYEVENT = 0x1, TOWERH_SIZE = 8, TRAILER_SIZE = 8,
  TCC_EB_NUMBTTS = 68, TCCID_SMID_SHIFT_EB = 27, NUMB_SM = 54, NUMB_FE = 68,
  NUMB_TCC = 108, NUMB_XTAL = 5, NUMB_STRIP = 5, NUMB_PSEUDOSTRIPS = 30,
  NUMB_TTS_TPG2_DUPL = 12, NUMB_TTS_TPG1 = 16, NUMB_TTS_TPG2 = 12, NUMB_SM_EE_MIN_MIN = 1,
  NUMB_SM_EE_MIN_MAX = 9, NUMB_SM_EB_MIN_MIN = 10, NUMB_SM_EB_MIN_MAX = 27, NUMB_SM_EB_PLU_MIN = 28,
  NUMB_SM_EB_PLU_MAX = 45, NUMB_SM_EE_PLU_MIN = 46, NUMB_SM_EE_PLU_MAX = 54, SECTOR_EEM_CCU_JUMP = 8,
  SECTOR_EEP_CCU_JUMP = 53, MIN_CCUID_JUMP = 18, MAX_CCUID_JUMP = 24, NUMB_TCC_EE_MIN_EXT_MIN = 19,
  NUMB_TCC_EE_MIN_EXT_MAX = 36, NUMB_TCC_EE_PLU_EXT_MIN = 73, NUMB_TCC_EE_PLU_EXT_MAX = 90
}
enum  headerFields {
  H_FEDID_B = 8, H_FEDID_MASK = 0xFFF, H_BX_B = 20, H_BX_MASK = 0xFFF,
  H_L1_B = 32, H_L1_MASK = 0xFFFFFF, H_TTYPE_B = 56, H_TTYPE_MASK = 0xF,
  H_EVLENGTH_MASK = 0xFFFFFF, H_ERRORS_B = 24, H_ERRORS_MASK = 0xFF, H_RNUMB_B = 32,
  H_RNUMB_MASK = 0xFFFFFF, H_RTYPE_MASK = 0xFFFFFFFF, H_DET_TTYPE_B = 32, H_DET_TTYPE_MASK = 0xFFFF,
  H_FOV_B = 48, H_FOV_MASK = 0xF, H_ORBITCOUNTER_B = 0, H_ORBITCOUNTER_MASK = 0xFFFFFFFF,
  H_SR_B = 32, H_ZS_B = 33, H_TZS_B = 34, H_MEM_B = 35,
  H_SRCHSTATUS_B = 36, H_CHSTATUS_MASK = 0xF, H_TCC1CHSTATUS_B = 40, H_TCC2CHSTATUS_B = 44,
  H_TCC3CHSTATUS_B = 48, H_TCC4CHSTATUS_B = 52
}
enum  srpFields {
  SRP_NREAD = 0, SRP_FULLREADOUT = 3, SRP_ID_MASK = 0xFF, SRP_BX_MASK = 0xFFF,
  SRP_BX_B = 16, SRP_L1_MASK = 0xFFF, SRP_L1_B = 32, SRP_NFLAGS_MASK = 0x7F,
  SRP_NFLAGS_B = 48, SRP_SRFLAG_MASK = 0x7, SRP_SRVAL_MASK = 0x3
}
enum  tccFields {
  TCC_ID_MASK = 0xFF, TCC_PS_B = 11, TCC_BX_MASK = 0xFFF, TCC_BX_B = 16,
  TCC_L1_MASK = 0xFFF, TCC_L1_B = 32, TCC_TT_MASK = 0x7F, TCC_TT_B = 48,
  TCC_TS_MASK = 0xF, TCC_TS_B = 55
}
enum  towerFields {
  TOWER_ID_MASK = 0x7F, TOWER_NSAMP_MASK = 0x7F, TOWER_NSAMP_B = 8, TOWER_BX_MASK = 0xFFF,
  TOWER_BX_B = 16, TOWER_L1_MASK = 0xFFF, TOWER_L1_B = 32, TOWER_ADC_MASK = 0xFFF,
  TOWER_DIGI_MASK = 0x3FFF, TOWER_STRIPID_MASK = 0x7, TOWER_XTALID_MASK = 0x7, TOWER_XTALID_B = 4,
  TOWER_LENGTH_MASK = 0x1FF, TOWER_LENGTH_B = 48
}

Enumeration Type Documentation

enum dccFOVs
Enumerator:
dcc_FOV_0 
dcc_FOV_1 
dcc_FOV_2 

Definition at line 230 of file DCCRawDataDefinitions.h.

            {
  // MC raw data based on CMS NOTE 2005/021
  // (and raw data when FOV was unassigned, earlier than mid 2008)
  dcc_FOV_0           = 0,

  // real data since ever FOV was initialized; only 2 used >= June 09 
  dcc_FOV_1           = 1,
  dcc_FOV_2           = 2
 
};
Enumerator:
H_DCCID_B 
H_DCCID_MASK 
H_WAVEL_B 
H_WAVEL_MASK 
H_TR_TYPE_B 
H_TR_TYPE_MASK 
H_HALF_B 
H_HALF_MASK 

Definition at line 142 of file DCCRawDataDefinitions.h.

                              { 

   H_DCCID_B            = 0,
   H_DCCID_MASK         = 0x3F,

   H_WAVEL_B            = 6,
   H_WAVEL_MASK         = 0x3,

   H_TR_TYPE_B          = 8,
   H_TR_TYPE_MASK       = 0x7,

   H_HALF_B             = 11,
   H_HALF_MASK          = 0x1

};
Enumerator:
BLOCK_UNPACKED 
SKIP_BLOCK_UNPACKING 
STOP_EVENT_UNPACKING 
B_MASK 
HEADERLENGTH 
HEADERSIZE 
EMPTYEVENTSIZE 
PHYSICTRIGGER 
CALIBRATIONTRIGGER 
TESTTRIGGER 
TECHNICALTRIGGER 
CH_ENABLED 
CH_DISABLED 
CH_TIMEOUT 
CH_HEADERERR 
CH_LINKERR 
CH_LENGTHERR 
CH_SUPPRESS 
CH_IFIFOFULL 
CH_L1AIFIFOFULL 
CH_FORCEDZS1 
SRP_NUMBFLAGS 
SRP_BLOCKLENGTH 
SRP_EB_NUMBFLAGS 
BOEVALUE 
ERROR_EMPTYEVENT 
TOWERH_SIZE 
TRAILER_SIZE 
TCC_EB_NUMBTTS 
TCCID_SMID_SHIFT_EB 
NUMB_SM 
NUMB_FE 
NUMB_TCC 
NUMB_XTAL 
NUMB_STRIP 
NUMB_PSEUDOSTRIPS 
NUMB_TTS_TPG2_DUPL 
NUMB_TTS_TPG1 
NUMB_TTS_TPG2 
NUMB_SM_EE_MIN_MIN 
NUMB_SM_EE_MIN_MAX 
NUMB_SM_EB_MIN_MIN 
NUMB_SM_EB_MIN_MAX 
NUMB_SM_EB_PLU_MIN 
NUMB_SM_EB_PLU_MAX 
NUMB_SM_EE_PLU_MIN 
NUMB_SM_EE_PLU_MAX 
SECTOR_EEM_CCU_JUMP 
SECTOR_EEP_CCU_JUMP 
MIN_CCUID_JUMP 
MAX_CCUID_JUMP 
NUMB_TCC_EE_MIN_EXT_MIN 
NUMB_TCC_EE_MIN_EXT_MAX 
NUMB_TCC_EE_PLU_EXT_MIN 
NUMB_TCC_EE_PLU_EXT_MAX 

Definition at line 5 of file DCCRawDataDefinitions.h.

                {

  BLOCK_UNPACKED = 0, 
  SKIP_BLOCK_UNPACKING=1, 
  STOP_EVENT_UNPACKING=2, 


  B_MASK               =  1,
  HEADERLENGTH         =  9,
  HEADERSIZE           = 72,
  EMPTYEVENTSIZE       = 32,
        
  PHYSICTRIGGER        = 1,
  CALIBRATIONTRIGGER   = 2,
  TESTTRIGGER          = 3,
  TECHNICALTRIGGER     = 4,
      
  CH_ENABLED           = 0,
  CH_DISABLED          = 1,
  CH_TIMEOUT           = 2,
  CH_HEADERERR         = 3,
  CH_LINKERR           = 5,
  CH_LENGTHERR         = 6,
  CH_SUPPRESS          = 7,
  CH_IFIFOFULL         = 8,
  CH_L1AIFIFOFULL      = 0xC,
  CH_FORCEDZS1         = 0xF,


  
  SRP_NUMBFLAGS        = 68,
  SRP_BLOCKLENGTH      = 6,
  SRP_EB_NUMBFLAGS     = 68,
  
  BOEVALUE             = 0x5, 
  ERROR_EMPTYEVENT     = 0x1,           
  TOWERH_SIZE          = 8, 
  TRAILER_SIZE         = 8,
  TCC_EB_NUMBTTS       = 68,
  TCCID_SMID_SHIFT_EB  = 27,
  
  NUMB_SM             = 54,
  NUMB_FE             = 68,
  NUMB_TCC            = 108,
  NUMB_XTAL           = 5,
  NUMB_STRIP          = 5,
  NUMB_PSEUDOSTRIPS   = 30, // input1 and input2 of TCC board has at most 30 PS_input (12 of which are duplicated)
  NUMB_TTS_TPG2_DUPL  = 12, //
  NUMB_TTS_TPG1       = 16, // input1 of TCC board has at most 16 TP's
  NUMB_TTS_TPG2       = 12, // input2 of TCC board has at most 12 TP's

  NUMB_SM_EE_MIN_MIN  = 1,
  NUMB_SM_EE_MIN_MAX  = 9,
  NUMB_SM_EB_MIN_MIN  = 10,
  NUMB_SM_EB_MIN_MAX  = 27,
  NUMB_SM_EB_PLU_MIN  = 28,
  NUMB_SM_EB_PLU_MAX  = 45,
  NUMB_SM_EE_PLU_MIN  = 46,
  NUMB_SM_EE_PLU_MAX  = 54,

  // two DCC have a missing interval in the CCU_id's
  SECTOR_EEM_CCU_JUMP = 8,
  SECTOR_EEP_CCU_JUMP = 53,
  MIN_CCUID_JUMP      = 18,
  MAX_CCUID_JUMP      = 24,
  
  NUMB_TCC_EE_MIN_EXT_MIN  = 19,     // outer TCC's in EE-
  NUMB_TCC_EE_MIN_EXT_MAX  = 36,
  NUMB_TCC_EE_PLU_EXT_MIN  = 73,    // outer TCC's in EE+
  NUMB_TCC_EE_PLU_EXT_MAX  = 90

};
Enumerator:
H_FEDID_B 
H_FEDID_MASK 
H_BX_B 
H_BX_MASK 
H_L1_B 
H_L1_MASK 
H_TTYPE_B 
H_TTYPE_MASK 
H_EVLENGTH_MASK 
H_ERRORS_B 
H_ERRORS_MASK 
H_RNUMB_B 
H_RNUMB_MASK 
H_RTYPE_MASK 
H_DET_TTYPE_B 
H_DET_TTYPE_MASK 
H_FOV_B 
H_FOV_MASK 
H_ORBITCOUNTER_B 
H_ORBITCOUNTER_MASK 
H_SR_B 
H_ZS_B 
H_TZS_B 
H_MEM_B 
H_SRCHSTATUS_B 
H_CHSTATUS_MASK 
H_TCC1CHSTATUS_B 
H_TCC2CHSTATUS_B 
H_TCC3CHSTATUS_B 
H_TCC4CHSTATUS_B 

Definition at line 80 of file DCCRawDataDefinitions.h.

                 { 
          
  H_FEDID_B            = 8,
  H_FEDID_MASK         = 0xFFF,
 
  H_BX_B               = 20,
  H_BX_MASK            = 0xFFF,
      
  H_L1_B               = 32,
  H_L1_MASK            = 0xFFFFFF,

  H_TTYPE_B            = 56,
  H_TTYPE_MASK         = 0xF,    

  H_EVLENGTH_MASK      = 0xFFFFFF,
      
  H_ERRORS_B           = 24,
  H_ERRORS_MASK        = 0xFF,

  H_RNUMB_B            = 32,
  H_RNUMB_MASK         = 0xFFFFFF,

  H_RTYPE_MASK         = 0xFFFFFFFF, // bits 0.. 31 of the 3rd DCC header word

  H_DET_TTYPE_B        = 32,
  H_DET_TTYPE_MASK     = 0xFFFF,     // for bits 32.. 47 of the 3rd DCC header word

        
  H_FOV_B              = 48,
  H_FOV_MASK           = 0xF,


  H_ORBITCOUNTER_B            = 0,
  H_ORBITCOUNTER_MASK         = 0xFFFFFFFF, // bits 0.. 31 of the 4th DCC header word

  H_SR_B               = 32,
  H_ZS_B               = 33,
  H_TZS_B              = 34,
  H_MEM_B              = 35,
        
  H_SRCHSTATUS_B       = 36,
  H_CHSTATUS_MASK      = 0xF,

  H_TCC1CHSTATUS_B     = 40, 
  H_TCC2CHSTATUS_B     = 44,
  H_TCC3CHSTATUS_B     = 48,
  H_TCC4CHSTATUS_B     = 52
     

};              
enum srpFields
Enumerator:
SRP_NREAD 
SRP_FULLREADOUT 
SRP_ID_MASK 
SRP_BX_MASK 
SRP_BX_B 
SRP_L1_MASK 
SRP_L1_B 
SRP_NFLAGS_MASK 
SRP_NFLAGS_B 
SRP_SRFLAG_MASK 
SRP_SRVAL_MASK 

Definition at line 208 of file DCCRawDataDefinitions.h.

              {
  
   SRP_NREAD           = 0,
   SRP_FULLREADOUT     = 3,
  

   SRP_ID_MASK         = 0xFF,
 
   SRP_BX_MASK         = 0xFFF,
   SRP_BX_B            = 16,

   SRP_L1_MASK         = 0xFFF, 
   SRP_L1_B            = 32,  

   SRP_NFLAGS_MASK     = 0x7F,
   SRP_NFLAGS_B        = 48,
        
   SRP_SRFLAG_MASK     = 0x7,
   SRP_SRVAL_MASK      = 0x3

};
enum tccFields
Enumerator:
TCC_ID_MASK 
TCC_PS_B 
TCC_BX_MASK 
TCC_BX_B 
TCC_L1_MASK 
TCC_L1_B 
TCC_TT_MASK 
TCC_TT_B 
TCC_TS_MASK 
TCC_TS_B 

Definition at line 187 of file DCCRawDataDefinitions.h.

              {
  
   TCC_ID_MASK         = 0xFF,
   
   TCC_PS_B            = 11,
 
   TCC_BX_MASK         = 0xFFF,
   TCC_BX_B            = 16,

   TCC_L1_MASK         = 0xFFF, 
   TCC_L1_B            = 32,  

   TCC_TT_MASK         = 0x7F,
   TCC_TT_B            = 48,

   TCC_TS_MASK         = 0xF,
   TCC_TS_B            = 55

};
Enumerator:
TOWER_ID_MASK 
TOWER_NSAMP_MASK 
TOWER_NSAMP_B 
TOWER_BX_MASK 
TOWER_BX_B 
TOWER_L1_MASK 
TOWER_L1_B 
TOWER_ADC_MASK 
TOWER_DIGI_MASK 
TOWER_STRIPID_MASK 
TOWER_XTALID_MASK 
TOWER_XTALID_B 
TOWER_LENGTH_MASK 
TOWER_LENGTH_B 

Definition at line 159 of file DCCRawDataDefinitions.h.