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L1MuCSCTFConfiguration Class Reference

#include <L1MuCSCTFConfiguration.h>

Public Member Functions

const std::string * configAsText (void) const throw ()
 
 L1MuCSCTFConfiguration (void)
 
 L1MuCSCTFConfiguration (std::string regs[12])
 
 L1MuCSCTFConfiguration (const L1MuCSCTFConfiguration &conf)
 
L1MuCSCTFConfiguration & operator= (const L1MuCSCTFConfiguration &conf)
 
edm::ParameterSet parameters (int sp) const
 
void print (std::ostream &) const
 print all the L1 CSCTF Configuration Parameters More...
 
 ~L1MuCSCTFConfiguration (void)
 

Private Attributes

std::string registers [12]
 

Detailed Description

Definition at line 7 of file L1MuCSCTFConfiguration.h.

Constructor & Destructor Documentation

L1MuCSCTFConfiguration::L1MuCSCTFConfiguration ( void  )
inline

Definition at line 23 of file L1MuCSCTFConfiguration.h.

23 {}
L1MuCSCTFConfiguration::L1MuCSCTFConfiguration ( std::string  regs[12])
inline

Definition at line 24 of file L1MuCSCTFConfiguration.h.

References registers.

24 { for(int sp=0;sp<12;sp++) registers[sp]=regs[sp]; }
L1MuCSCTFConfiguration::L1MuCSCTFConfiguration ( const L1MuCSCTFConfiguration &  conf)
inline

Definition at line 25 of file L1MuCSCTFConfiguration.h.

References registers.

25  {
26  for(int sp=0;sp<12;sp++) registers[sp] = conf.registers[sp];
27  }
L1MuCSCTFConfiguration::~L1MuCSCTFConfiguration ( void  )
inline

Definition at line 28 of file L1MuCSCTFConfiguration.h.

28 {}

Member Function Documentation

const std::string* L1MuCSCTFConfiguration::configAsText ( void  ) const
throw (
)
inline

Definition at line 12 of file L1MuCSCTFConfiguration.h.

References registers.

12  {
13  return registers;
14  }
L1MuCSCTFConfiguration& L1MuCSCTFConfiguration::operator= ( const L1MuCSCTFConfiguration &  conf)
inline

Definition at line 18 of file L1MuCSCTFConfiguration.h.

References registers.

18  {
19  for(int sp=0;sp<12;sp++) registers[sp] = conf.registers[sp];
20  return *this;
21  }
edm::ParameterSet L1MuCSCTFConfiguration::parameters ( int  sp) const

Definition at line 6 of file L1MuCSCTFConfiguration.cc.

References edm::ParameterSet::addParameter(), dbtoconf::conf, geometryCSVtoXML::line, LogDebug, registers, and relativeConstraints::value.

Referenced by Vispa.Plugins.ConfigEditor.ConfigDataAccessor.ConfigDataAccessor::inputTags(), Vispa.Plugins.ConfigEditor.ConfigDataAccessor.ConfigDataAccessor::properties(), and Vispa.Plugins.ConfigEditor.ConfigDataAccessor.ConfigDataAccessor::recursePSetProperties().

6  {
7 
8  LogDebug("L1MuCSCTFConfiguration") << "SP:"<<int(sp)<< std::endl;
9 
10  edm::ParameterSet pset;
11  if(sp>=12) return pset;
12 
13  // ------------------------------------------------------
14  // core configuration
15  // by default everything is disabled: we need to set them
16  // coincidence and singles
17  bool run_core = 0;
18  bool trigger_on_ME1a = 0;
19  bool trigger_on_ME1b = 0;
20  bool trigger_on_ME2 = 0;
21  bool trigger_on_ME3 = 0;
22  bool trigger_on_ME4 = 0;
23  bool trigger_on_MB1a = 0;
24  bool trigger_on_MB1d = 0;
25 
26  unsigned int BXAdepth = 0;
27  unsigned int useDT = 0;
28  unsigned int widePhi = 0;
29  unsigned int PreTrigger = 0;
30  // ------------------------------------------------------
31 
32  // ------------------------------------------------------
33  // these are very important parameters.
34  // Double check with Alex
35  unsigned int CoreLatency = 7;
36  bool rescaleSinglesPhi = 1;
37 
38  // ask Alex if use or remove them or what
39  bool AllowALCTonly = 0;
40  bool AllowCLCTonly = 0;
41 
42  // other useful parameters in general not set in the OMDS
43  unsigned int QualityEnableME1a = 0xFFFF;
44  unsigned int QualityEnableME1b = 0xFFFF;
45  unsigned int QualityEnableME1c = 0xFFFF;
46  unsigned int QualityEnableME1d = 0xFFFF;
47  unsigned int QualityEnableME1e = 0xFFFF;
48  unsigned int QualityEnableME1f = 0xFFFF;
49  unsigned int QualityEnableME2a = 0xFFFF;
50  unsigned int QualityEnableME2b = 0xFFFF;
51  unsigned int QualityEnableME2c = 0xFFFF;
52  unsigned int QualityEnableME3a = 0xFFFF;
53  unsigned int QualityEnableME3b = 0xFFFF;
54  unsigned int QualityEnableME3c = 0xFFFF;
55  unsigned int QualityEnableME4a = 0xFFFF;
56  unsigned int QualityEnableME4b = 0xFFFF;
57  unsigned int QualityEnableME4c = 0xFFFF;
58 
59  unsigned int kill_fiber = 0;
60  unsigned int singlesTrackOutput = 1;
61  // ------------------------------------------------------
62 
63 
64  //initialization of the DAT_ETA registers with default values
65  //the DAT_ETA registers meaning are explained at Table 2 of
66  //http://www.phys.ufl.edu/~uvarov/SP05/LU-SP_ReferenceGuide_090915_Update.pdf
67  std::vector<unsigned int> etamin(8), etamax(8), etawin(7);
68 
69  unsigned int mindetap = 8;
70  unsigned int mindetap_halo = 8;
71 
72  etamin[0] = 22;
73  etamin[1] = 22;
74  etamin[2] = 14;
75  etamin[3] = 14;
76  etamin[4] = 14;
77  etamin[5] = 14;
78  etamin[6] = 10;
79  etamin[7] = 22;
80 
81  unsigned int mindeta12_accp = 8;
82  unsigned int mindeta13_accp = 19;
83  unsigned int mindeta112_accp = 19;
84  unsigned int mindeta113_accp = 30;
85 
86  etamax[0] = 127;
87  etamax[1] = 127;
88  etamax[2] = 127;
89  etamax[3] = 127;
90  etamax[4] = 127;
91  etamax[5] = 24;
92  etamax[6] = 24;
93  etamax[7] = 127;
94 
95  unsigned int maxdeta12_accp = 14;
96  unsigned int maxdeta13_accp = 25;
97  unsigned int maxdeta112_accp = 25;
98  unsigned int maxdeta113_accp = 36;
99 
100  etawin[0] = 4;
101  etawin[1] = 4;
102  etawin[2] = 4;
103  etawin[3] = 4;
104  etawin[4] = 4;
105  etawin[5] = 4;
106  etawin[6] = 4;
107 
108  unsigned int maxdphi12_accp = 64;
109  unsigned int maxdphi13_accp = 64;
110  unsigned int maxdphi112_accp = 64;
111  unsigned int maxdphi113_accp = 64;
112 
113  unsigned int mindphip = 128;
114  unsigned int mindphip_halo = 128;
115 
116  unsigned int straightp = 60;
117  unsigned int curvedp = 200;
118 
119  unsigned int mbaPhiOff = 0;
120  // this differ from the default value in the documentation because during
121  // craft 09 it mbbPhiOff, as well as mbaPhiOff were not existing, thus set to 0 (they are offsets)
122  // and for backward compatibility it needs to be set to 0. Anyway mbbPhiOff since its introduction in the
123  // core will have to be ALWAYS part of the configuration, so it won't be never initialized to the
124  // default value 2048.
125  unsigned int mbbPhiOff = 0;
126 
127  int eta_cnt=0;
128 
129  // default firmware versions (the ones used from run 132440)
130  unsigned int firmwareSP=20100210;
131  unsigned int firmwareFA=20090521;
132  unsigned int firmwareDD=20090521;
133  unsigned int firmwareVM=20090521;
134 
135  // default printout
136  LogDebug("L1MuCSCTFConfiguration") << "\nCORE CONFIGURATION DEFAULT VALUES"
137  << "\nrun_core=" << run_core
138  << "\ntrigger_on_ME1a=" << trigger_on_ME1a
139  << "\ntrigger_on_ME1b=" << trigger_on_ME1b
140  << "\ntrigger_on_ME2=" << trigger_on_ME2
141  << "\ntrigger_on_ME3=" << trigger_on_ME3
142  << "\ntrigger_on_ME4=" << trigger_on_ME4
143  << "\ntrigger_on_MB1a=" << trigger_on_MB1a
144  << "\ntrigger_on_MB1d=" << trigger_on_MB1d
145 
146  << "\nBXAdepth=" << BXAdepth
147  << "\nuseDT=" << useDT
148  << "\nwidePhi=" << widePhi
149  << "\nPreTrigger=" << PreTrigger
150 
151  << "\nCoreLatency="<< CoreLatency
152  << "\nrescaleSinglesPhi=" << rescaleSinglesPhi
153 
154  << "\n\nVARIOUS CONFIGURATION PARAMETERS DEFAULT VALUES"
155  << "\nAllowALCTonly=" << AllowALCTonly
156  << "\nAllowCLCTonly=" << AllowCLCTonly
157 
158  << "\nQualityEnableME1a=" << QualityEnableME1a
159  << "\nQualityEnableME1b=" << QualityEnableME1b
160  << "\nQualityEnableME1c=" << QualityEnableME1c
161  << "\nQualityEnableME1d=" << QualityEnableME1d
162  << "\nQualityEnableME1e=" << QualityEnableME1e
163  << "\nQualityEnableME1f=" << QualityEnableME1f
164  << "\nQualityEnableME2a=" << QualityEnableME2a
165  << "\nQualityEnableME2b=" << QualityEnableME2b
166  << "\nQualityEnableME2c=" << QualityEnableME2c
167  << "\nQualityEnableME3a=" << QualityEnableME3a
168  << "\nQualityEnableME3b=" << QualityEnableME3b
169  << "\nQualityEnableME3c=" << QualityEnableME3c
170  << "\nQualityEnableME4a=" << QualityEnableME4a
171  << "\nQualityEnableME4b=" << QualityEnableME4b
172  << "\nQualityEnableME4c=" << QualityEnableME4c
173 
174  << "\nkill_fiber=" << kill_fiber
175  << "\nsinglesTrackOutput=" << singlesTrackOutput
176 
177  << "\n\nDEFAULT VALUES FOR DAT_ETA"
178  << "\nmindetap =" << mindetap
179  << "\nmindetap_halo=" << mindetap_halo
180 
181  << "\netamin[0]=" << etamin[0]
182  << "\netamin[1]=" << etamin[1]
183  << "\netamin[2]=" << etamin[2]
184  << "\netamin[3]=" << etamin[3]
185  << "\netamin[4]=" << etamin[4]
186  << "\netamin[5]=" << etamin[5]
187  << "\netamin[6]=" << etamin[6]
188  << "\netamin[7]=" << etamin[7]
189 
190  << "\nmindeta12_accp =" << mindeta12_accp
191  << "\nmindeta13_accp =" << mindeta13_accp
192  << "\nmindeta112_accp=" << mindeta112_accp
193  << "\nmindeta113_accp=" << mindeta113_accp
194 
195  << "\netamax[0]=" << etamax[0]
196  << "\netamax[1]=" << etamax[1]
197  << "\netamax[2]=" << etamax[2]
198  << "\netamax[3]=" << etamax[3]
199  << "\netamax[4]=" << etamax[4]
200  << "\netamax[5]=" << etamax[5]
201  << "\netamax[6]=" << etamax[6]
202  << "\netamax[7]=" << etamax[7]
203 
204  << "\nmaxdeta12_accp =" << maxdeta12_accp
205  << "\nmaxdeta13_accp =" << maxdeta13_accp
206  << "\nmaxdeta112_accp=" << maxdeta112_accp
207  << "\nmaxdeta113_accp=" << maxdeta113_accp
208 
209  << "\netawin[0]=" << etawin[0]
210  << "\netawin[1]=" << etawin[1]
211  << "\netawin[2]=" << etawin[2]
212  << "\netawin[3]=" << etawin[3]
213  << "\netawin[4]=" << etawin[4]
214  << "\netawin[5]=" << etawin[5]
215  << "\netawin[6]=" << etawin[6]
216 
217  << "\nmaxdphi12_accp =" << maxdphi12_accp
218  << "\nmaxdphi13_accp =" << maxdphi13_accp
219  << "\nmaxdphi112_accp=" << maxdphi112_accp
220  << "\nmaxdphi113_accp=" << maxdphi113_accp
221 
222  << "\nmindphip =" << mindphip
223  << "\nmindphip_halo=" << mindphip_halo
224 
225  << "\nstraightp=" << straightp
226  << "\ncurvedp =" << curvedp
227  << "\nmbaPhiOff=" << mbaPhiOff
228  << "\nmbbPhiOff=" << mbbPhiOff
229 
230  << "\n\nFIRMWARE VERSIONS"
231  << "\nSP: " << firmwareSP
232  << "\nFA: " << firmwareFA
233  << "\nDD: " << firmwareDD
234  << "\nVM: " << firmwareVM;
235 
236  // start filling the registers with the values in the DBS
237  std::stringstream conf(registers[sp]);
238  while( !conf.eof() ){
239  char buff[1024];
240  conf.getline(buff,1024);
241  std::stringstream line(buff);
242  //std::cout<<"buff:"<<buff<<std::endl;
243  std::string register_; line>>register_;
244  std::string chip_; line>>chip_;
245  std::string muon_; line>>muon_;
246  std::string writeValue_; line>>writeValue_;
247  std::string comments_; std::getline(line,comments_);
248 
249  if( register_=="CSR_REQ" && chip_=="SP" ){
250  unsigned int value = strtol(writeValue_.c_str(),'\0',16);
251  run_core = (value&0x8000);
252  trigger_on_ME1a = (value&0x0001);
253  trigger_on_ME1b = (value&0x0002);
254  trigger_on_ME2 = (value&0x0004);
255  trigger_on_ME3 = (value&0x0008);
256  trigger_on_ME4 = (value&0x0010);
257  trigger_on_MB1a = (value&0x0100);
258  trigger_on_MB1d = (value&0x0200);
259  }
260 
261 
262  if( register_=="CSR_SCC" && chip_=="SP" ){
263  unsigned int value = strtol(writeValue_.c_str(),'\0',16);
264 
265  BXAdepth = (value&0x3);
266  useDT = ( (value&0x80)>>7 );
267  widePhi = ( (value&0x40)>>6 );
268  PreTrigger = ( (value&0x300)>>8);
269  }
270 
271 
272  if( register_=="CSR_LQE" && chip_=="F1" && muon_=="M1" )
273  QualityEnableME1a = strtol(writeValue_.c_str(),'\0',16);
274  if( register_=="CSR_LQE" && chip_=="F1" && muon_=="M2" )
275  QualityEnableME1b = strtol(writeValue_.c_str(),'\0',16);
276  if( register_=="CSR_LQE" && chip_=="F1" && muon_=="M3" )
277  QualityEnableME1c = strtol(writeValue_.c_str(),'\0',16);
278  if( register_=="CSR_LQE" && chip_=="F2" && muon_=="M1" )
279  QualityEnableME1d = strtol(writeValue_.c_str(),'\0',16);
280  if( register_=="CSR_LQE" && chip_=="F2" && muon_=="M2" )
281  QualityEnableME1e = strtol(writeValue_.c_str(),'\0',16);
282  if( register_=="CSR_LQE" && chip_=="F2" && muon_=="M3" )
283  QualityEnableME1f = strtol(writeValue_.c_str(),'\0',16);
284  if( register_=="CSR_LQE" && chip_=="F3" && muon_=="M1" )
285  QualityEnableME2a = strtol(writeValue_.c_str(),'\0',16);
286  if( register_=="CSR_LQE" && chip_=="F3" && muon_=="M2" )
287  QualityEnableME2b = strtol(writeValue_.c_str(),'\0',16);
288  if( register_=="CSR_LQE" && chip_=="F3" && muon_=="M3" )
289  QualityEnableME2c = strtol(writeValue_.c_str(),'\0',16);
290  if( register_=="CSR_LQE" && chip_=="F4" && muon_=="M1" )
291  QualityEnableME3a = strtol(writeValue_.c_str(),'\0',16);
292  if( register_=="CSR_LQE" && chip_=="F4" && muon_=="M2" )
293  QualityEnableME3b = strtol(writeValue_.c_str(),'\0',16);
294  if( register_=="CSR_LQE" && chip_=="F4" && muon_=="M3" )
295  QualityEnableME3c = strtol(writeValue_.c_str(),'\0',16);
296  if( register_=="CSR_LQE" && chip_=="F5" && muon_=="M1" )
297  QualityEnableME4a = strtol(writeValue_.c_str(),'\0',16);
298  if( register_=="CSR_LQE" && chip_=="F5" && muon_=="M2" )
299  QualityEnableME4b = strtol(writeValue_.c_str(),'\0',16);
300  if( register_=="CSR_LQE" && chip_=="F5" && muon_=="M3" )
301  QualityEnableME4c = strtol(writeValue_.c_str(),'\0',16);
302 
303  if( register_=="CSR_KFL" )
304  kill_fiber = strtol(writeValue_.c_str(),'\0',16);
305 
306  if( register_=="CSR_SFC" && chip_=="SP" ){
307  unsigned int value = strtol(writeValue_.c_str(),'\0',16);
308  singlesTrackOutput = ((value&0x3000)>>12);
309  }
310 
311  if( register_=="CNT_ETA" && chip_=="SP" ){
312  unsigned int value = strtol(writeValue_.c_str(),'\0',16);
313  eta_cnt = value;
314  }
315 
316 
317  // LATEST VERSION FROM CORE 2010-01-22 at http://www.phys.ufl.edu/~madorsky/sp/2010-01-22
318  if( register_=="DAT_ETA" && chip_=="SP" ){
319 
320  unsigned int value = strtol(writeValue_.c_str(),'\0',16);
321 
322  //std::cout<<"DAT_ETA SP value:"<<value<<std::endl;
323 
324  if (eta_cnt== 0) mindetap = value;
325  if (eta_cnt== 1) mindetap_halo = value;
326 
327  if (eta_cnt>= 2 && eta_cnt<10 ) etamin[eta_cnt-2] = value;
328 
329  if (eta_cnt==10) mindeta12_accp = value;
330  if (eta_cnt==11) mindeta13_accp = value;
331  if (eta_cnt==12) mindeta112_accp = value;
332  if (eta_cnt==13) mindeta113_accp = value;
333 
334  if (eta_cnt>=14 && eta_cnt<22 ) etamax[eta_cnt-14] = value;
335 
336  if (eta_cnt==22) maxdeta12_accp = value;
337  if (eta_cnt==23) maxdeta13_accp = value;
338  if (eta_cnt==24) maxdeta112_accp = value;
339  if (eta_cnt==25) maxdeta113_accp = value;
340 
341  if( eta_cnt>=26 && eta_cnt<33) etawin[eta_cnt-26] = value;
342 
343  if (eta_cnt==33) maxdphi12_accp = value;
344  if (eta_cnt==34) maxdphi13_accp = value;
345  if (eta_cnt==35) maxdphi112_accp = value;
346  if (eta_cnt==36) maxdphi113_accp = value;
347 
348  if (eta_cnt==37) mindphip = value;
349  if (eta_cnt==38) mindphip_halo = value;
350 
351  if (eta_cnt==39) straightp = value;
352  if (eta_cnt==40) curvedp = value;
353  if (eta_cnt==41) mbaPhiOff = value;
354  if (eta_cnt==42) mbbPhiOff = value;
355 
356  eta_cnt++;
357  }
358 
359  // filling the firmware variables: SP MEZZANINE
360  if( register_=="FIRMWARE" && muon_=="SP" ){
361  unsigned int value = atoi(writeValue_.c_str());
362  firmwareSP=value;
363  }
364 
365  // filling the firmware variables: Front FPGAs
366  if( register_=="FIRMWARE" && muon_=="FA" ){
367  unsigned int value = atoi(writeValue_.c_str());
368  firmwareFA=value;
369  }
370 
371  // filling the firmware variables: DDU
372  if( register_=="FIRMWARE" && muon_=="DD" ){
373  unsigned int value = atoi(writeValue_.c_str());
374  firmwareDD=value;
375  }
376 
377  // filling the firmware variables: VM
378  if( register_=="FIRMWARE" && muon_=="VM" ){
379  unsigned int value = atoi(writeValue_.c_str());
380  firmwareVM=value;
381  }
382  }
383 
384 
385 
386  pset.addParameter<bool>("run_core" , run_core );
387  pset.addParameter<bool>("trigger_on_ME1a", trigger_on_ME1a);
388  pset.addParameter<bool>("trigger_on_ME1b", trigger_on_ME1b);
389  pset.addParameter<bool>("trigger_on_ME2" , trigger_on_ME2 );
390  pset.addParameter<bool>("trigger_on_ME3" , trigger_on_ME3 );
391  pset.addParameter<bool>("trigger_on_ME4" , trigger_on_ME4 );
392  pset.addParameter<bool>("trigger_on_MB1a", trigger_on_MB1a);
393  pset.addParameter<bool>("trigger_on_MB1d", trigger_on_MB1d);
394 
395  pset.addParameter<unsigned int>("BXAdepth" , BXAdepth );
396  pset.addParameter<unsigned int>("useDT" , useDT );
397  pset.addParameter<unsigned int>("widePhi" , widePhi );
398  pset.addParameter<unsigned int>("PreTrigger", PreTrigger);
399 
400  // this were two old settings, not used anymore. Set them to zero
401  // ask Alex if he can remove them altogether
402  pset.addParameter<bool>("AllowALCTonly", AllowALCTonly);
403  pset.addParameter<bool>("AllowCLCTonly", AllowCLCTonly);
404 
405  pset.addParameter<int>("CoreLatency", CoreLatency);
406  pset.addParameter<bool>("rescaleSinglesPhi", rescaleSinglesPhi);
407 
408  pset.addParameter<unsigned int>("QualityEnableME1a",QualityEnableME1a);
409  pset.addParameter<unsigned int>("QualityEnableME1b",QualityEnableME1b);
410  pset.addParameter<unsigned int>("QualityEnableME1c",QualityEnableME1c);
411  pset.addParameter<unsigned int>("QualityEnableME1d",QualityEnableME1d);
412  pset.addParameter<unsigned int>("QualityEnableME1e",QualityEnableME1e);
413  pset.addParameter<unsigned int>("QualityEnableME1f",QualityEnableME1f);
414  pset.addParameter<unsigned int>("QualityEnableME2a",QualityEnableME2a);
415  pset.addParameter<unsigned int>("QualityEnableME2b",QualityEnableME2b);
416  pset.addParameter<unsigned int>("QualityEnableME2c",QualityEnableME2c);
417  pset.addParameter<unsigned int>("QualityEnableME3a",QualityEnableME3a);
418  pset.addParameter<unsigned int>("QualityEnableME3b",QualityEnableME3b);
419  pset.addParameter<unsigned int>("QualityEnableME3c",QualityEnableME3c);
420  pset.addParameter<unsigned int>("QualityEnableME4a",QualityEnableME4a);
421  pset.addParameter<unsigned int>("QualityEnableME4b",QualityEnableME4b);
422  pset.addParameter<unsigned int>("QualityEnableME4c",QualityEnableME4c);
423 
424  pset.addParameter<unsigned int>("kill_fiber",kill_fiber);
425  pset.addParameter<unsigned int>("singlesTrackOutput",singlesTrackOutput);
426 
427  // add the DAT_ETA registers to the pset
428  pset.addParameter<unsigned int>("mindetap" , mindetap );
429  pset.addParameter<unsigned int>("mindetap_halo", mindetap_halo);
430 
431  pset.addParameter< std::vector<unsigned int> >("EtaMin",etamin);
432 
433  pset.addParameter<unsigned int>("mindeta12_accp", mindeta12_accp );
434  pset.addParameter<unsigned int>("mindeta13_accp" , mindeta13_accp );
435  pset.addParameter<unsigned int>("mindeta112_accp", mindeta112_accp);
436  pset.addParameter<unsigned int>("mindeta113_accp", mindeta113_accp);
437 
438  pset.addParameter< std::vector<unsigned int> >("EtaMax",etamax);
439 
440  pset.addParameter<unsigned int>("maxdeta12_accp", maxdeta12_accp );
441  pset.addParameter<unsigned int>("maxdeta13_accp" , maxdeta13_accp );
442  pset.addParameter<unsigned int>("maxdeta112_accp", maxdeta112_accp);
443  pset.addParameter<unsigned int>("maxdeta113_accp", maxdeta113_accp);
444 
445  pset.addParameter< std::vector<unsigned int> >("EtaWindows",etawin);
446 
447  pset.addParameter<unsigned int>("maxdphi12_accp", maxdphi12_accp );
448  pset.addParameter<unsigned int>("maxdphi13_accp" , maxdphi13_accp );
449  pset.addParameter<unsigned int>("maxdphi112_accp", maxdphi112_accp);
450  pset.addParameter<unsigned int>("maxdphi113_accp", maxdphi113_accp);
451 
452  pset.addParameter<unsigned int>("mindphip", mindphip );
453  pset.addParameter<unsigned int>("mindphip_halo", mindphip_halo);
454 
455  pset.addParameter<unsigned int>("straightp", straightp);
456  pset.addParameter<unsigned int>("curvedp" , curvedp );
457  pset.addParameter<unsigned int>("mbaPhiOff", mbaPhiOff);
458  pset.addParameter<unsigned int>("mbbPhiOff", mbbPhiOff);
459 
460  pset.addParameter<unsigned int>("firmwareSP", firmwareSP);
461  pset.addParameter<unsigned int>("firmwareFA", firmwareFA);
462  pset.addParameter<unsigned int>("firmwareDD", firmwareDD);
463  pset.addParameter<unsigned int>("firmwareVM", firmwareVM);
464 
465 
466  // printout
467  LogDebug("L1MuCSCTFConfiguration") << "\nCORE CONFIGURATION AFTER READING THE DBS VALUES"
468  << "\nrun_core=" << run_core
469  << "\ntrigger_on_ME1a=" << trigger_on_ME1a
470  << "\ntrigger_on_ME1b=" << trigger_on_ME1b
471  << "\ntrigger_on_ME2=" << trigger_on_ME2
472  << "\ntrigger_on_ME3=" << trigger_on_ME3
473  << "\ntrigger_on_ME4=" << trigger_on_ME4
474  << "\ntrigger_on_MB1a=" << trigger_on_MB1a
475  << "\ntrigger_on_MB1d=" << trigger_on_MB1d
476 
477  << "\nBXAdepth=" << BXAdepth
478  << "\nuseDT=" << useDT
479  << "\nwidePhi=" << widePhi
480  << "\nPreTrigger=" << PreTrigger
481 
482  << "\nCoreLatency=" << CoreLatency
483  << "\nrescaleSinglesPhi=" << rescaleSinglesPhi
484 
485  << "\n\nVARIOUS CONFIGURATION PARAMETERS AFTER READING THE DBS VALUES"
486  << "\nAllowALCTonly=" << AllowALCTonly
487  << "\nAllowCLCTonly=" << AllowCLCTonly
488 
489  << "\nQualityEnableME1a=" << QualityEnableME1a
490  << "\nQualityEnableME1b=" << QualityEnableME1b
491  << "\nQualityEnableME1c=" << QualityEnableME1c
492  << "\nQualityEnableME1d=" << QualityEnableME1d
493  << "\nQualityEnableME1e=" << QualityEnableME1e
494  << "\nQualityEnableME1f=" << QualityEnableME1f
495  << "\nQualityEnableME2a=" << QualityEnableME2a
496  << "\nQualityEnableME2b=" << QualityEnableME2b
497  << "\nQualityEnableME2c=" << QualityEnableME2c
498  << "\nQualityEnableME3a=" << QualityEnableME3a
499  << "\nQualityEnableME3b=" << QualityEnableME3b
500  << "\nQualityEnableME3c=" << QualityEnableME3c
501  << "\nQualityEnableME4a=" << QualityEnableME4a
502  << "\nQualityEnableME4b=" << QualityEnableME4b
503  << "\nQualityEnableME4c=" << QualityEnableME4c
504 
505  << "\nkill_fiber=" << kill_fiber
506  << "\nsinglesTrackOutput=" << singlesTrackOutput
507 
508  << "\n\nDAT_ETA AFTER READING THE DBS VALUES"
509  << "\nmindetap =" << mindetap
510  << "\nmindetap_halo=" << mindetap_halo
511 
512  << "\netamin[0]=" << etamin[0]
513  << "\netamin[1]=" << etamin[1]
514  << "\netamin[2]=" << etamin[2]
515  << "\netamin[3]=" << etamin[3]
516  << "\netamin[4]=" << etamin[4]
517  << "\netamin[5]=" << etamin[5]
518  << "\netamin[6]=" << etamin[6]
519  << "\netamin[7]=" << etamin[7]
520 
521  << "\nmindeta12_accp =" << mindeta12_accp
522  << "\nmindeta13_accp =" << mindeta13_accp
523  << "\nmindeta112_accp=" << mindeta112_accp
524  << "\nmindeta113_accp=" << mindeta113_accp
525 
526  << "\netamax[0]=" << etamax[0]
527  << "\netamax[1]=" << etamax[1]
528  << "\netamax[2]=" << etamax[2]
529  << "\netamax[3]=" << etamax[3]
530  << "\netamax[4]=" << etamax[4]
531  << "\netamax[5]=" << etamax[5]
532  << "\netamax[6]=" << etamax[6]
533  << "\netamax[7]=" << etamax[7]
534 
535  << "\nmaxdeta12_accp =" << maxdeta12_accp
536  << "\nmaxdeta13_accp =" << maxdeta13_accp
537  << "\nmaxdeta112_accp=" << maxdeta112_accp
538  << "\nmaxdeta113_accp=" << maxdeta113_accp
539 
540  << "\netawin[0]=" << etawin[0]
541  << "\netawin[1]=" << etawin[1]
542  << "\netawin[2]=" << etawin[2]
543  << "\netawin[3]=" << etawin[3]
544  << "\netawin[4]=" << etawin[4]
545  << "\netawin[5]=" << etawin[5]
546  << "\netawin[6]=" << etawin[6]
547 
548  << "\nmaxdphi12_accp =" << maxdphi12_accp
549  << "\nmaxdphi13_accp =" << maxdphi13_accp
550  << "\nmaxdphi112_accp=" << maxdphi112_accp
551  << "\nmaxdphi113_accp=" << maxdphi113_accp
552 
553  << "\nmindphip =" << mindphip
554  << "\nmindphip_halo=" << mindphip_halo
555 
556  << "\nstraightp=" << straightp
557  << "\ncurvedp =" << curvedp
558  << "\nmbaPhiOff=" << mbaPhiOff
559  << "\nmbbPhiOff=" << mbbPhiOff
560 
561  << "\n\nFIRMWARE VERSIONS AFTER READING THE DBS VALUES"
562  << "\nSP: " << firmwareSP
563  << "\nFA: " << firmwareFA
564  << "\nDD: " << firmwareDD
565  << "\nVM: " << firmwareVM;
566 
567  // ---------------------------------------------------------
568 
569  return pset;
570 
571 }
LogDebug
#define LogDebug(id)
Definition: MessageLogger.h:501
edm::ParameterSet::addParameter
void addParameter(std::string const &name, T const &value)
Definition: ParameterSet.h:145
dbtoconf.conf
tuple conf
Definition: dbtoconf.py:185
void L1MuCSCTFConfiguration::print ( std::ostream &  myStr) const

print all the L1 CSCTF Configuration Parameters

Definition at line 575 of file L1MuCSCTFConfiguration.cc.

References registers.

575  {
576  myStr << "\nL1 Mu CSCTF Parameters \n" << std::endl;
577 
578  for (int iSP=0;iSP<12;iSP++) {
579  myStr << "=============================================" << std::endl;
580  myStr << "Printing out Global Tag Content for SP " << iSP+1 << std::endl;
581  myStr << registers[iSP];
582  myStr << "=============================================" << std::endl;
583  }
584 }

Member Data Documentation

std::string L1MuCSCTFConfiguration::registers[12]
private

Definition at line 9 of file L1MuCSCTFConfiguration.h.

Referenced by configAsText(), L1MuCSCTFConfiguration(), operator=(), parameters(), and print().

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