CMS 3D CMS Logo

 All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Properties Friends Macros Pages
FedCablingHistograms.cc
Go to the documentation of this file.
9 #include <iostream>
10 #include <sstream>
11 #include <iomanip>
12 #include "TProfile.h"
13 
14 using namespace std;
15 using namespace sistrip;
16 
17 // -----------------------------------------------------------------------------
20  DQMStore* bei )
21  : CommissioningHistograms( pset.getParameter<edm::ParameterSet>("FedCablingParameters"),
22  bei,
23  sistrip::FED_CABLING ),
24  factory_( new Factory )
25 {
27  << "[FedCablingHistograms::" << __func__ << "]"
28  << " Constructing object...";
29 }
30 
31 // -----------------------------------------------------------------------------
35  << "[FedCablingHistograms::" << __func__ << "]"
36  << " Destructing object...";
37 }
38 
39 // -----------------------------------------------------------------------------
43  << "[FedCablingHistograms::" << __func__ << "]";
44 
45  uint16_t valid = 0;
46  HistosMap::const_iterator iter;
47  Analyses::iterator ianal;
48 
49  // Clear map holding analysis objects
50  for ( ianal = data_.begin(); ianal != data_.end(); ianal++ ) {
51  if ( ianal->second ) { delete ianal->second; }
52  }
53  data_.clear();
54 
55  // Iterate through map containing histograms
56  for ( iter = histos().begin();
57  iter != histos().end(); iter++ ) {
58 
59  // Check vector of histos is not empty
60  if ( iter->second.empty() ) {
62  << "[FedCablingHistograms::" << __func__ << "]"
63  << " Zero histograms found!";
64  continue;
65  }
66 
67  // Retrieve pointers to histos
68  std::vector<TH1*> profs;
69  Histos::const_iterator ihis = iter->second.begin();
70  for ( ; ihis != iter->second.end(); ihis++ ) {
71  TProfile* prof = ExtractTObject<TProfile>().extract( (*ihis)->me_ );
72  if ( prof ) { profs.push_back(prof); }
73  }
74 
75  // Perform histo analysis
76  FedCablingAnalysis* anal = new FedCablingAnalysis( iter->first );
77  FedCablingAlgorithm algo( this->pset(), anal );
78  algo.analysis( profs );
79  data_[iter->first] = anal;
80  if ( anal->isValid() ) { valid++; }
81 
82  }
83 
84  if ( !histos().empty() ) {
86  << "[FedCablingHistograms::" << __func__ << "]"
87  << " Analyzed histograms for " << histos().size()
88  << " FED channels, of which " << valid
89  << " (" << 100 * valid / histos().size()
90  << "%) are valid.";
91  } else {
93  << "[FedCablingHistograms::" << __func__ << "]"
94  << " No histograms to analyze!";
95  }
96 
97 }
98 
99 // -----------------------------------------------------------------------------
102  Analyses::iterator ianal = data_.begin();
103  Analyses::iterator janal = data_.end();
104  for ( ; ianal != janal; ++ianal ) {
105  if ( ianal->second ) {
106  std::stringstream ss;
107  ianal->second->print( ss );
108  if ( ianal->second->isValid() ) { LogTrace(mlDqmClient_) << ss.str();
109  } else { edm::LogWarning(mlDqmClient_) << ss.str(); }
110  }
111  }
112 }
113 
114 // -----------------------------------------------------------------------------
117  const sistrip::Presentation& type,
118  const std::string& dir,
119  const sistrip::Granularity& gran ) {
121  << "[FedCablingHistograms::" << __func__ << "]";
122 
123  // Check view
125  if ( view == sistrip::UNKNOWN_VIEW ) { return; }
126 
127  // Analyze histograms if not done already
128  if ( data_.empty() ) { histoAnalysis( false ); }
129 
130  // Extract data to be histogrammed
131  uint32_t xbins = factory_->init( histo, type, view, dir, gran, data_ );
132 
133  // Create summary histogram (if it doesn't already exist)
134  TH1* summary = histogram( histo, type, view, dir, xbins );
135 
136  // Fill histogram with data
137  factory_->fill( *summary );
138 
139 }
140 
141 
142 
143 
void analysis(const std::vector< TH1 * > &)
type
Definition: HCALResponse.h:22
TH1 * histogram(const sistrip::Monitorable &, const sistrip::Presentation &, const sistrip::View &, const std::string &directory, const uint32_t &xbins, const float &xlow=1.*sistrip::invalid_, const float &xhigh=1.*sistrip::invalid_)
const double xbins[]
const edm::ParameterSet & pset() const
Histogram-based analysis for connection loop.
std::auto_ptr< Factory > factory_
static const char mlDqmClient_[]
void createSummaryHisto(const sistrip::Monitorable &, const sistrip::Presentation &, const std::string &top_level_dir, const sistrip::Granularity &)
static std::string view(const sistrip::View &)
#define LogTrace(id)
int extract(std::vector< int > *output, const std::string &dati)
#define begin
Definition: vmac.h:31
FedCablingHistograms(const edm::ParameterSet &pset, DQMStore *)
void histoAnalysis(bool debug)
dbl *** dir
Definition: mlp_gen.cc:35
LimitAlgo * algo
Definition: Combine.cc:60
#define debug
Definition: MEtoEDMFormat.h:34
Histogram-based analysis for connection loop.
const HistosMap & histos() const