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SiStripFecCabling Class Reference

#include <SiStripFecCabling.h>

Public Member Functions

void addDevices (const FedChannelConnection &conn)
 
void buildFecCabling (const SiStripFedCabling &)
 
void connections (std::vector< FedChannelConnection > &) const
 
NumberOfDevices countDevices () const
 
const std::vector
< SiStripFecCrate > & 
crates () const
 
void dcuId (const FedChannelConnection &conn)
 
void detId (const FedChannelConnection &conn)
 
const std::vector< SiStripFec > & fecs () const
 
const SiStripModulemodule (const FedChannelConnection &conn) const
 
const SiStripModulemodule (const uint32_t &dcu_id) const
 
void nApvPairs (const FedChannelConnection &conn)
 
void print (std::stringstream &) const
 
 SiStripFecCabling (const SiStripFedCabling &)
 
 SiStripFecCabling ()
 
void terse (std::stringstream &) const
 
 ~SiStripFecCabling ()
 

Private Attributes

std::vector< SiStripFecCratecrates_
 

Detailed Description

Definition at line 25 of file SiStripFecCabling.h.

Constructor & Destructor Documentation

SiStripFecCabling::SiStripFecCabling ( const SiStripFedCabling fed_cabling)

Definition at line 14 of file SiStripFecCabling.cc.

References buildFecCabling(), crates_, LogTrace, and sistrip::mlCabling_.

15  : crates_()
16 {
18  << "[SiStripFecCabling::" << __func__ << "]"
19  << " Constructing object...";
20  crates_.reserve(4);
21  buildFecCabling( fed_cabling );
22 }
std::vector< SiStripFecCrate > crates_
static const char mlCabling_[]
void buildFecCabling(const SiStripFedCabling &)
#define LogTrace(id)
SiStripFecCabling::SiStripFecCabling ( )
inline

Definition at line 34 of file SiStripFecCabling.h.

34 {;}
SiStripFecCabling::~SiStripFecCabling ( )
inline

Definition at line 36 of file SiStripFecCabling.h.

36 {;} //@@ needs implementation!!

Member Function Documentation

void SiStripFecCabling::addDevices ( const FedChannelConnection conn)

Definition at line 66 of file SiStripFecCabling.cc.

References SiStripFecCrate::addDevices(), crates(), crates_, end, and FedChannelConnection::fecCrate().

Referenced by buildFecCabling(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDetIds(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices(), SiStripFedCablingBuilderFromDb::buildFecCablingFromFedConnections(), and SiStripFedCablingFakeESSource::make().

66  {
67  std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin();
68  while ( icrate != crates().end() && (*icrate).fecCrate() != conn.fecCrate() ) { icrate++; }
69  if ( icrate == crates().end() ) {
70  crates_.push_back( SiStripFecCrate( conn ) );
71  } else {
72  const_cast<SiStripFecCrate&>(*icrate).addDevices( conn );
73  }
74 }
const uint16_t & fecCrate() const
std::vector< SiStripFecCrate > crates_
const std::vector< SiStripFecCrate > & crates() const
#define end
Definition: vmac.h:38
void addDevices(const FedChannelConnection &conn)
void SiStripFecCabling::buildFecCabling ( const SiStripFedCabling fed_cabling)

Definition at line 26 of file SiStripFecCabling.cc.

References addDevices(), begin, SiStripFedCabling::connections(), crates(), SiStripFedCabling::feds(), sistrip::invalid_, LogTrace, and sistrip::mlCabling_.

Referenced by SiStripFedCablingBuilderFromDb::getFecCabling(), and SiStripFecCabling().

26  {
28  << "[SiStripFecCabling::" << __func__ << "]"
29  << " Building FEC cabling...";
30 
31  // Retrieve and iterate through FED ids
32  const std::vector<uint16_t>& feds = fed_cabling.feds();
33  std::vector<uint16_t>::const_iterator ifed;
34  for ( ifed = feds.begin(); ifed != feds.end(); ifed++ ) {
35 
36  // Retrieve and iterate through FED channel connections
37  const std::vector<FedChannelConnection>& conns = fed_cabling.connections( *ifed );
38  std::vector<FedChannelConnection>::const_iterator iconn;
39  for ( iconn = conns.begin(); iconn != conns.end(); iconn++ ) {
40 
41  // Check that FED id is not invalid and add devices
42  if ( iconn->fedId() != sistrip::invalid_ ) { addDevices( *iconn ); }
43 
44  }
45  }
46 
47  // Consistency checks
48  for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
49  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
50  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
51  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
52  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
53  //@@ need consistency checks here!
54  }
55  }
56  }
57  }
58  }
60  << "[SiStripFecCabling::" << __func__ << "]"
61  << " Finished building FEC cabling";
62 }
const std::vector< uint16_t > & feds() const
void addDevices(const FedChannelConnection &conn)
const std::vector< SiStripFecCrate > & crates() const
static const char mlCabling_[]
#define LogTrace(id)
static const uint16_t invalid_
Definition: Constants.h:17
#define begin
Definition: vmac.h:31
const std::vector< FedChannelConnection > & connections(uint16_t fed_id) const
void SiStripFecCabling::connections ( std::vector< FedChannelConnection > &  conns) const

Definition at line 78 of file SiStripFecCabling.cc.

References begin, crates(), first, LogTrace, sistrip::mlCabling_, and edm::second().

Referenced by SiStripFedCablingBuilderFromDb::getFedCabling(), and SiStripFedCablingFakeESSource::make().

78  {
80  << "[SiStripFecCabling::" << __func__ << "]"
81  << " Building vector of FedChannelConnection objects...";
82  conns.clear();
83  for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
84  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
85  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
86  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
87  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
88  for ( uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++ ) {
89  conns.push_back( FedChannelConnection( icrate->fecCrate(),
90  ifec->fecSlot(),
91  iring->fecRing(),
92  iccu->ccuAddr(),
93  imod->ccuChan(),
94  imod->activeApvPair( imod->lldChannel(ipair) ).first,
95  imod->activeApvPair( imod->lldChannel(ipair) ).second,
96  imod->dcuId(),
97  imod->detId(),
98  imod->nApvPairs(),
99  imod->fedCh(ipair).fedId_,
100  imod->fedCh(ipair).fedCh_,
101  imod->length(),
102  imod->dcu(),
103  imod->pll(),
104  imod->mux(),
105  imod->lld() ) );
106  uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
107  uint16_t fed_slot = imod->fedCh(ipair).fedSlot_;
108  conns.back().fedCrate( fed_crate );
109  conns.back().fedSlot( fed_slot );
110  }
111  }
112  }
113  }
114  }
115  }
116 }
const std::vector< SiStripFecCrate > & crates() const
U second(std::pair< T, U > const &p)
static const char mlCabling_[]
Class containning control, module, detector and connection information, at the level of a FED channel...
bool first
Definition: L1TdeRCT.cc:94
#define LogTrace(id)
#define begin
Definition: vmac.h:31
NumberOfDevices SiStripFecCabling::countDevices ( ) const

Definition at line 188 of file SiStripFecCabling.cc.

References begin, crates(), spr::find(), NumberOfDevices::nApvPairs0_, NumberOfDevices::nApvPairs1_, NumberOfDevices::nApvPairs2_, NumberOfDevices::nApvPairs3_, NumberOfDevices::nApvPairs_, NumberOfDevices::nApvPairsX_, NumberOfDevices::nApvs_, NumberOfDevices::nCcuAddrs_, NumberOfDevices::nCcuChans_, NumberOfDevices::nDcuIds_, NumberOfDevices::nDcus_, NumberOfDevices::nDetIds_, NumberOfDevices::nFecCrates_, NumberOfDevices::nFecRings_, NumberOfDevices::nFecSlots_, NumberOfDevices::nFedChans_, NumberOfDevices::nFedCrates_, NumberOfDevices::nFedIds_, NumberOfDevices::nFedSlots_, NumberOfDevices::nLlds_, NumberOfDevices::nMuxes_, and NumberOfDevices::nPlls_.

Referenced by SiStripFedCablingBuilderFromDb::buildFecCabling(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices(), and SiStripFedCablingFakeESSource::make().

188  {
189 
190  NumberOfDevices num_of_devices; // simple container class used for counting
191 
192  std::vector<uint16_t> fed_crates;
193  std::vector<uint16_t> fed_slots;
194  std::vector<uint16_t> fed_ids;
195  for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
196  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
197  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
198  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
199  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
200 
201  // APVs
202  if ( imod->activeApv(32) ) { num_of_devices.nApvs_++; }
203  if ( imod->activeApv(33) ) { num_of_devices.nApvs_++; }
204  if ( imod->activeApv(34) ) { num_of_devices.nApvs_++; }
205  if ( imod->activeApv(35) ) { num_of_devices.nApvs_++; }
206  if ( imod->activeApv(36) ) { num_of_devices.nApvs_++; }
207  if ( imod->activeApv(37) ) { num_of_devices.nApvs_++; }
208  if ( imod->dcuId() ) { num_of_devices.nDcuIds_++; }
209  if ( imod->detId() ) { num_of_devices.nDetIds_++; }
210 
211  // APV pairs
212  num_of_devices.nApvPairs_ += imod->nApvPairs();
213  if ( imod->nApvPairs() == 0 ) { num_of_devices.nApvPairs0_++; }
214  else if ( imod->nApvPairs() == 1 ) { num_of_devices.nApvPairs1_++; }
215  else if ( imod->nApvPairs() == 2 ) { num_of_devices.nApvPairs2_++; }
216  else if ( imod->nApvPairs() == 3 ) { num_of_devices.nApvPairs3_++; }
217  else { num_of_devices.nApvPairsX_++; }
218 
219  // FED crates, slots, ids, channels
220  for ( uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++ ) {
221 
222  uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
223  uint16_t fed_slot = imod->fedCh(ipair).fedSlot_;
224  uint16_t fed_id = imod->fedCh(ipair).fedId_;
225 
226  if ( fed_id ) {
227 
228  num_of_devices.nFedChans_++;
229 
230  std::vector<uint16_t>::iterator icrate = find( fed_crates.begin(), fed_crates.end(), fed_crate );
231  if ( icrate == fed_crates.end() ) {
232  num_of_devices.nFedCrates_++;
233  fed_crates.push_back(fed_crate);
234  }
235 
236  std::vector<uint16_t>::iterator islot = find( fed_slots.begin(), fed_slots.end(), fed_slot );
237  if ( islot == fed_slots.end() ) {
238  num_of_devices.nFedSlots_++;
239  fed_slots.push_back(fed_slot);
240  }
241 
242  std::vector<uint16_t>::iterator ifed = find( fed_ids.begin(), fed_ids.end(), fed_id );
243  if ( ifed == fed_ids.end() ) {
244  num_of_devices.nFedIds_++;
245  fed_ids.push_back(fed_id);
246  }
247 
248  }
249 
250  }
251 
252  // FE devices
253  if ( imod->dcu() ) { num_of_devices.nDcus_++; }
254  if ( imod->mux() ) { num_of_devices.nMuxes_++; }
255  if ( imod->pll() ) { num_of_devices.nPlls_++; }
256  if ( imod->lld() ) { num_of_devices.nLlds_++; }
257 
258  // FE modules
259  num_of_devices.nCcuChans_++;
260  }
261  num_of_devices.nCcuAddrs_++;
262  }
263  num_of_devices.nFecRings_++;
264  }
265  num_of_devices.nFecSlots_++;
266  }
267  num_of_devices.nFecCrates_++;
268  }
269 
270  return num_of_devices;
271 
272 }
uint32_t nFecCrates_
const std::vector< SiStripFecCrate > & crates() const
void find(edm::Handle< EcalRecHitCollection > &hits, DetId thisDet, std::vector< EcalRecHitCollection::const_iterator > &hit, bool debug=false)
Definition: FindCaloHit.cc:7
uint32_t nApvPairs3_
uint32_t nApvPairsX_
uint32_t nApvPairs0_
Simple container class for counting devices.
uint32_t nApvPairs2_
#define begin
Definition: vmac.h:31
uint32_t nApvPairs1_
uint32_t nFedCrates_
const std::vector< SiStripFecCrate > & SiStripFecCabling::crates ( ) const
inline
void SiStripFecCabling::dcuId ( const FedChannelConnection conn)
inline

Definition at line 88 of file SiStripFecCabling.h.

References FedChannelConnection::dcuId(), and module().

Referenced by SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices().

88  {
89  const_cast<SiStripModule&>(module(conn)).dcuId(conn.dcuId());
90 }
Device and connection information at the level of a front-end module.
Definition: SiStripModule.h:25
const SiStripModule & module(const FedChannelConnection &conn) const
void dcuId(const FedChannelConnection &conn)
const uint32_t & dcuId() const
void SiStripFecCabling::detId ( const FedChannelConnection conn)
inline

Definition at line 92 of file SiStripFecCabling.h.

References FedChannelConnection::detId(), and module().

92  {
93  const_cast<SiStripModule&>(module(conn)).detId(conn.detId());
94 }
Device and connection information at the level of a front-end module.
Definition: SiStripModule.h:25
const SiStripModule & module(const FedChannelConnection &conn) const
const uint32_t & detId() const
void detId(const FedChannelConnection &conn)
const std::vector< SiStripFec > & SiStripFecCabling::fecs ( ) const
inline

Definition at line 82 of file SiStripFecCabling.h.

References crates_.

82  {
83  static std::vector<SiStripFec> my_fecs;
84  if ( !crates_.empty() ) { return crates_[0].fecs(); }
85  else { return my_fecs; }
86 }
std::vector< SiStripFecCrate > crates_
const SiStripModule & SiStripFecCabling::module ( const FedChannelConnection conn) const

Definition at line 120 of file SiStripFecCabling.cc.

References FedChannelConnection::ccuAddr(), FedChannelConnection::ccuChan(), crates(), end, FedChannelConnection::fecCrate(), FedChannelConnection::fecRing(), FedChannelConnection::fecSlot(), sistrip::mlCabling_, and groupFilesInBlocks::temp.

Referenced by dcuId(), detId(), SiStripCommissioningSource::fillCablingHistos(), module(), and nApvPairs().

120  {
121 
122  std::stringstream ss;
123  std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin();
124  while ( icrate != crates().end() && icrate->fecCrate() != conn.fecCrate() ) { icrate++; }
125  if ( icrate != crates().end() ) {
126  std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin();
127  while ( ifec != icrate->fecs().end() && ifec->fecSlot() != conn.fecSlot() ) { ifec++; }
128  if ( ifec != icrate->fecs().end() ) {
129  std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin();
130  while ( iring != ifec->rings().end() && iring->fecRing() != conn.fecRing() ) { iring++; }
131  if ( iring != ifec->rings().end() ) {
132  std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin();
133  while ( iccu != iring->ccus().end() && iccu->ccuAddr() != conn.ccuAddr() ) { iccu++; }
134  if ( iccu != iring->ccus().end() ) {
135  std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin();
136  while ( imod != iccu->modules().end() && imod->ccuChan() != conn.ccuChan() ) { imod++; }
137  if ( imod != iccu->modules().end() ) {
138  return *imod;
139  } else {
140  ss << "[SiStripFecCabling::" << __func__ << "]"
141  << " CCU channel " << conn.ccuChan()
142  << " not found!"; }
143  } else {
144  ss << "[SiStripFecCabling::" << __func__ << "]"
145  << " CCU address " << conn.ccuAddr()
146  << " not found!"; }
147  } else {
148  ss << "[SiStripFecCabling::" << __func__ << "]"
149  << " FEC ring " << conn.fecRing()
150  << " not found!"; }
151  } else {
152  ss << "[SiStripFecCabling::" << __func__ << "]"
153  << " FEC slot " << conn.fecSlot()
154  << " not found!"; }
155  } else {
156  ss << "[SiStripFecCabling::" << __func__ << "]"
157  << " FEC crate " << conn.fecCrate()
158  << " not found!";
159  }
160 
161  if ( !ss.str().empty() ) { edm::LogWarning(mlCabling_) << ss.str(); }
162  static FedChannelConnection temp;
163  static const SiStripModule module(temp);
164  return module;
165 }
const uint16_t & fecSlot() const
Device and connection information at the level of a front-end module.
Definition: SiStripModule.h:25
const uint16_t & fecCrate() const
const SiStripModule & module(const FedChannelConnection &conn) const
const std::vector< SiStripFecCrate > & crates() const
static const char mlCabling_[]
const uint16_t & fecRing() const
Class containning control, module, detector and connection information, at the level of a FED channel...
const uint16_t & ccuChan() const
#define end
Definition: vmac.h:38
const uint16_t & ccuAddr() const
const SiStripModule & SiStripFecCabling::module ( const uint32_t &  dcu_id) const

Definition at line 169 of file SiStripFecCabling.cc.

References begin, crates(), module(), and groupFilesInBlocks::temp.

169  {
170  for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
171  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
172  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
173  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
174  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
175  if ( (*imod).dcuId() == dcu_id ) { return *imod; }
176  }
177  }
178  }
179  }
180  }
181  static FedChannelConnection temp;
182  static const SiStripModule module(temp);
183  return module;
184 }
Device and connection information at the level of a front-end module.
Definition: SiStripModule.h:25
const SiStripModule & module(const FedChannelConnection &conn) const
const std::vector< SiStripFecCrate > & crates() const
Class containning control, module, detector and connection information, at the level of a FED channel...
#define begin
Definition: vmac.h:31
void SiStripFecCabling::nApvPairs ( const FedChannelConnection conn)
inline

Definition at line 96 of file SiStripFecCabling.h.

References module(), and FedChannelConnection::nApvPairs().

96  {
97  const_cast<SiStripModule&>(module(conn)).nApvPairs(conn.nApvPairs());
98 }
Device and connection information at the level of a front-end module.
Definition: SiStripModule.h:25
void nApvPairs(const FedChannelConnection &conn)
const SiStripModule & module(const FedChannelConnection &conn) const
const uint16_t & nApvPairs() const
void SiStripFecCabling::print ( std::stringstream &  ss) const

Definition at line 276 of file SiStripFecCabling.cc.

References begin, crates(), sistrip::invalid_, findQualityFiles::jj, pileupDistInMC::total, and TrackValidation_HighPurity_cff::valid.

Referenced by operator<<().

276  {
277  uint32_t valid = 0;
278  uint32_t total = 0;
279  ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
280  ss << "Printing cabling for " << crates().size() << " crates" << std::endl;
281  for ( std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); icrate++ ) {
282  ss << "Printing cabling for " << icrate->fecs().size() << " FECs for crate " << icrate->fecCrate() << std::endl;
283  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
284  ss << "Printing cabling for " << ifec->rings().size() << " rings for FEC " << ifec->fecSlot() << std::endl;
285  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
286  ss << "Printing cabling for " << iring->ccus().size() << " CCUs for ring " << iring->fecRing() << std::endl;
287  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
288  ss << "Printing cabling for " << iccu->modules().size() << " modules for CCU " << iccu->ccuAddr() << std::endl;
289  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
290 
291  SiStripModule::FedCabling conns = imod->fedChannels();
292  SiStripModule::FedCabling::const_iterator ii = conns.begin();
293  SiStripModule::FedCabling::const_iterator jj = conns.end();
294  for ( ; ii != jj; ++ii ) {
295  if ( ii->second.fedId_ != sistrip::invalid_ &&
296  ii->second.fedCh_ != sistrip::invalid_ ) { valid++; }
297  total++;
298  }
299  ss << *imod << std::endl;
300  }
301  }
302  }
303  }
304  }
305  ss << "Number of connected: " << valid << std::endl
306  << "Number of connections: " << total << std::endl;
307 }
const std::vector< SiStripFecCrate > & crates() const
static const uint16_t invalid_
Definition: Constants.h:17
#define begin
Definition: vmac.h:31
std::map< uint16_t, FedChannel > FedCabling
Definition: SiStripModule.h:60
void SiStripFecCabling::terse ( std::stringstream &  ss) const

Definition at line 311 of file SiStripFecCabling.cc.

References begin, and crates().

311  {
312  ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
313  for ( std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); icrate++ ) {
314  for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
315  for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
316  for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
317  for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
318  imod->terse(ss);
319  ss << std::endl;
320  }
321  }
322  }
323  }
324  }
325 }
const std::vector< SiStripFecCrate > & crates() const
#define begin
Definition: vmac.h:31

Member Data Documentation

std::vector<SiStripFecCrate> SiStripFecCabling::crates_
private

Definition at line 73 of file SiStripFecCabling.h.

Referenced by addDevices(), crates(), fecs(), and SiStripFecCabling().