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DTTSCand.cc
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1 //-------------------------------------------------
2 //
3 // Class: DTTSCand.cpp
4 //
5 // Description: A Trigger Server Candidate
6 //
7 //
8 // Author List:
9 // C. Grandi
10 // Modifications:
11 // S. Marcellini, D. Bonacorsi
12 // 04/01/2007 : C. Battilana local config update
13 //
14 //--------------------------------------------------
15 
16 //-----------------------
17 // This Class's Header --
18 //-----------------------
20 
21 //-------------------------------
22 // Collaborating Class Headers --
23 //-------------------------------
25 
26 //---------------
27 // C++ Headers --
28 //---------------
29 #include <iostream>
30 
31 //----------------
32 
33 // Constructors --
34 //----------------
35 
37  int ifs, int pos)
38  : _tss(tss), _tctrig(tctrig), _tcPos(pos), _isCarry(0) {
39 
40  _dataword.one(); // reset dataword to 0x1ff
41 
42  // SM sector collector Set bit 14 instead of 8, for 1st/2nd track to allow extra space
43  // if(ifs==1)_dataword.unset(8); // set bit 8 (0=first, 1=second tracks)
44  if(ifs==1)_dataword.unset(14); // set bit 14 (0=first, 1=second tracks)
45 
46 }
47 
49  : _tss(tscand._tss), _tctrig(tscand._tctrig), _tcPos(tscand._tcPos),
50  _isCarry(tscand._isCarry) {
51 
52 
53 }
54 
55 
57 
58 //--------------
59 // Destructor --
60 //--------------
62 }
63 
64 
65 //--------------
66 // Operations --
67 //--------------
68 
69 DTTSCand&
70 DTTSCand::operator=(const DTTSCand& tscand) {
71  if(this != &tscand){
72  _tss = tscand._tss;
73  _tctrig = tscand._tctrig;
74  _tcPos = tscand._tcPos;
75  _isCarry = tscand._isCarry;
76  }
77  return *this;
78 }
79 
80 void
82  _tctrig=0;
83  _dataword.one();
84 
85  _isCarry=0;
86 
87 }
88 
89 void
91  // first/second track already set. Set other 3 bits
92  int itk=_dataword.element(14); // first tracks 0, second tracks 1
93 
94  clearBits();
95  if(_tctrig->pvK()>32|| _tctrig->pvK()<0){ // Check K within 5 bits range
96  std::cout << "DTTSCand::setBitsTss() pvK outside valid range: " << _tctrig->pvK();
97  std::cout << " deltaPsiR set to 31" << std::endl;
98  }
99  else {
100  // assign preview in dataword (common to any other assignment)
101  _dataword.assign(0,5,_tctrig->pvK());
102  // _dataword.assign(0,5,0);
103 
104  int posH=-1;
105  int posI=-1;
106  int posC=-1;
107  switch(config()->TssMasking(itk)) {
108  case 123: // H/L, In/Out, Corr/NotC
109  posH = 7;
110  posI = 6;
111  posC = 5;
112  break;
113  case 132: // H/L, Corr/NotC, In/Out
114  posH = 7;
115  posI = 5;
116  posC = 6;
117  break;
118  case 213: // In/Out, H/L, Corr/NotC
119  posH = 6;
120  posI = 7;
121  posC = 5;
122  break;
123  case 231: // In/Out, Corr/NotC, H/L
124  posH = 5;
125  posI = 7;
126  posC = 6;
127  break;
128  case 312: // Corr/NotC, H/L, In/Out
129  posH = 6;
130  posI = 5;
131  posC = 7;
132  break;
133  case 321: // Corr/NotC, In/Out, H/L
134  posH = 5;
135  posI = 6;
136  posC = 7;
137  break;
138  default:
139  std::cout << "DTTSCand::DTTSCand(): masking not correct: ";
140  std::cout << config()->TssMasking(itk);
141  std::cout << " All bits set to 1" << std::endl;
142  }
143  // Masking:
144  bool enaH = config()->TssHtrigEna(itk);
145  bool enaI = config()->TssInOutEna(itk);
146  bool enaC = config()->TssCorrEna(itk) ;
147  if(isCarry()) {
148  // Special setting for carry
149  enaH = config()->TssHtrigEnaCarry();
150  enaI = config()->TssInOutEnaCarry();
151  enaC = config()->TssCorrEnaCarry() ;
152  }
153  // Bits set to 0 give higher priority:
154  if(isHtrig()&&enaH&&posH>0)_dataword.unset(posH);
155  if(isInner()&&enaI&&posI>0)_dataword.unset(posI);
156  if(isCorr() &&enaC&&posC>0)_dataword.unset(posC);
157  }
158 
159 }
160 
161 
162 void
164  // first/second track already set. Set other 4 bits (1 for null, 3 for a2, a1, a0)
165  clearBitsBkmod();
166  // std::cout << " clearbits in TSM bk mode " << _dataword.print() << std::endl;
167 
168  int a2 = 6;
169  int a1 = 5;
170  int a0 = 4;
171  //
172  // std::cout << " _tctrig->qdec(): " << _tctrig->qdec() << std::endl;
173  if( _tctrig->qdec()==6 ) { _dataword.unset(a2); _dataword.unset(a1); _dataword.unset(a0); } // 1-000
174  if( _tctrig->qdec()==5 ) { _dataword.unset(a2); _dataword.unset(a1); } // 1-001
175  if( _tctrig->qdec()==4 ) { _dataword.unset(a2); _dataword.unset(a0); } // 1-010
176  if( _tctrig->qdec()==3 ) { _dataword.unset(a1); } // 1-101
177  if( _tctrig->qdec()==2 ) { _dataword.unset(a1); _dataword.unset(a0); } // 1-100
178 
179  if( _tctrig->qdec()==0 ) { _dataword.unset(a0); } // 1-110
180 
181  // std::cout << " set Bits TSM back up " << _dataword.print() << std::endl;
182 }
183 
184 
185 void
187  // first/second track already set. Set other 3 bits
188  int itk=_dataword.element(14); // first tracks 0, second tracks 1
189 
190  clearBits();
191 
192  if(_tctrig->pvK()>31|| _tctrig->pvK()<0){ // Check K within 5 bits range
193  std::cout << "DTTSCand::setBitsTsm pvK outside valid range: " << _tctrig->pvK();
194  std::cout << " deltaPsiR set to 31" << std::endl;
195  }
196  else {
197  // SM double TSM
198  // assign preview in dataword (common to any other assignment)
199  _dataword.assign(0,5,_tctrig->pvK());
200  // _dataword.assign(0,5,0);
201  //
202 
203  int posH=-1;
204  int posI=-1;
205  int posC=-1;
206  switch(config()->TsmMasking(itk)) {
207  case 123: // H/L, In/Out, Corr/NotC
208  posH = 7;
209  posI = 6;
210  posC = 5;
211  break;
212  case 132: // H/L, Corr/NotC, In/Out
213  posH = 7;
214  posI = 5;
215  posC = 6;
216  break;
217  case 213: // In/Out, H/L, Corr/NotC
218  posH = 6;
219  posI = 7;
220  posC = 5;
221  break;
222  case 231: // In/Out, Corr/NotC, H/L
223  posH = 5;
224  posI = 7;
225  posC = 6;
226  break;
227  case 312: // Corr/NotC, H/L, In/Out
228  posH = 6;
229  posI = 5;
230  posC = 7;
231  break;
232  case 321: // Corr/NotC, In/Out, H/L
233  posH = 5;
234  posI = 6;
235  posC = 7;
236  break;
237  default:
238  std::cout << "DTTSCand::DTTSCand(): masking not correct: ";
239  std::cout << config()->TssMasking(itk);
240  std::cout << " All bits set to 1" << std::endl;
241 
242  // Masking:
243  bool enaH = config()->TsmHtrigEna(itk);
244  bool enaI = config()->TsmInOutEna(itk);
245  bool enaC = config()->TsmCorrEna(itk) ;
246  if(isCarry()) {
247  // Special setting for carry
248  enaH = config()->TsmHtrigEnaCarry();
249  enaI = config()->TsmInOutEnaCarry();
250  enaC = config()->TsmCorrEnaCarry() ;
251  }
252  // Bits set to 0 give higher priority:
253  if(isHtrig()&&enaH&&posH>0)_dataword.unset(posH);
254  if(isInner()&&enaI&&posI>0)_dataword.unset(posI);
255  if(isCorr() &&enaC&&posC>0)_dataword.unset(posC);
256 
257  }
258  }
259 
260 
261 }
262 void
264  std::cout << " First=" << isFirst();
265  std::cout << " HTRIG=" << isHtrig();
266  std::cout << " Inner=" << isInner();
267  std::cout << " Corr=" << isCorr();
268  std::cout << " Kpv=" << tracoTr()->pvK();
269  std::cout << " dataword=";
270  _dataword.print();
271  std::cout << std::endl;
272 }
273 
int _isCarry
Definition: DTTSCand.h:157
bool TsmInOutEna(int i) const
Enable Inner SL checking in TSM for sort1/2.
Definition: DTConfigTSPhi.h:96
void setBitsTss()
Set the quality bits for DTTSS analysis.
Definition: DTTSCand.cc:90
bool TssInOutEnaCarry() const
Enable Inner SL checking in TSS for carry.
Definition: DTConfigTSPhi.h:78
bool TsmHtrigEna(int i) const
Enable Htrig checking in TSM for sort1/2.
Definition: DTConfigTSPhi.h:90
int isHtrig() const
Return HTRIG/LTRIG bit.
Definition: DTTSCand.h:103
int _tcPos
Definition: DTTSCand.h:155
~DTTSCand()
Destructor.
Definition: DTTSCand.cc:61
void clearBitsBkmod()
Clear (set to 1) all the bits (back-up mode)
Definition: DTTSCand.h:76
int TsmMasking(int i) const
Order of quality bits in TSM for sort1/2.
Definition: DTConfigTSPhi.h:87
int TssMasking(int i) const
Order of quality bits in TSS for sort1/2.
Definition: DTConfigTSPhi.h:66
void clear()
Clear the trigger.
Definition: DTTSCand.cc:81
const DTTracoTrigData * _tctrig
Definition: DTTSCand.h:152
int isFirst() const
Return the first/second track bit.
Definition: DTTSCand.h:100
void one()
Definition: BitArray.h:223
bool TssCorrEnaCarry() const
Enable Correlation checking in TSS for carry.
Definition: DTConfigTSPhi.h:84
DTTSS * _tss
Definition: DTTSCand.h:151
int pvK() const
Return the preview K.
DTTSCand & operator=(const DTTSCand &tscand)
Assignment operator.
Definition: DTTSCand.cc:70
bool TsmHtrigEnaCarry() const
Enable Htrig checking in TSM for carry.
Definition: DTConfigTSPhi.h:93
void setBitsTsm()
Set the quality bits for DTTSM analysis.
Definition: DTTSCand.cc:186
int isCarry() const
Return the carry bit.
Definition: DTTSCand.h:112
void print() const
Print the trigger.
Definition: DTTSCand.cc:263
void unset(const int i)
Definition: BitArray.h:231
bool TssHtrigEnaCarry() const
Enable Htrig checking in TSS for carry.
Definition: DTConfigTSPhi.h:72
DTTSCand()
Constructor.
Definition: DTTSCand.cc:56
DTConfigTSPhi * config() const
Configuration set.
Definition: DTTSCand.h:82
const DTTracoTrigData * tracoTr() const
Return associated TRACO trigger.
Definition: DTTSCand.h:85
int element(const int pos) const
Definition: BitArray.h:210
Definition: DTTSS.h:38
bool TsmCorrEnaCarry() const
Enable Correlation checking in TSM for carry.
void clearBits()
Clear (set to 1) the quality bits (but first/second track bit)
Definition: DTTSCand.h:73
bool TsmCorrEna(int i) const
Enable Correlation checking in TSM for sort1/2.
int isInner() const
Return Inner/Outer bit.
Definition: DTTSCand.h:106
void assign(const int p, const int n, const int val)
Definition: BitArray.h:239
bool TssInOutEna(int i) const
Enable Inner SL checking in TSS for sort1/2.
Definition: DTConfigTSPhi.h:75
int qdec() const
Return the trigger code in new format.
bool TsmInOutEnaCarry() const
Enable Inner SL checking in TSM for carry.
Definition: DTConfigTSPhi.h:99
BitArray< 15 > _dataword
Definition: DTTSCand.h:153
tuple cout
Definition: gather_cfg.py:41
std::ostream & print(std::ostream &o=std::cout) const
Definition: BitArray.h:345
bool TssCorrEna(int i) const
Enable Correlation checking in TSS for sort1/2.
Definition: DTConfigTSPhi.h:81
void setBitsBkmod()
Set the bits for TSM back-up mode.
Definition: DTTSCand.cc:163
int isCorr() const
Return correlation bit.
Definition: DTTSCand.h:109
bool TssHtrigEna(int i) const
Enable Htrig checking in TSS for sort1/2.
Definition: DTConfigTSPhi.h:69