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PixelFEDCard.cc
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1 // Read the pixelFED setup parameters from an ASCII file
2 // Will Johns & Danek Kotlinski 04/06.
3 
4 #include <iostream>
5 
6 #include "CalibFormats/SiPixelObjects/interface/PixelFEDCard.h"
7 #include "CalibFormats/SiPixelObjects/interface/PixelTimeFormatter.h"
8 
9 #include <cassert>
10 #include <sstream>
11 #include <map>
12 #include <stdexcept>
13 
14 using namespace std;
15 
16 using namespace pos;
17 
18 PixelFEDCard::PixelFEDCard() : PixelConfigBase(" ", " ", " ") { clear(); }
19 
20 // modified by MR on 24-04-2008 12:05:42
21 // Read configuration from DB
22 PixelFEDCard::PixelFEDCard(vector<vector<string> > &tableMat) : PixelConfigBase(" ", " ", " ") {
23  std::string mthn = "[PixelFEDCard::PixelFEDCard()]\t\t ";
24  vector<string> ins = tableMat[0];
25  map<string, int> colM;
26  vector<string> colNames;
27  bool first = true;
128  colNames.push_back("BUSYWHENBEHIND");
129  colNames.push_back("FEATUREREGISTER");
130  colNames.push_back("FIFO2LIMIT");
131  colNames.push_back("TIMEOUTOROOSLIMIT");
132  colNames.push_back("LASTDACOFF");
133  colNames.push_back("SIMHITSPERROC");
134  colNames.push_back("BUSYHOLDMIN");
135  colNames.push_back("SPARE1");
136  colNames.push_back("SPARE2");
137  colNames.push_back("SPARE3");
138  colNames.push_back("SPARE4");
139  colNames.push_back("SPARE5");
140  colNames.push_back("SPARE6");
141  colNames.push_back("SPARE7");
142  colNames.push_back("SPARE8");
143  colNames.push_back("SPARE9");
144  colNames.push_back("SPARE10");
145  colNames.push_back("CONFIG_KEY");
146  colNames.push_back("KEY_TYPE");
147  colNames.push_back("KEY_ALIAS_ID");
148  colNames.push_back("KEY_ALIAS");
149  colNames.push_back("VERSION");
150  colNames.push_back("KIND_OF_COND");
151  colNames.push_back("CRATE_LABEL");
152  colNames.push_back("CRATE_NUMBER");
153  colNames.push_back("SLOT_NUMBER");
154  colNames.push_back("VME_ADDRS_HEX");
155  colNames.push_back("PIXEL_FED");
156  colNames.push_back("CHANNEL_ID");
157  colNames.push_back("NUM_ROCS");
158  colNames.push_back("CHAN_OFFST_DAC");
159  colNames.push_back("CHAN_DELAY");
160  colNames.push_back("CHAN_BHIGH");
161  colNames.push_back("CHAN_BLOW");
162  colNames.push_back("CHAN_UB");
163  colNames.push_back("OPT1_CAP");
164  colNames.push_back("OPT2_CAP");
165  colNames.push_back("OPT3_CAP");
166  colNames.push_back("OPT1_INP");
167  colNames.push_back("OPT2_INP");
168  colNames.push_back("OPT3_INP");
169  colNames.push_back("OPT1_OUT");
170  colNames.push_back("OPT2_OUT");
171  colNames.push_back("OPT3_OUT");
172  colNames.push_back("NORTH_CLKPHB");
173  colNames.push_back("NORTHCENTER_CLKPHB");
174  colNames.push_back("SOUTHCENTER_CLKPHB");
175  colNames.push_back("SOUTH_CLKPHB");
176  colNames.push_back("NORTH_CTRL");
177  colNames.push_back("NORTHCENTER_CTRL");
178  colNames.push_back("SOUTHCENTER_CTRL");
179  colNames.push_back("SOUTH_CTRL");
180  colNames.push_back("REG0_TTCRX_FDLA");
181  colNames.push_back("REG1_TTCRX_FDLA");
182  colNames.push_back("REG2_TTCRX_CDLA");
183  colNames.push_back("REG3_TTCRX_CLKD2");
184  colNames.push_back("CENTER_CTRL");
185  colNames.push_back("CENTER_MODE");
186  colNames.push_back("B1_ADCGN");
187  colNames.push_back("B2_ADCGN");
188  colNames.push_back("B3_ADCGN");
189  colNames.push_back("B4_ADCGN");
190  colNames.push_back("NORTH_BADJ");
191  colNames.push_back("NORTHCENTER_BADJ");
192  colNames.push_back("SOUTHCENTER_BADJ");
193  colNames.push_back("SOUTH_BADJ");
194  colNames.push_back("NORTH_TBMMASK");
195  colNames.push_back("NORTHCENTER_TBMMASK");
196  colNames.push_back("SOUTHCENTER_TBMMASK");
197  colNames.push_back("SOUTH_TBMMASK");
198  colNames.push_back("NORTH_PWORD");
199  colNames.push_back("NORTHCENTER_PWORD");
200  colNames.push_back("SOUTH_PWORD");
201  colNames.push_back("SOUTHCENTER_PWORD");
202  colNames.push_back("SPECDAC");
203  colNames.push_back("OOS_LVL");
204  colNames.push_back("ERR_LVL");
205  colNames.push_back("NORTH_FIFO1_BZ_LVL");
206  colNames.push_back("NORTHCENTER_FIFO1_BZ_LVL");
207  colNames.push_back("SOUTHCENTER_FIFO1_BZ_LVL");
208  colNames.push_back("SOUTH_FIFO1_BZ_LVL");
209  colNames.push_back("FIFO3_WRN_LVL");
210  colNames.push_back("FED_MASTER_DELAY");
211  colNames.push_back("NO_HITLIMIT");
212  colNames.push_back("NC_HITLIMIT");
213  colNames.push_back("SC_HITLIMIT");
214  colNames.push_back("SO_HITLIMIT");
215  colNames.push_back("NO_TESTREG");
216  colNames.push_back("NC_TESTREG");
217  colNames.push_back("SC_TESTREG");
218  colNames.push_back("SO_TESTREG");
219  colNames.push_back("TRIGGERHOLDOFF");
220 
221  for (unsigned int c = 0; c < ins.size(); c++) {
222  for (unsigned int n = 0; n < colNames.size(); n++) {
223  if (tableMat[0][c] == colNames[n]) {
224  colM[colNames[n]] = c;
225  break;
226  }
227  }
228  } //end for
229  for (unsigned int n = 0; n < colNames.size(); n++) {
230  if (colM.find(colNames[n]) == colM.end()) {
231  std::cerr << __LINE__ << "]\t[PixelFEDCard::PixelFEDCard]\tCouldn't find in the database the column with name "
232  << colNames[n] << std::endl;
233  assert(0);
234  }
235  }
236  // disentagle different tables
237  int size[3];
238  int indexsize = 0;
239  for (unsigned int r = 0; r < tableMat.size(); r++) { //Goes to every row of the Matrix
240  if (tableMat[r].empty()) {
241  // cout << __LINE__ << "]\t" << mthn << "__________________ NEW TABLE __________________"<< endl ;
242  size[indexsize] = r;
243  // cout << __LINE__ << "]\t" << mthn << "size[" << indexsize << "] = " << size[indexsize] << endl ;
244  indexsize++;
245  continue;
246  }
247  for (vector<string>::iterator it = tableMat[r].begin(); it != tableMat[r].end(); ++it) {
248  // cout << __LINE__ << "]\t" << mthn << *it <<"["<<&*it<<"]\t" ;
249  // cout << __LINE__ << "]\t" << mthn << *it <<"\t" ;
250  }
251  // cout << __LINE__ << "]\t" << mthn << endl ;
252  }
253 
254  // Read below quantities pertaining to a single FED that are equal accross 36 channels
255  if (first) {
256  first = false;
257  //VME base address
258  //Fed Base Address
259  sscanf(tableMat[1][colM["VME_ADDRS_HEX"]].c_str(), "%lx", &FEDBASE_0);
260  // sscanf(tableMat[1][colM["PIXEL_FED"]].c_str(), "PxlFED_%ld",&fedNumber);
261  fedNumber = atoi(tableMat[1][colM["PIXEL_FED"]].c_str());
262  //Settable optical input parameters (one for each 12-receiver)
263  opt_cap[0] = atoi(tableMat[1][colM["OPT1_CAP"]].c_str());
264  opt_cap[1] = atoi(tableMat[1][colM["OPT2_CAP"]].c_str());
265  opt_cap[2] = atoi(tableMat[1][colM["OPT3_CAP"]].c_str());
266  opt_inadj[0] = atoi(tableMat[1][colM["OPT1_INP"]].c_str());
267  opt_inadj[1] = atoi(tableMat[1][colM["OPT2_INP"]].c_str());
268  opt_inadj[2] = atoi(tableMat[1][colM["OPT3_INP"]].c_str());
269  opt_ouadj[0] = atoi(tableMat[1][colM["OPT1_OUT"]].c_str());
270  opt_ouadj[1] = atoi(tableMat[1][colM["OPT2_OUT"]].c_str());
271  opt_ouadj[2] = atoi(tableMat[1][colM["OPT3_OUT"]].c_str());
272 
273  //clock phases, use bits 0-8, select the clock edged
274  clkphs1_9 = atoi(tableMat[1][colM["NORTH_CLKPHB"]].c_str()); // TO BE VERIFIED
275  clkphs10_18 = atoi(tableMat[1][colM["NORTHCENTER_CLKPHB"]].c_str()); // TO BE VERIFIED
276  clkphs19_27 = atoi(tableMat[1][colM["SOUTHCENTER_CLKPHB"]].c_str()); // TO BE VERIFIED
277  clkphs28_36 = atoi(tableMat[1][colM["SOUTH_CLKPHB"]].c_str()); // TO BE VERIFIED
278 
279  // Control register and delays for the TTCrx
280  FineDes1Del = atoi(tableMat[1][colM["REG0_TTCRX_FDLA"]].c_str());
281  FineDes2Del = atoi(tableMat[1][colM["REG1_TTCRX_FDLA"]].c_str());
282  CoarseDel = atoi(tableMat[1][colM["REG2_TTCRX_CDLA"]].c_str());
283  ClkDes2 = atoi(tableMat[1][colM["REG3_TTCRX_CLKD2"]].c_str());
284 
285  Ccntrl = atoi(tableMat[1][colM["CENTER_CTRL"]].c_str());
286  modeRegister = atoi(tableMat[1][colM["CENTER_MODE"]].c_str());
287 
288  //data Regs adjustable fifo Almost Full levels
289  Nfifo1Bzlvl = atoi(tableMat[1][colM["NORTH_FIFO1_BZ_LVL"]].c_str());
290  NCfifo1Bzlvl = atoi(tableMat[1][colM["NORTHCENTER_FIFO1_BZ_LVL"]].c_str());
291  SCfifo1Bzlvl = atoi(tableMat[1][colM["SOUTHCENTER_FIFO1_BZ_LVL"]].c_str());
292  Sfifo1Bzlvl = atoi(tableMat[1][colM["SOUTH_FIFO1_BZ_LVL"]].c_str());
293 
294  //Bits (1st 8) used to mask TBM trailer bits
295  N_TBMmask = atoi(tableMat[1][colM["NORTH_TBMMASK"]].c_str());
296  NC_TBMmask = atoi(tableMat[1][colM["NORTHCENTER_TBMMASK"]].c_str());
297  SC_TBMmask = atoi(tableMat[1][colM["SOUTHCENTER_TBMMASK"]].c_str());
298  S_TBMmask = atoi(tableMat[1][colM["SOUTH_TBMMASK"]].c_str());
299 
300  //Bits (1st 8) used to set the Private Word in the gap and filler words
301  N_Pword = atoi(tableMat[1][colM["NORTH_PWORD"]].c_str());
302  NC_Pword = atoi(tableMat[1][colM["NORTHCENTER_PWORD"]].c_str());
303  SC_Pword = atoi(tableMat[1][colM["SOUTHCENTER_PWORD"]].c_str());
304  S_Pword = atoi(tableMat[1][colM["SOUTH_PWORD"]].c_str());
305 
306  Nbaseln = atoi(tableMat[1][colM["NORTH_BADJ"]].c_str());
307  NCbaseln = atoi(tableMat[1][colM["NORTHCENTER_BADJ"]].c_str());
308  SCbaseln = atoi(tableMat[1][colM["SOUTHCENTER_BADJ"]].c_str());
309  Sbaseln = atoi(tableMat[1][colM["SOUTH_BADJ"]].c_str());
310 
311  Ncntrl = atoi(tableMat[1][colM["NORTH_CTRL"]].c_str());
312  NCcntrl = atoi(tableMat[1][colM["NORTHCENTER_CTRL"]].c_str());
313  SCcntrl = atoi(tableMat[1][colM["SOUTHCENTER_CTRL"]].c_str());
314  Scntrl = atoi(tableMat[1][colM["SOUTH_CTRL"]].c_str());
315 
316  //These bit sets the special dac mode for random triggers
317  SpecialDac = atoi(tableMat[1][colM["SPECDAC"]].c_str());
318 
319  //These bits set the number of Out of consecutive out of sync events until a TTs OOs
320  Ooslvl = atoi(tableMat[1][colM["OOS_LVL"]].c_str());
321  //These bits set the number of Empty events until a TTs Error
322  Errlvl = atoi(tableMat[1][colM["ERR_LVL"]].c_str());
323 
324  //Control Regs for setting ADC 1Vpp and 2Vpp
325  Nadcg = atoi(tableMat[1][colM["B1_ADCGN"]].c_str());
326  NCadcg = atoi(tableMat[1][colM["B2_ADCGN"]].c_str());
327  SCadcg = atoi(tableMat[1][colM["B3_ADCGN"]].c_str());
328  Sadcg = atoi(tableMat[1][colM["B4_ADCGN"]].c_str());
329  fifo3Wrnlvl = atoi(tableMat[1][colM["FIFO3_WRN_LVL"]].c_str());
330  FedTTCDelay = atoi(tableMat[1][colM["FED_MASTER_DELAY"]].c_str());
331  N_hitlimit = atoi(tableMat[1][colM["NO_HITLIMIT"]].c_str());
332  NC_hitlimit = atoi(tableMat[1][colM["NC_HITLIMIT"]].c_str());
333  SC_hitlimit = atoi(tableMat[1][colM["SC_HITLIMIT"]].c_str());
334  S_hitlimit = atoi(tableMat[1][colM["SO_HITLIMIT"]].c_str());
335  N_testreg = atoi(tableMat[1][colM["NO_TESTREG"]].c_str());
336  NC_testreg = atoi(tableMat[1][colM["NC_TESTREG"]].c_str());
337  SC_testreg = atoi(tableMat[1][colM["SC_TESTREG"]].c_str());
338  S_testreg = atoi(tableMat[1][colM["SO_TESTREG"]].c_str());
339  BusyHoldMin = atoi(tableMat[1][colM["BUSYHOLDMIN"]].c_str());
340  BusyWhenBehind = atoi(tableMat[1][colM["BUSYWHENBEHIND"]].c_str());
341  FeatureRegister = atoi(tableMat[1][colM["FEATUREREGISTER"]].c_str());
342  FIFO2Limit = atoi(tableMat[1][colM["FIFO2LIMIT"]].c_str());
343  LastDacOff = atoi(tableMat[1][colM["LASTDACOFF"]].c_str());
344  SimHitsPerRoc = atoi(tableMat[1][colM["SIMHITSPERROC"]].c_str());
345  TimeoutOROOSLimit = atoi(tableMat[1][colM["TIMEOUTOROOSLIMIT"]].c_str());
346  TriggerHoldoff = atoi(tableMat[1][colM["TRIGGERHOLDOFF"]].c_str());
347 
348  SPARE1 = atoi(tableMat[1][colM["SPARE1"]].c_str());
349  SPARE2 = atoi(tableMat[1][colM["SPARE2"]].c_str());
350  SPARE3 = atoi(tableMat[1][colM["SPARE3"]].c_str());
351  SPARE4 = atoi(tableMat[1][colM["SPARE4"]].c_str());
352  SPARE5 = atoi(tableMat[1][colM["SPARE5"]].c_str());
353  SPARE6 = atoi(tableMat[1][colM["SPARE6"]].c_str());
354  SPARE7 = atoi(tableMat[1][colM["SPARE7"]].c_str());
355  SPARE8 = atoi(tableMat[1][colM["SPARE8"]].c_str());
356  SPARE9 = atoi(tableMat[1][colM["SPARE9"]].c_str());
357  SPARE10 = atoi(tableMat[1][colM["SPARE10"]].c_str());
358 
359  } // end of 'first' condition
360  [[clang::suppress]]
361  for (int r = 1; r < size[0]; r++) //Goes to every row of the FIRST Matrix (MUST BE 36, one for each FED channel)
362  {
363  //Number of ROCS per FED channel
364  NRocs[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["NUM_ROCS"]].c_str());
365  //input offset dac (one for each channel)
366  offs_dac[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["CHAN_OFFST_DAC"]].c_str());
367  //Channel delays, one for each channel, 0=15
368  DelayCh[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["CHAN_DELAY"]].c_str());
369  //Blacks and Ultra-blacks, 3 limit per channel
370  BlackHi[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["CHAN_BHIGH"]].c_str());
371  BlackLo[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["CHAN_BLOW"]].c_str());
372  Ublack[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["CHAN_UB"]].c_str());
373  }
374 
375  [[clang::suppress]] readDBTBMLevels(tableMat, size[0] + 1, size[1]);
376  [[clang::suppress]] readDBROCLevels(tableMat, size[1] + 1, size[2]);
377  Ccntrl_original = Ccntrl;
378  modeRegister_original = modeRegister;
379 
380  Ncntrl_original = Ncntrl;
381  NCcntrl_original = NCcntrl;
382  SCcntrl_original = SCcntrl;
383  Scntrl_original = Scntrl;
384 
385  Nbaseln_original = Nbaseln;
386  NCbaseln_original = NCbaseln;
387  SCbaseln_original = SCbaseln;
388  Sbaseln_original = Sbaseln;
389 
390  // Modified by MR on 17-11-2008
391  // This new variable has to be read from DB!!!!!
392  // We need to add a column in the DB. Talk to Umesh.
393  FineDes1Del = 14;
394 }
395 
396 void PixelFEDCard::readDBTBMLevels(std::vector<std::vector<std::string> > &tableMat, int firstRow, int lastRow) {
397  string mthn = "[PixelFEDCard::readDBTBMLevels()] ";
398  vector<string> ins = tableMat[firstRow];
399  map<string, int> colM;
400  vector<string> colNames;
401 
430  colNames.push_back("CONFIG_KEY");
431  colNames.push_back("KEY_TYPE");
432  colNames.push_back("KEY_ALIAS");
433  colNames.push_back("VERSION");
434  colNames.push_back("KIND_OF_COND");
435  colNames.push_back("TBM_NAME");
436  colNames.push_back("PIXEL_FED");
437  colNames.push_back("FED_CHAN");
438  colNames.push_back("TBMA_HEAD_L0");
439  colNames.push_back("TBMA_HEAD_L1");
440  colNames.push_back("TBMA_HEAD_L2");
441  colNames.push_back("TBMA_HEAD_L3");
442  colNames.push_back("TBMA_HEAD_L4");
443  colNames.push_back("TBMA_TRAIL_L0");
444  colNames.push_back("TBMA_TRAIL_L1");
445  colNames.push_back("TBMA_TRAIL_L2");
446  colNames.push_back("TBMA_TRAIL_L3");
447  colNames.push_back("TBMA_TRAIL_L4");
448  colNames.push_back("TBMA_HEAD_B");
449  colNames.push_back("TBMA_HEAD_UB");
450  colNames.push_back("TBMA_TRAIL_B");
451  colNames.push_back("TBMA_TRAIL_UB");
452  /*
453  colNames.push_back("CONFIG_KEY_ID" );
454  colNames.push_back("CONFIG_KEY" );
455  colNames.push_back("VERSION" );
456  colNames.push_back("CONDITION_DATA_SET_ID" );
457  colNames.push_back("KIND_OF_CONDITION_ID" );
458  colNames.push_back("KIND_OF_COND" );
459  colNames.push_back("PXLFED_NAME" );
460  colNames.push_back("FED_CHAN" );
461  colNames.push_back("TBM_PART_ID" );
462  colNames.push_back("TBM_SER_NUM" );
463  colNames.push_back("PANEL_NAME" );
464  colNames.push_back("HUB_ADDRS" );
465  colNames.push_back("TBMA_HEAD_L0" );
466  colNames.push_back("TBMA_HEAD_L1" );
467  colNames.push_back("TBMA_HEAD_L2" );
468  colNames.push_back("TBMA_HEAD_L3" );
469  colNames.push_back("TBMA_HEAD_L4" );
470  colNames.push_back("TBMA_TRAIL_L0" );
471  colNames.push_back("TBMA_TRAIL_L1" );
472  colNames.push_back("TBMA_TRAIL_L2" );
473  colNames.push_back("TBMA_TRAIL_L3" );
474  colNames.push_back("TBMA_TRAIL_L4" );
475 */
476  // Retrieve header row and cross check that everyfield is there.
477  for (unsigned int c = 0; c < ins.size(); c++) {
478  for (unsigned int n = 0; n < colNames.size(); n++) {
479  if (tableMat[firstRow][c] == colNames[n]) {
480  colM[colNames[n]] = c;
481  break;
482  }
483  }
484  } //end for
485  for (unsigned int n = 0; n < colNames.size(); n++) {
486  if (colM.find(colNames[n]) == colM.end()) {
487  std::cerr << mthn << "\tCouldn't find in the database the column with name " << colNames[n] << std::endl;
488  assert(0);
489  }
490  }
491  for (int r = firstRow + 1; r < lastRow; r++) //Goes to every row of the Matrix (MUST BE 36, one for each FED channel)
492  {
493  //Signal levels for the TBM, one per channel
494  TBM_L0[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_HEAD_L0"]].c_str());
495  TBM_L1[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_HEAD_L1"]].c_str());
496  TBM_L2[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_HEAD_L2"]].c_str());
497  TBM_L3[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_HEAD_L3"]].c_str());
498  TBM_L4[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_HEAD_L4"]].c_str());
499  TRL_L0[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_TRAIL_L0"]].c_str());
500  TRL_L1[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_TRAIL_L1"]].c_str());
501  TRL_L2[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_TRAIL_L2"]].c_str());
502  TRL_L3[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_TRAIL_L3"]].c_str());
503  TRL_L4[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_TRAIL_L4"]].c_str());
504  }
505 }
506 
507 void PixelFEDCard::readDBROCLevels(std::vector<std::vector<std::string> > &tableMat, int firstRow, int lastRow) {
508  string mthn = "[PixelFEDCard::readDBROCLevels()] ";
509  map<string, int> colM;
510  vector<string> colNames;
511 
534  colNames.push_back("CONFIG_KEY");
535  colNames.push_back("KEY_TYPE");
536  colNames.push_back("KEY_ALIAS");
537  colNames.push_back("VERSION");
538  colNames.push_back("KIND_OF_COND");
539  colNames.push_back("ROC_NAME");
540  colNames.push_back("FED_ROC_NUM");
541  colNames.push_back("PIXEL_FED");
542  colNames.push_back("FED_CHAN");
543  colNames.push_back("ROC_L0");
544  colNames.push_back("ROC_L1");
545  colNames.push_back("ROC_L2");
546  colNames.push_back("ROC_L3");
547  colNames.push_back("ROC_L4");
548  colNames.push_back("ROC_B");
549  colNames.push_back("ROC_UB");
550  /*
551  colNames.push_back("CONFIG_KEY_ID" );
552  colNames.push_back("CONFIG_KEY" );
553  colNames.push_back("VERSION" );
554  colNames.push_back("KIND_OF_COND" );
555  colNames.push_back("PXLFED_NAME" );
556  colNames.push_back("FED_CHAN" );
557  colNames.push_back("AOH_CHAN" );
558  colNames.push_back("ROC_NAME" );
559  colNames.push_back("HUB_ADDRS" );
560  colNames.push_back("PORT_NUMBER" );
561  colNames.push_back("ROC_I2C_ADDR" );
562  colNames.push_back("GEOM_ROC_NUM" );
563  colNames.push_back("FED_ROC_NUM" );
564  colNames.push_back("ROC_L0" );
565  colNames.push_back("ROC_L1" );
566  colNames.push_back("ROC_L2" );
567  colNames.push_back("ROC_L3" );
568  colNames.push_back("ROC_L4" );
569 */
570  // Retrieve header row and cross check that everyfield is there.
571  for (unsigned int c = 0; c < tableMat[firstRow].size(); c++) {
572  for (unsigned int n = 0; n < colNames.size(); n++) {
573  if (tableMat[firstRow][c] == colNames[n]) {
574  colM[colNames[n]] = c;
575  break;
576  }
577  }
578  } //end for
579  for (unsigned int n = 0; n < colNames.size(); n++) {
580  if (colM.find(colNames[n]) == colM.end()) {
581  std::cerr << mthn << "\tCouldn't find in the database the column with name " << colNames[n] << std::endl;
582  assert(0);
583  }
584  }
585  // Address levels 1 per channel (36) per roc(max=26)
586  // int ROC_L0[36][26],ROC_L1[36][26],ROC_L2[36][26],ROC_L3[36][26],ROC_L4[36][26];
587 
588  for (int r = firstRow + 1; r < lastRow; r++) //Goes to every row of the Matrix (MUST BE 36, one for each FED channel)
589  {
590  ROC_L0[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] =
591  atoi(tableMat[r][colM["ROC_L0"]].c_str());
592  ROC_L1[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] =
593  atoi(tableMat[r][colM["ROC_L1"]].c_str());
594  ROC_L2[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] =
595  atoi(tableMat[r][colM["ROC_L2"]].c_str());
596  ROC_L3[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] =
597  atoi(tableMat[r][colM["ROC_L3"]].c_str());
598  ROC_L4[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] =
599  atoi(tableMat[r][colM["ROC_L4"]].c_str());
600  }
601 }
602 
603 // Read the configuration parameters from file
604 PixelFEDCard::PixelFEDCard(string fileName) : PixelConfigBase(" ", " ", " ") {
605  std::string mthn = "]\t[PixelFEDCard::PixelFEDCard()]\t\t\t\t ";
606  //const bool localDEBUG = true;
607  const bool localDEBUG = false;
608 
609  // Added by Dario (March 26th, 2008): insure variables are all cleared before read-in
610  clear();
611 
612  // cout << __LINE__ << "]\t" << mthn <<" Get setup parameters from file "<<fileName<<endl;
613  FILE *infile = fopen((fileName.c_str()), "r");
614  if (infile == nullptr)
615  throw std::runtime_error("Failed to open FED Card parameter file: " + fileName);
616 
617  //Fed Base Address
618  fscanf(infile, "FED Base address :%lx\n", &FEDBASE_0);
619  fscanf(infile, "FEDID Number :%lx\n", &fedNumber);
620 
621  // if(localDEBUG) cout << __LINE__ << mthn << "FED Base address, FED # : " << std::hex << FEDBASE_0 << std::dec << std::endl ;
622  // if(localDEBUG) printf("FED Base address, FED # :%lx\n",FEDBASE_0);
623  //if(FEDBASE != FEDBASE_0) cout<< __LINE__ << "]\t" << mthn << " Inconsistent FED base address?"<<endl;
624  // if(localDEBUG) cout << __LINE__ << mthn << "FEDID # : " << std::hex << fedNumber << std::dec << std::endl ;
625  // if(localDEBUG) printf("FEDID # :%lx\n",fedNumber);
626 
627  // Number of ROCs
628  int ijx = 0;
629  for (int i = 0; i < 36; i++) {
630  ijx = i + 1;
631  fscanf(infile, "Number of ROCs Chnl %d:%d \n", &ijx, &NRocs[i]);
632  if (localDEBUG)
633  printf("Number of ROCs per Chnl %d:%d \n", ijx, NRocs[i]);
634  }
635 
636  //Settable optical input parameters
637  fscanf(infile, "Optical reciever 1 Capacitor Adjust(0-3):%d\n", &opt_cap[0]);
638  fscanf(infile, "Optical reciever 2 Capacitor Adjust(0-3):%d\n", &opt_cap[1]);
639  fscanf(infile, "Optical reciever 3 Capacitor Adjust(0-3):%d\n", &opt_cap[2]);
640  fscanf(infile, "Optical reciever 1 Input Offset (0-15) :%d\n", &opt_inadj[0]);
641  fscanf(infile, "Optical reciever 2 Input Offset (0-15) :%d\n", &opt_inadj[1]);
642  fscanf(infile, "Optical reciever 3 Input Offset (0-15) :%d\n", &opt_inadj[2]);
643  fscanf(infile, "Optical reciever 1 Output Offset (0-3) :%d\n", &opt_ouadj[0]);
644  fscanf(infile, "Optical reciever 2 Output Offset (0-3) :%d\n", &opt_ouadj[1]);
645  fscanf(infile, "Optical reciever 3 Output Offset (0-3) :%d\n", &opt_ouadj[2]);
646 
647  if (localDEBUG) {
648  printf("Optical reciever 1 Capacitor Adjust(0-3):%d\n", opt_cap[0]);
649  printf("Optical reciever 2 Capacitor Adjust(0-3):%d\n", opt_cap[1]);
650  printf("Optical reciever 3 Capacitor Adjust(0-3):%d\n", opt_cap[2]);
651  printf("Optical reciever 1 Input Offset (0-15) :%d\n", opt_inadj[0]);
652  printf("Optical reciever 2 Input Offset (0-15) :%d\n", opt_inadj[1]);
653  printf("Optical reciever 3 Input Offset (0-15) :%d\n", opt_inadj[2]);
654  printf("Optical reciever 1 Output Offset (0-3) :%d\n", opt_ouadj[0]);
655  printf("Optical reciever 2 Output Offset (0-3) :%d\n", opt_ouadj[1]);
656  printf("Optical reciever 3 Output Offset (0-3) :%d\n", opt_ouadj[2]);
657  }
658 
659  //input offset dac
660  for (int i = 0; i < 36; i++) {
661  fscanf(infile, "Offset DAC channel %d:%d\n", &ijx, &offs_dac[i]);
662  if (localDEBUG)
663  printf("Offset DAC channel %d:%d\n", i + 1, offs_dac[i]);
664  }
665 
666  //clock phases
667  fscanf(infile, "Clock Phase Bits ch 1-9:%x\n", &clkphs1_9);
668  fscanf(infile, "Clock Phase Bits ch 10-18:%x\n", &clkphs10_18);
669  fscanf(infile, "Clock Phase Bits ch 19-27:%x\n", &clkphs19_27);
670  fscanf(infile, "Clock Phase Bits ch 28-36:%x\n", &clkphs28_36);
671  if (localDEBUG)
672  printf("Clock Phase Bits ch 1-9:%x\n", clkphs1_9);
673  if (localDEBUG)
674  printf("Clock Phase Bits ch 10-18:%x\n", clkphs10_18);
675  if (localDEBUG)
676  printf("Clock Phase Bits ch 19-27:%x\n", clkphs19_27);
677  if (localDEBUG)
678  printf("Clock Phase Bits ch 28-36:%x\n", clkphs28_36);
679 
680  //Blacks
681  for (int i = 0; i < 36; i++) {
682  fscanf(infile, "Black HiThold ch %d:%d \n", &ijx, &BlackHi[i]);
683  fscanf(infile, "Black LoThold ch %d:%d \n", &ijx, &BlackLo[i]);
684  fscanf(infile, "ULblack Thold ch %d:%d \n", &ijx, &Ublack[i]);
685  if (localDEBUG)
686  printf("Black HiThold ch %d:%d\n", ijx, BlackHi[i]);
687  if (localDEBUG)
688  printf("Black LoThold ch %d:%d\n", ijx, BlackLo[i]);
689  if (localDEBUG)
690  printf("ULblack Thold ch %d:%d\n", ijx, Ublack[i]);
691  }
692 
693  //Channel delays
694  for (int i = 0; i < 36; i++) {
695  fscanf(infile, "Delay channel %d(0-15):%d\n", &ijx, &DelayCh[i]);
696  if (localDEBUG)
697  printf("Delay channel %d(0-15):%d\n", i + 1, DelayCh[i]);
698  }
699 
700  //Signal levels
701  for (int i = 0; i < 36; i++) {
702  fscanf(infile, "TBM level 0 Channel %d:%d\n", &ijx, &TBM_L0[i]);
703  fscanf(infile, "TBM level 1 Channel %d:%d\n", &ijx, &TBM_L1[i]);
704  fscanf(infile, "TBM level 2 Channel %d:%d\n", &ijx, &TBM_L2[i]);
705  fscanf(infile, "TBM level 3 Channel %d:%d\n", &ijx, &TBM_L3[i]);
706  fscanf(infile, "TBM level 4 Channel %d:%d\n", &ijx, &TBM_L4[i]);
707  if (localDEBUG)
708  printf("TBM level 0 Channel %d:%d\n", ijx, TBM_L0[i]);
709  if (localDEBUG)
710  printf("TBM level 1 Channel %d:%d\n", ijx, TBM_L1[i]);
711  if (localDEBUG)
712  printf("TBM level 2 Channel %d:%d\n", ijx, TBM_L2[i]);
713  if (localDEBUG)
714  printf("TBM level 3 Channel %d:%d\n", ijx, TBM_L3[i]);
715  if (localDEBUG)
716  printf("TBM level 4 Channel %d:%d\n", ijx, TBM_L4[i]);
717 
718  int ijy = 0;
719  for (int j = 0; j < NRocs[i]; j++) {
720  fscanf(infile, "ROC%d level 0 Channel %d :%d\n", &ijy, &ijx, &ROC_L0[i][j]);
721  fscanf(infile, "ROC%d level 1 Channel %d :%d\n", &ijy, &ijx, &ROC_L1[i][j]);
722  fscanf(infile, "ROC%d level 2 Channel %d :%d\n", &ijy, &ijx, &ROC_L2[i][j]);
723  fscanf(infile, "ROC%d level 3 Channel %d :%d\n", &ijy, &ijx, &ROC_L3[i][j]);
724  fscanf(infile, "ROC%d level 4 Channel %d :%d\n", &ijy, &ijx, &ROC_L4[i][j]);
725  if (localDEBUG)
726  printf("ROC%d level 0 Channel %d :%d\n", ijy, ijx, ROC_L0[i][j]);
727  if (localDEBUG)
728  printf("ROC%d level 1 Channel %d :%d\n", ijy, ijx, ROC_L1[i][j]);
729  if (localDEBUG)
730  printf("ROC%d level 2 Channel %d :%d\n", ijy, ijx, ROC_L2[i][j]);
731  if (localDEBUG)
732  printf("ROC%d level 3 Channel %d :%d\n", ijy, ijx, ROC_L3[i][j]);
733  if (localDEBUG)
734  printf("ROC%d level 4 Channel %d :%d\n", ijy, ijx, ROC_L4[i][j]);
735  }
736 
737  fscanf(infile, "TRLR level 0 Channel %d:%d\n", &ijx, &TRL_L0[i]);
738  fscanf(infile, "TRLR level 1 Channel %d:%d\n", &ijx, &TRL_L1[i]);
739  fscanf(infile, "TRLR level 2 Channel %d:%d\n", &ijx, &TRL_L2[i]);
740  fscanf(infile, "TRLR level 3 Channel %d:%d\n", &ijx, &TRL_L3[i]);
741  fscanf(infile, "TRLR level 4 Channel %d:%d\n", &ijx, &TRL_L4[i]);
742  if (localDEBUG)
743  printf("TRLR level 0 Channel %d:%d\n", ijx, TRL_L0[i]);
744  if (localDEBUG)
745  printf("TRLR level 1 Channel %d:%d\n", ijx, TRL_L1[i]);
746  if (localDEBUG)
747  printf("TRLR level 2 Channel %d:%d\n", ijx, TRL_L2[i]);
748  if (localDEBUG)
749  printf("TRLR level 3 Channel %d:%d\n", ijx, TRL_L3[i]);
750  if (localDEBUG)
751  printf("TRLR level 4 Channel %d:%d\n", ijx, TRL_L4[i]);
752  }
753 
754  //These bits turn off(1) and on(0) channels
755  fscanf(infile, "Channel Enbable bits chnls 1-9 (on = 0):%x\n", &Ncntrl);
756  fscanf(infile, "Channel Enbable bits chnls 10-18(on = 0):%x\n", &NCcntrl);
757  fscanf(infile, "Channel Enbable bits chnls 19-27(on = 0):%x\n", &SCcntrl);
758  fscanf(infile, "Channel Enbable bits chnls 28-36(on = 0):%x\n", &Scntrl);
759  if (localDEBUG)
760  printf("Channel Enbable bits chnls 1-9 (on = 0):%x\n", Ncntrl);
761  if (localDEBUG)
762  printf("Channel Enbable bits chnls 10-18(on = 0):%x\n", NCcntrl);
763  if (localDEBUG)
764  printf("Channel Enbable bits chnls 19-27(on = 0):%x\n", SCcntrl);
765  if (localDEBUG)
766  printf("Channel Enbable bits chnls 28-36(on = 0):%x\n", Scntrl);
767 
768  //These are delays to the TTCrx
769  fscanf(infile, "TTCrx Coarse Delay Register 2:%d\n", &CoarseDel);
770  fscanf(infile, "TTCrc ClkDes2 Register 3:%x\n", &ClkDes2);
771  fscanf(infile, "TTCrc Fine Dlay ClkDes2 Reg 1:%d\n", &FineDes2Del);
772  if (localDEBUG)
773  printf("TTCrx Coarse Delay Register 2:%d\n", CoarseDel);
774  if (localDEBUG)
775  printf("TTCrc ClkDes2 Register 3:%x\n", ClkDes2);
776  if (localDEBUG)
777  printf("TTCrc Fine Dlay ClkDes2 Reg 1:%d\n", FineDes2Del);
778 
779  // Control register
780  fscanf(infile, "Center Chip Control Reg:%x\n", &Ccntrl);
781  if (localDEBUG)
782  printf("Control Reg:0x%x\n", Ccntrl);
783  fscanf(infile, "Initial Slink DAQ mode:%d\n", &modeRegister);
784  if (localDEBUG)
785  printf("Mode Reg:%d\n", modeRegister);
786 
787  //These bits set ADC Gain/Range 1Vpp(0) and 2Vpp(1) for channels
788  fscanf(infile, "Channel ADC Gain bits chnls 1-12(1Vpp = 0):%x\n", &Nadcg);
789  fscanf(infile, "Channel ADC Gain bits chnls 13-20(1Vpp = 0):%x\n", &NCadcg);
790  fscanf(infile, "Channel ADC Gain bits chnls 21-28(1Vpp = 0):%x\n", &SCadcg);
791  fscanf(infile, "Channel ADC Gain bits chnls 29-36(1Vpp = 0):%x\n", &Sadcg);
792  if (localDEBUG)
793  printf("Channel ADC Gain bits chnls 1-12(1Vpp = 0):%x\n", Nadcg);
794  if (localDEBUG)
795  printf("Channel ADC Gain bits chnls 13-20(1Vpp = 0):%x\n", NCadcg);
796  if (localDEBUG)
797  printf("Channel ADC Gain bits chnls 21-28(1Vpp = 0):%x\n", SCadcg);
798  if (localDEBUG)
799  printf("Channel ADC Gain bits chnls 29-36(1Vpp = 0):%x\n", Sadcg);
800 
801  //These bits set Baseline adjustment value (common by FPGA)//can turn on by channel
802  fscanf(infile, "Channel Baseline Enbable chnls 1-9 (on = (0x1ff<<16)+):%x\n", &Nbaseln);
803  fscanf(infile, "Channel Baseline Enbable chnls 10-18(on = (0x1ff<<16)+):%x\n", &NCbaseln);
804  fscanf(infile, "Channel Baseline Enbable chnls 19-27(on = (0x1ff<<16)+):%x\n", &SCbaseln);
805  fscanf(infile, "Channel Baseline Enbable chnls 28-36(on = (0x1ff<<16)+):%x\n", &Sbaseln);
806  if (localDEBUG)
807  printf("Channel Baseline Enbable chnls 1-9 (on = (0x1ff<<16)+):%x\n", Nbaseln);
808  if (localDEBUG)
809  printf("Channel Baseline Enbable chnls 10-18(on = (0x1ff<<16)+):%x\n", NCbaseln);
810  if (localDEBUG)
811  printf("Channel Baseline Enbable chnls 19-27(on = (0x1ff<<16)+):%x\n", SCbaseln);
812  if (localDEBUG)
813  printf("Channel Baseline Enbable chnls 28-36(on = (0x1ff<<16)+):%x\n", Sbaseln);
814 
815  //These bits set TBM trailer mask (common by FPGA)
816  fscanf(infile, "TBM trailer mask chnls 1-9 (0xff = all masked):%x\n", &N_TBMmask);
817  fscanf(infile, "TBM trailer mask chnls 10-18(0xff = all masked):%x\n", &NC_TBMmask);
818  fscanf(infile, "TBM trailer mask chnls 19-27(0xff = all masked):%x\n", &SC_TBMmask);
819  fscanf(infile, "TBM trailer mask chnls 28-36(0xff = all masked):%x\n", &S_TBMmask);
820  if (localDEBUG)
821  printf("TBM trailer mask chnls 1-9 (0xff = all masked):%x\n", N_TBMmask);
822  if (localDEBUG)
823  printf("TBM trailer mask chnls 10-18(0xff = all masked):%x\n", NC_TBMmask);
824  if (localDEBUG)
825  printf("TBM trailer mask chnls 19-27(0xff = all masked):%x\n", SC_TBMmask);
826  if (localDEBUG)
827  printf("TBM trailer mask chnls 28-36(0xff = all masked):%x\n", S_TBMmask);
828 
829  //These bits set the Private fill/gap word value (common by FPGA)
830  fscanf(infile, "Private 8 bit word chnls 1-9 :%x\n", &N_Pword);
831  fscanf(infile, "Private 8 bit word chnls 10-18:%x\n", &NC_Pword);
832  fscanf(infile, "Private 8 bit word chnls 19-27:%x\n", &SC_Pword);
833  fscanf(infile, "Private 8 bit word chnls 28-36:%x\n", &S_Pword);
834  if (localDEBUG)
835  printf("Private 8 bit word chnls 1-9 :%x\n", N_Pword);
836  if (localDEBUG)
837  printf("Private 8 bit word chnls 10-18:%x\n", NC_Pword);
838  if (localDEBUG)
839  printf("Private 8 bit word chnls 19-27:%x\n", SC_Pword);
840  if (localDEBUG)
841  printf("Private 8 bit word chnls 28-36:%x\n", S_Pword);
842 
843  //These bit sets the special dac mode for random triggers
844  fscanf(infile, "Special Random testDAC mode (on = 0x1, off=0x0):%x\n", &SpecialDac);
845  if (localDEBUG)
846  printf("Special Random testDAC mode (on = 0x1, off=0x0):%x\n", SpecialDac);
847 
848  //These bits set the number of Out of consecutive out of sync events until a TTs OOs
849  fscanf(infile, "Number of Consecutive (max 1023) Out of Syncs till TTs OOS set:%d\n", &Ooslvl);
850  if (localDEBUG)
851  printf("Number of Consecutive (max 1023) Out of Syncs till TTs OOS set:%d\n", Ooslvl);
852 
853  //These bits set the number of Empty events until a TTs Error
854  fscanf(infile, "Number of Consecutive (max 1023) Empty events till TTs ERR set:%d\n", &Errlvl);
855  if (localDEBUG)
856  printf("Number of Consecutive (max 1023) Empty events till TTs ERR set:%d\n", Errlvl);
857 
858  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 N
859  fscanf(infile, "N Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", &Nfifo1Bzlvl);
860  if (localDEBUG)
861  printf("N Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", Nfifo1Bzlvl);
862 
863  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 NC
864  fscanf(infile, "NC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", &NCfifo1Bzlvl);
865  if (localDEBUG)
866  printf("NC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", NCfifo1Bzlvl);
867 
868  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 SC
869  fscanf(infile, "SC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", &SCfifo1Bzlvl);
870  if (localDEBUG)
871  printf("SC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", SCfifo1Bzlvl);
872 
873  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 S
874  fscanf(infile, "S Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", &Sfifo1Bzlvl);
875  if (localDEBUG)
876  printf("S Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", Sfifo1Bzlvl);
877 
878  //These bits set the Almost Full level in fifo-3, Almost full = TTs WARN in fifo-3
879  fscanf(infile, "Fifo-3 almost full level,sets TTs WARN (max 8191):%d\n", &fifo3Wrnlvl);
880  if (localDEBUG)
881  printf("Fifo-3 almost full level,sets TTs WARN (max 8191):%d\n", fifo3Wrnlvl);
882 
883  fscanf(infile, "FED Master delay 0=0,1=32,2=48,3=64:%d\n", &FedTTCDelay);
884  if (localDEBUG)
885  printf("FED Master delay 0=0,1=32,2=48,3=64:%d\n", FedTTCDelay);
886 
887  fscanf(infile, "TTCrx Register 0 fine delay ClkDes1:%d\n", &FineDes1Del);
888  if (localDEBUG)
889  printf("TTCrx Register 0 fine delay ClkDes1:%d\n", FineDes1Del);
890 
891  int checkword = 0;
892  fscanf(infile, "Params FED file check word:%d\n", &checkword);
893  if (checkword != 90508 && checkword != 91509 && checkword != 20211)
894  cout << __LINE__ << "]\t" << mthn << "FEDID: " << fedNumber << " Params FED File read error. Checkword read "
895  << checkword << " check word expected 090508 or 91509 or 20211" << endl;
896  assert((checkword == 90508) | (checkword == 91509) | (checkword == 20211));
897 
898  if (localDEBUG)
899  cout << __LINE__ << "]\t" << mthn << "Params FED file check word: " << checkword << endl;
900 
901  //These bits set the hit limit in fifo-1 for an event
902 
903  if (checkword == 20211) {
904  //These bits set the hit limit in fifo-1 for an event
905  fscanf(infile, "N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &N_hitlimit);
906  if (localDEBUG)
907  printf("N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", N_hitlimit);
908  fscanf(infile, "NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &NC_hitlimit);
909  if (localDEBUG)
910  printf("NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", NC_hitlimit);
911  fscanf(infile, "SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &SC_hitlimit);
912  if (localDEBUG)
913  printf("SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", SC_hitlimit);
914  fscanf(infile, "S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &S_hitlimit);
915  if (localDEBUG)
916  printf("S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", S_hitlimit);
917  //These bits allow a ROC to be skipped (1/fpga)
918 
919  fscanf(infile, "Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &N_testreg);
920  if (localDEBUG)
921  printf("Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", N_testreg);
922  fscanf(infile, "Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &NC_testreg);
923  if (localDEBUG)
924  printf("Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", NC_testreg);
925  fscanf(infile, "Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &SC_testreg);
926  if (localDEBUG)
927  printf("Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", SC_testreg);
928  fscanf(infile, "Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &S_testreg);
929  if (localDEBUG)
930  printf("Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", S_testreg);
931 
932  fscanf(infile, "Set BUSYWHENBEHIND by this many triggers with timeouts:%d\n", &BusyWhenBehind);
933  if (localDEBUG)
934  printf("Set BUSYWHENBEHIND by this many triggers with timeouts:%d\n", BusyWhenBehind);
935 
936  fscanf(infile, "D[0]=1 enable fed-stuck reset D[1]=1 disable ev# protect(dont):%x\n", &FeatureRegister);
937  if (localDEBUG)
938  printf("D[0]=1 enable fed-stuck reset D[1]=1 disable ev# protect(dont):%x\n", FeatureRegister);
939 
940  fscanf(infile, "Limit for fifo-2 almost full (point for the TTS flag):%x\n", &FIFO2Limit);
941  if (localDEBUG)
942  printf("Limit for fifo-2 almost full (point for the TTS flag):%x\n", FIFO2Limit);
943 
944  fscanf(infile, "Limit for consecutive timeout OR OOSs:%d\n", &TimeoutOROOSLimit);
945  if (localDEBUG)
946  printf("Limit for consecutive timeout OR OOSs:%d\n", TimeoutOROOSLimit);
947 
948  fscanf(infile, "Turn off filling of lastdac fifos(exc 1st ROC):%d\n", &LastDacOff);
949  if (localDEBUG)
950  printf("Turn off filling of lastdac fifos(exc 1st ROC):%d\n", LastDacOff);
951 
952  fscanf(infile, "Number of simulated hits per ROC for internal generator:%d\n", &SimHitsPerRoc);
953  if (localDEBUG)
954  printf("Number of simulated hits per ROC for internal generator:%d\n", SimHitsPerRoc);
955 
956  fscanf(infile, "Miniumum hold time for busy (changing definition):%d\n", &BusyHoldMin);
957  if (localDEBUG)
958  printf("Miniumum hold time for busy (changing definition):%d\n", BusyHoldMin);
959 
960  fscanf(infile, "Trigger Holdoff in units of 25us(0=none):%d\n", &TriggerHoldoff);
961  if (localDEBUG)
962  printf("Trigger Holdoff in units of 25us(0=none):%d\n", TriggerHoldoff);
963 
964  fscanf(infile, "Spare fedcard input 1:%d\n", &SPARE1);
965  if (localDEBUG)
966  printf("Spare fedcard input 1:%d\n", SPARE1);
967  fscanf(infile, "Spare fedcard input 2:%d\n", &SPARE2);
968  if (localDEBUG)
969  printf("Spare fedcard input 2:%d\n", SPARE2);
970  fscanf(infile, "Spare fedcard input 3:%d\n", &SPARE3);
971  if (localDEBUG)
972  printf("Spare fedcard input 3:%d\n", SPARE3);
973  fscanf(infile, "Spare fedcard input 4:%d\n", &SPARE4);
974  if (localDEBUG)
975  printf("Spare fedcard input 4:%d\n", SPARE4);
976  fscanf(infile, "Spare fedcard input 5:%d\n", &SPARE5);
977  if (localDEBUG)
978  printf("Spare fedcard input 5:%d\n", SPARE5);
979  fscanf(infile, "Spare fedcard input 6:%d\n", &SPARE6);
980  if (localDEBUG)
981  printf("Spare fedcard input 6:%d\n", SPARE6);
982  fscanf(infile, "Spare fedcard input 7:%d\n", &SPARE7);
983  if (localDEBUG)
984  printf("Spare fedcard input 7:%d\n", SPARE7);
985  fscanf(infile, "Spare fedcard input 8:%d\n", &SPARE8);
986  if (localDEBUG)
987  printf("Spare fedcard input 8:%d\n", SPARE8);
988  fscanf(infile, "Spare fedcard input 9:%d\n", &SPARE9);
989  if (localDEBUG)
990  printf("Spare fedcard input 9:%d\n", SPARE9);
991  fscanf(infile, "Spare fedcard input 10:%d\n", &SPARE10);
992  if (localDEBUG)
993  printf("Spare fedcard input 10:%d\n", SPARE10);
994 
995  } else if (checkword == 91509) {
996  //These bits set the hit limit in fifo-1 for an event
997  fscanf(infile, "N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &N_hitlimit);
998  if (localDEBUG)
999  printf("N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", N_hitlimit);
1000  fscanf(infile, "NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &NC_hitlimit);
1001  if (localDEBUG)
1002  printf("NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", NC_hitlimit);
1003  fscanf(infile, "SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &SC_hitlimit);
1004  if (localDEBUG)
1005  printf("SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", SC_hitlimit);
1006  fscanf(infile, "S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &S_hitlimit);
1007  if (localDEBUG)
1008  printf("S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", S_hitlimit);
1009  //These bits allow a ROC to be skipped (1/fpga)
1010 
1011  fscanf(infile, "Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &N_testreg);
1012  if (localDEBUG)
1013  printf("Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", N_testreg);
1014  fscanf(infile, "Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &NC_testreg);
1015  if (localDEBUG)
1016  printf("Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", NC_testreg);
1017  fscanf(infile, "Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &SC_testreg);
1018  if (localDEBUG)
1019  printf("Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", SC_testreg);
1020  fscanf(infile, "Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &S_testreg);
1021  if (localDEBUG)
1022  printf("Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", S_testreg);
1023 
1024  BusyWhenBehind = 8;
1025  FeatureRegister = 0x1;
1026  FIFO2Limit = 0x1C00;
1027  TimeoutOROOSLimit = 200;
1028  LastDacOff = 0;
1029  SimHitsPerRoc = 0;
1030  BusyHoldMin = 0;
1031  TriggerHoldoff = 0;
1032  SPARE1 = 0;
1033  SPARE2 = 0;
1034  SPARE3 = 0;
1035  SPARE4 = 0;
1036  SPARE5 = 0;
1037  SPARE6 = 0;
1038  SPARE7 = 0;
1039  SPARE8 = 0;
1040  SPARE9 = 0;
1041  SPARE10 = 0;
1042 
1043  } else {
1044  N_hitlimit = 192;
1045  NC_hitlimit = 192;
1046  SC_hitlimit = 192;
1047  S_hitlimit = 192;
1048 
1049  N_testreg = 0;
1050  NC_testreg = 0;
1051  SC_testreg = 0;
1052  S_testreg = 0;
1053 
1054  BusyWhenBehind = 8;
1055  FeatureRegister = 0x1;
1056  FIFO2Limit = 0x1c00;
1057  TimeoutOROOSLimit = 200;
1058  LastDacOff = 0;
1059  SimHitsPerRoc = 0;
1060  BusyHoldMin = 0;
1061  TriggerHoldoff = 0;
1062  SPARE1 = 0;
1063  SPARE2 = 0;
1064  SPARE3 = 0;
1065  SPARE4 = 0;
1066  SPARE5 = 0;
1067  SPARE6 = 0;
1068  SPARE7 = 0;
1069  SPARE8 = 0;
1070  SPARE9 = 0;
1071  SPARE10 = 0;
1072  }
1073 
1074  fclose(infile);
1075 
1076  Ccntrl_original = Ccntrl;
1077  modeRegister_original = modeRegister;
1078 
1079  Ncntrl_original = Ncntrl;
1080  NCcntrl_original = NCcntrl;
1081  SCcntrl_original = SCcntrl;
1082  Scntrl_original = Scntrl;
1083 
1084  Nbaseln_original = Nbaseln;
1085  NCbaseln_original = NCbaseln;
1086  SCbaseln_original = SCbaseln;
1087  Sbaseln_original = Sbaseln;
1088 
1089  return;
1090 }
1091 
1092 //==================================================================================
1093 // Added by Dario (March 26th 2008)
1094 void PixelFEDCard::clear(void) {
1095  FEDBASE_0 = 0;
1096  fedNumber = 999;
1097  for (int i = 0; i < 36; i++) {
1098  NRocs[i] = 0;
1099  offs_dac[i] = 0;
1100  BlackHi[i] = 0;
1101  BlackLo[i] = 0;
1102  Ublack[i] = 0;
1103  DelayCh[i] = 0;
1104  TBM_L0[i] = 0;
1105  TBM_L1[i] = 0;
1106  TBM_L2[i] = 0;
1107  TBM_L3[i] = 0;
1108  TBM_L4[i] = 0;
1109  TRL_L0[i] = 0;
1110  TRL_L1[i] = 0;
1111  TRL_L2[i] = 0;
1112  TRL_L3[i] = 0;
1113  TRL_L4[i] = 0;
1114  }
1115  for (int i = 0; i < 3; i++) {
1116  opt_cap[i] = 0;
1117  opt_inadj[i] = 0;
1118  opt_ouadj[i] = 0;
1119  }
1120  clkphs1_9 = 0;
1121  clkphs10_18 = 0;
1122  clkphs19_27 = 0;
1123  clkphs28_36 = 0;
1124 
1125  for (int i = 0; i < 36; i++) {
1126  for (int j = 0; j < 26; j++) {
1127  ROC_L0[i][j] = 0;
1128  ROC_L1[i][j] = 0;
1129  ROC_L2[i][j] = 0;
1130  ROC_L3[i][j] = 0;
1131  ROC_L4[i][j] = 0;
1132  }
1133  }
1134  Ncntrl = 0;
1135  NCcntrl = 0;
1136  SCcntrl = 0;
1137  Scntrl = 0;
1138  CoarseDel = 0;
1139  ClkDes2 = 0;
1140  FineDes2Del = 0;
1141  FineDes1Del = 0;
1142  Ccntrl = 0;
1143  modeRegister = 0;
1144  Nadcg = 0;
1145  NCadcg = 0;
1146  SCadcg = 0;
1147  Sadcg = 0;
1148  Nbaseln = 0;
1149  NCbaseln = 0;
1150  SCbaseln = 0;
1151  Sbaseln = 0;
1152  N_TBMmask = 0;
1153  NC_TBMmask = 0;
1154  SC_TBMmask = 0;
1155  S_TBMmask = 0;
1156  N_Pword = 0;
1157  NC_Pword = 0;
1158  SC_Pword = 0;
1159  S_Pword = 0;
1160  SpecialDac = 0;
1161  Ooslvl = 0;
1162  Errlvl = 0;
1163  Nfifo1Bzlvl = 0;
1164  NCfifo1Bzlvl = 0;
1165  SCfifo1Bzlvl = 0;
1166  Sfifo1Bzlvl = 0;
1167  fifo3Wrnlvl = 0;
1168 
1169  BusyHoldMin = 0;
1170  BusyWhenBehind = 0;
1171  FeatureRegister = 0;
1172  FIFO2Limit = 0;
1173  LastDacOff = 0;
1174  SimHitsPerRoc = 0;
1175  TimeoutOROOSLimit = 0;
1176  TriggerHoldoff = 0;
1177 
1178  SPARE1 = 0;
1179  SPARE2 = 0;
1180  SPARE3 = 0;
1181  SPARE4 = 0;
1182  SPARE5 = 0;
1183  SPARE6 = 0;
1184  SPARE7 = 0;
1185  SPARE8 = 0;
1186  SPARE9 = 0;
1187  SPARE10 = 0;
1188 }
1189 //==================================================================================
1190 
1191 void PixelFEDCard::writeASCII(std::string dir) const {
1192  std::string mthn = "[PixelFEDCard::writeASCII()]\t\t\t\t ";
1193 
1194  ostringstream s1;
1195  s1 << fedNumber;
1196  std::string fedNum = s1.str();
1197 
1198  if (!dir.empty())
1199  dir += "/";
1200 
1201  std::string filename = dir + "params_fed_" + fedNum + ".dat";
1202 
1203  FILE *outfile = fopen((filename.c_str()), "w");
1204  if (outfile == nullptr) {
1205  cout << __LINE__ << "]\t" << mthn << "Could not open file: " << filename << " for writing" << endl;
1206  return;
1207  }
1208 
1209  //Fed Base Address
1210  fprintf(outfile, "FED Base address :0x%lx\n", FEDBASE_0);
1211  fprintf(outfile, "FEDID Number :0x%lx\n", fedNumber);
1212 
1213  // Number of ROCs
1214  int ijx = 0;
1215  for (int i = 0; i < 36; i++) {
1216  ijx = i + 1;
1217  fprintf(outfile, "Number of ROCs Chnl %d:%d\n", ijx, NRocs[i]);
1218  }
1219 
1220  //Settable optical input parameters
1221  fprintf(outfile, "Optical reciever 1 Capacitor Adjust(0-3):%d\n", opt_cap[0]);
1222  fprintf(outfile, "Optical reciever 2 Capacitor Adjust(0-3):%d\n", opt_cap[1]);
1223  fprintf(outfile, "Optical reciever 3 Capacitor Adjust(0-3):%d\n", opt_cap[2]);
1224  fprintf(outfile, "Optical reciever 1 Input Offset (0-15) :%d\n", opt_inadj[0]);
1225  fprintf(outfile, "Optical reciever 2 Input Offset (0-15) :%d\n", opt_inadj[1]);
1226  fprintf(outfile, "Optical reciever 3 Input Offset (0-15) :%d\n", opt_inadj[2]);
1227  fprintf(outfile, "Optical reciever 1 Output Offset (0-3) :%d\n", opt_ouadj[0]);
1228  fprintf(outfile, "Optical reciever 2 Output Offset (0-3) :%d\n", opt_ouadj[1]);
1229  fprintf(outfile, "Optical reciever 3 Output Offset (0-3) :%d\n", opt_ouadj[2]);
1230 
1231  //input offset dac
1232  for (int i = 0; i < 36; i++) {
1233  fprintf(outfile, "Offset DAC channel %d:%d\n", i + 1, offs_dac[i]);
1234  }
1235 
1236  //clock phases
1237  fprintf(outfile, "Clock Phase Bits ch 1-9:0x%x\n", clkphs1_9);
1238  fprintf(outfile, "Clock Phase Bits ch 10-18:0x%x\n", clkphs10_18);
1239  fprintf(outfile, "Clock Phase Bits ch 19-27:0x%x\n", clkphs19_27);
1240  fprintf(outfile, "Clock Phase Bits ch 28-36:0x%x\n", clkphs28_36);
1241 
1242  //Blacks
1243  for (int i = 0; i < 36; i++) {
1244  fprintf(outfile, "Black HiThold ch %d:%d \n", i + 1, BlackHi[i]);
1245  fprintf(outfile, "Black LoThold ch %d:%d \n", i + 1, BlackLo[i]);
1246  fprintf(outfile, "ULblack Thold ch %d:%d \n", i + 1, Ublack[i]);
1247  }
1248 
1249  //Channel delays
1250  for (int i = 0; i < 36; i++) {
1251  fprintf(outfile, "Delay channel %d(0-15):%d\n", i + 1, DelayCh[i]);
1252  }
1253 
1254  //Signal levels
1255  for (int i = 0; i < 36; i++) {
1256  fprintf(outfile, "TBM level 0 Channel %d:%d\n", i + 1, TBM_L0[i]);
1257  fprintf(outfile, "TBM level 1 Channel %d:%d\n", i + 1, TBM_L1[i]);
1258  fprintf(outfile, "TBM level 2 Channel %d:%d\n", i + 1, TBM_L2[i]);
1259  fprintf(outfile, "TBM level 3 Channel %d:%d\n", i + 1, TBM_L3[i]);
1260  fprintf(outfile, "TBM level 4 Channel %d:%d\n", i + 1, TBM_L4[i]);
1261 
1262  for (int j = 0; j < NRocs[i]; j++) {
1263  fprintf(outfile, "ROC%d level 0 Channel %d :%d\n", j, i + 1, ROC_L0[i][j]);
1264  fprintf(outfile, "ROC%d level 1 Channel %d :%d\n", j, i + 1, ROC_L1[i][j]);
1265  fprintf(outfile, "ROC%d level 2 Channel %d :%d\n", j, i + 1, ROC_L2[i][j]);
1266  fprintf(outfile, "ROC%d level 3 Channel %d :%d\n", j, i + 1, ROC_L3[i][j]);
1267  fprintf(outfile, "ROC%d level 4 Channel %d :%d\n", j, i + 1, ROC_L4[i][j]);
1268  }
1269 
1270  fprintf(outfile, "TRLR level 0 Channel %d:%d\n", i + 1, TRL_L0[i]);
1271  fprintf(outfile, "TRLR level 1 Channel %d:%d\n", i + 1, TRL_L1[i]);
1272  fprintf(outfile, "TRLR level 2 Channel %d:%d\n", i + 1, TRL_L2[i]);
1273  fprintf(outfile, "TRLR level 3 Channel %d:%d\n", i + 1, TRL_L3[i]);
1274  fprintf(outfile, "TRLR level 4 Channel %d:%d\n", i + 1, TRL_L4[i]);
1275  }
1276 
1277  //These bits turn off(1) and on(0) channels
1278  fprintf(outfile, "Channel Enbable bits chnls 1-9 (on = 0):0x%x\n", Ncntrl);
1279  fprintf(outfile, "Channel Enbable bits chnls 10-18(on = 0):0x%x\n", NCcntrl);
1280  fprintf(outfile, "Channel Enbable bits chnls 19-27(on = 0):0x%x\n", SCcntrl);
1281  fprintf(outfile, "Channel Enbable bits chnls 28-36(on = 0):0x%x\n", Scntrl);
1282 
1283  //These are delays to the TTCrx
1284  fprintf(outfile, "TTCrx Coarse Delay Register 2:%d\n", CoarseDel);
1285  fprintf(outfile, "TTCrc ClkDes2 Register 3:0x%x\n", ClkDes2);
1286  fprintf(outfile, "TTCrc Fine Dlay ClkDes2 Reg 1:%d\n", FineDes2Del);
1287 
1288  // Control register
1289  fprintf(outfile, "Center Chip Control Reg:0x%x\n", Ccntrl);
1290  fprintf(outfile, "Initial Slink DAQ mode:%d\n", modeRegister);
1291 
1292  //These bits set ADC Gain/Range 1Vpp(0) and 2Vpp(1) for channels
1293  fprintf(outfile, "Channel ADC Gain bits chnls 1-12(1Vpp = 0):0x%x\n", Nadcg);
1294  fprintf(outfile, "Channel ADC Gain bits chnls 13-20(1Vpp = 0):0x%x\n", NCadcg);
1295  fprintf(outfile, "Channel ADC Gain bits chnls 21-28(1Vpp = 0):0x%x\n", SCadcg);
1296  fprintf(outfile, "Channel ADC Gain bits chnls 29-36(1Vpp = 0):0x%x\n", Sadcg);
1297 
1298  //These bits set Baseline adjustment value (common by FPGA)//can turn on by channel
1299  fprintf(outfile, "Channel Baseline Enbable chnls 1-9 (on = (0x1ff<<16)+):0x%x\n", Nbaseln);
1300  fprintf(outfile, "Channel Baseline Enbable chnls 10-18(on = (0x1ff<<16)+):0x%x\n", NCbaseln);
1301  fprintf(outfile, "Channel Baseline Enbable chnls 19-27(on = (0x1ff<<16)+):0x%x\n", SCbaseln);
1302  fprintf(outfile, "Channel Baseline Enbable chnls 28-36(on = (0x1ff<<16)+):0x%x\n", Sbaseln);
1303 
1304  //These bits set TBM trailer mask (common by FPGA)
1305  fprintf(outfile, "TBM trailer mask chnls 1-9 (0xff = all masked):0x%x\n", N_TBMmask);
1306  fprintf(outfile, "TBM trailer mask chnls 10-18(0xff = all masked):0x%x\n", NC_TBMmask);
1307  fprintf(outfile, "TBM trailer mask chnls 19-27(0xff = all masked):0x%x\n", SC_TBMmask);
1308  fprintf(outfile, "TBM trailer mask chnls 28-36(0xff = all masked):0x%x\n", S_TBMmask);
1309 
1310  //These bits set the Private fill/gap word value (common by FPGA)
1311  fprintf(outfile, "Private 8 bit word chnls 1-9 :0x%x\n", N_Pword);
1312  fprintf(outfile, "Private 8 bit word chnls 10-18:0x%x\n", NC_Pword);
1313  fprintf(outfile, "Private 8 bit word chnls 19-27:0x%x\n", SC_Pword);
1314  fprintf(outfile, "Private 8 bit word chnls 28-36:0x%x\n", S_Pword);
1315 
1316  //These bit sets the special dac mode for random triggers
1317  fprintf(outfile, "Special Random testDAC mode (on = 0x1, off=0x0):0x%x\n", SpecialDac);
1318 
1319  //These bits set the number of Out of consecutive out of sync events until a TTs OOs
1320  fprintf(outfile, "Number of Consecutive (max 1023) Out of Syncs till TTs OOS set:%d\n", Ooslvl);
1321 
1322  //These bits set the number of Empty events until a TTs Error
1323  fprintf(outfile, "Number of Consecutive (max 1023) Empty events till TTs ERR set:%d\n", Errlvl);
1324 
1325  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 N
1326  fprintf(outfile, "N Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", Nfifo1Bzlvl);
1327 
1328  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 NC
1329  fprintf(outfile, "NC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", NCfifo1Bzlvl);
1330 
1331  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 SC
1332  fprintf(outfile, "SC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", SCfifo1Bzlvl);
1333 
1334  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 S
1335  fprintf(outfile, "S Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", Sfifo1Bzlvl);
1336 
1337  //These bits set the Almost Full level in fifo-3, Almost full = TTs WARN in fifo-3
1338  fprintf(outfile, "Fifo-3 almost full level,sets TTs WARN (max 8191):%d\n", fifo3Wrnlvl);
1339 
1340  fprintf(outfile, "FED Master delay 0=0,1=32,2=48,3=64:%d\n", FedTTCDelay);
1341 
1342  fprintf(outfile, "TTCrx Register 0 fine delay ClkDes1:%d\n", FineDes1Del);
1343 
1344  int checkword = 20211;
1345 
1346  fprintf(outfile, "Params FED file check word:%d\n", checkword);
1347 
1348  //These bits set the hit limit in fifo-1 for an event
1349  fprintf(outfile, "N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1350  N_hitlimit); //ch 1-9
1351 
1352  fprintf(outfile, "NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1353  NC_hitlimit); //ch 10-18
1354 
1355  fprintf(outfile, "SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1356  SC_hitlimit); //ch 19-27
1357 
1358  fprintf(outfile, "S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1359  S_hitlimit); //ch 28-36
1360 
1361  //These bits allow a ROC to be skipped (1/fpga)
1362  fprintf(outfile, "Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", N_testreg);
1363 
1364  fprintf(outfile, "Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", NC_testreg);
1365 
1366  fprintf(outfile, "Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", SC_testreg);
1367 
1368  fprintf(outfile, "Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", S_testreg);
1369 
1370  fprintf(outfile, "Set BUSYWHENBEHIND by this many triggers with timeouts:%d\n", BusyWhenBehind);
1371 
1372  fprintf(outfile, "D[0]=1 enable fed-stuck reset D[1]=1 disable ev# protect(dont):0x%x\n", FeatureRegister);
1373 
1374  fprintf(outfile, "Limit for fifo-2 almost full (point for the TTS flag):0x%x\n", FIFO2Limit);
1375 
1376  fprintf(outfile, "Limit for consecutive timeout OR OOSs:%d\n", TimeoutOROOSLimit);
1377 
1378  fprintf(outfile, "Turn off filling of lastdac fifos(exc 1st ROC):%d\n", LastDacOff);
1379 
1380  fprintf(outfile, "Number of simulated hits per ROC for internal generator:%d\n", SimHitsPerRoc);
1381 
1382  fprintf(outfile, "Miniumum hold time for busy (changing definition):%d\n", BusyHoldMin);
1383 
1384  fprintf(outfile, "Trigger Holdoff in units of 25us(0=none):%d\n", TriggerHoldoff);
1385 
1386  fprintf(outfile, "Spare fedcard input 1:%d\n", SPARE1);
1387  fprintf(outfile, "Spare fedcard input 2:%d\n", SPARE2);
1388  fprintf(outfile, "Spare fedcard input 3:%d\n", SPARE3);
1389  fprintf(outfile, "Spare fedcard input 4:%d\n", SPARE4);
1390  fprintf(outfile, "Spare fedcard input 5:%d\n", SPARE5);
1391  fprintf(outfile, "Spare fedcard input 6:%d\n", SPARE6);
1392  fprintf(outfile, "Spare fedcard input 7:%d\n", SPARE7);
1393  fprintf(outfile, "Spare fedcard input 8:%d\n", SPARE8);
1394  fprintf(outfile, "Spare fedcard input 9:%d\n", SPARE9);
1395  fprintf(outfile, "Spare fedcard input 10:%d\n", SPARE10);
1396 
1397  fclose(outfile);
1398 }
1399 
1400 //=============================================================================================
1401 void PixelFEDCard::writeXMLHeader(pos::PixelConfigKey key,
1402  int version,
1403  std::string path,
1404  std::ofstream *fedstream,
1405  std::ofstream *rocstream,
1406  std::ofstream *tbmstream) const {
1407  std::string mthn = "[PixelFEDCard::writeXMLHeader()]\t\t\t ";
1408  std::stringstream fedfullPath;
1409  std::stringstream rocfullPath;
1410  std::stringstream tbmfullPath;
1411 
1412  // modified by MR on 05-08-2008 16:50:28
1413  // FED MAIN XML FILE
1414  fedfullPath << path << "/FedConfiguration_Template_" << PixelTimeFormatter::getmSecTime() << ".xml";
1415  std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << fedfullPath.str() << "" << std::endl;
1416 
1417  fedstream->open(fedfullPath.str().c_str());
1418 
1419  *fedstream << "<?xml version='1.0' encoding='UTF-8' standalone='yes'?>" << std::endl;
1420  *fedstream << "<ROOT xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'>" << std::endl;
1421  *fedstream << "" << std::endl;
1422  *fedstream << " <HEADER>" << std::endl;
1423  *fedstream << " <HINTS mode='load-as-group' /> " << std::endl;
1424  *fedstream << " <TYPE>" << std::endl;
1425  *fedstream << " <EXTENSION_TABLE_NAME>FED_CONFIGURATION</EXTENSION_TABLE_NAME>" << std::endl;
1426  *fedstream << " <NAME>Pixel FED Configuration</NAME>" << std::endl;
1427  *fedstream << " </TYPE>" << std::endl;
1428  *fedstream << " <RUN>" << std::endl;
1429  *fedstream << " <RUN_TYPE>Pixel FED Configuration</RUN_TYPE>" << std::endl;
1430  *fedstream << " <RUN_NUMBER>1</RUN_NUMBER>" << std::endl;
1431  *fedstream << " <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl;
1432  *fedstream << " <LOCATION>CERN P5</LOCATION>" << std::endl;
1433  *fedstream << " </RUN>" << std::endl;
1434  *fedstream << " </HEADER>" << std::endl;
1435  *fedstream << "" << std::endl;
1436  *fedstream << " <DATA_SET>" << std::endl;
1437  *fedstream << "" << std::endl;
1438  *fedstream << " <VERSION>" << version << "</VERSION>" << std::endl;
1439  *fedstream << " <COMMENT_DESCRIPTION>" << getComment() << "</COMMENT_DESCRIPTION>" << std::endl;
1440  *fedstream << " <CREATED_BY_USER>" << getAuthor() << "</CREATED_BY_USER>" << std::endl;
1441  *fedstream << "" << std::endl;
1442  *fedstream << " <PART>" << std::endl;
1443  *fedstream << " <NAME_LABEL>CMS-PIXEL-ROOT</NAME_LABEL>" << std::endl;
1444  *fedstream << " <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl;
1445  *fedstream << " </PART>" << std::endl;
1446 
1447  // ROC LEVELS MAIN XML FILE
1448  rocfullPath << path << "/Pixel_RocAnalogLevels_" << PixelTimeFormatter::getmSecTime() << ".xml";
1449  std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << rocfullPath.str() << "" << std::endl;
1450 
1451  rocstream->open(rocfullPath.str().c_str());
1452 
1453  *rocstream << "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"yes\"?>" << std::endl;
1454  *rocstream << "<ROOT xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\">" << std::endl;
1455  *rocstream << "" << std::endl;
1456  *rocstream << " <HEADER>" << std::endl;
1457  *rocstream << " <HINTS mode='only-det-root,load-as-group'/>" << std::endl;
1458  *rocstream << " <TYPE>" << std::endl;
1459  *rocstream << " <EXTENSION_TABLE_NAME>ROC_ANALOG_LEVELS</EXTENSION_TABLE_NAME>" << std::endl;
1460  *rocstream << " <NAME>ROC Analog Levels</NAME>" << std::endl;
1461  *rocstream << " </TYPE>" << std::endl;
1462  *rocstream << " <RUN>" << std::endl;
1463  *rocstream << " <RUN_TYPE>ROC Analog Levels</RUN_TYPE>" << std::endl;
1464  *rocstream << " <RUN_NUMBER>1</RUN_NUMBER> " << std::endl;
1465  *rocstream << " <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl;
1466  *rocstream << " <CREATED_BY_USER>Umesh Joshi</CREATED_BY_USER> " << std::endl;
1467  *rocstream << " <LOCATION>CERN</LOCATION> " << std::endl;
1468  *rocstream << " <COMMENT_DESCRIPTION>ROC Analog Levels Template</COMMENT_DESCRIPTION>" << std::endl;
1469  *rocstream << " </RUN>" << std::endl;
1470  *rocstream << " </HEADER>" << std::endl;
1471  *rocstream << "" << std::endl;
1472  *rocstream << " <DATA_SET>" << std::endl;
1473  *rocstream << " <COMMENT_DESCRIPTION>ROC Analog Levels Template</COMMENT_DESCRIPTION>" << std::endl;
1474  *rocstream << " <VERSION>" << version << "</VERSION>" << std::endl;
1475  *rocstream << " " << std::endl;
1476  *rocstream << " <PART>" << std::endl;
1477  *rocstream << " <SERIAL_NUMBER>CMS-PIXEL-ROOT</SERIAL_NUMBER>" << std::endl;
1478  *rocstream << " <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl;
1479  *rocstream << " </PART>" << std::endl;
1480 
1481  // TBM LEVELS MAIN XML FILE
1482  tbmfullPath << path << "/Pixel_TbmAnalogLevels_" << PixelTimeFormatter::getmSecTime() << ".xml";
1483  std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << tbmfullPath.str() << "" << std::endl;
1484 
1485  tbmstream->open(tbmfullPath.str().c_str());
1486 
1487  *tbmstream << "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"yes\"?>" << std::endl;
1488  *tbmstream << "<ROOT xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\">" << std::endl;
1489  *tbmstream << "" << std::endl;
1490  *tbmstream << " <HEADER>" << std::endl;
1491  *tbmstream << " <HINTS mode='only-det-root,load-as-group' />" << std::endl;
1492  *tbmstream << " <TYPE>" << std::endl;
1493  *tbmstream << " <EXTENSION_TABLE_NAME>TBM_ANALOG_LEVELS</EXTENSION_TABLE_NAME>" << std::endl;
1494  *tbmstream << " <NAME>TBM Analog Levels</NAME>" << std::endl;
1495  *tbmstream << " </TYPE>" << std::endl;
1496  *tbmstream << " <RUN>" << std::endl;
1497  *tbmstream << " <RUN_TYPE>TBM Analog Levels</RUN_TYPE>" << std::endl;
1498  *tbmstream << " <RUN_NUMBER>1</RUN_NUMBER>" << std::endl;
1499  *tbmstream << " <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl;
1500  *tbmstream << " <CREATED_BY_USER>Umesh Joshi</CREATED_BY_USER> " << std::endl;
1501  *tbmstream << " <LOCATION>CERN</LOCATION> " << std::endl;
1502  *tbmstream << " <COMMENT_DESCRIPTION>TBM Analog Levels</COMMENT_DESCRIPTION>" << std::endl;
1503  *tbmstream << " </RUN>" << std::endl;
1504  *tbmstream << " </HEADER>" << std::endl;
1505  *tbmstream << "" << std::endl;
1506  *tbmstream << " <DATA_SET>" << std::endl;
1507  *tbmstream << " <VERSION>" << version << "</VERSION>" << std::endl;
1508  *tbmstream << " " << std::endl;
1509  *tbmstream << " <PART>" << std::endl;
1510  *tbmstream << " <SERIAL_NUMBER>CMS-PIXEL-ROOT</SERIAL_NUMBER>" << std::endl;
1511  *tbmstream << " <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl;
1512  *tbmstream << " </PART>" << std::endl;
1513 }
1514 
1515 //=============================================================================================
1516 void PixelFEDCard::writeXMLHeader(pos::PixelConfigKey key, int version, std::string path, std::ofstream *out) const {
1517  std::string mthn = "[PixelFEDCard::writeXMLHeader()]\t\t\t ";
1518  std::stringstream fullPath;
1519 
1520  fullPath << path << "/fedcard_" << PixelTimeFormatter::getmSecTime() << ".xml";
1521  std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << fullPath.str() << "" << std::endl;
1522 
1523  out->open(fullPath.str().c_str());
1524 
1525  *out << "<?xml version='1.0' encoding='UTF-8' standalone='yes'?>" << std::endl;
1526  *out << "<ROOT>" << std::endl;
1527  *out << "" << std::endl;
1528  *out << " <HEADER>" << std::endl;
1529  *out << " <TYPE>" << std::endl;
1530  *out << " <EXTENSION_TABLE_NAME>FED_CONFIGURATION</EXTENSION_TABLE_NAME>" << std::endl;
1531  *out << " <NAME>Pixel FED Configuration</NAME>" << std::endl;
1532  *out << " </TYPE>" << std::endl;
1533  *out << " <RUN>" << std::endl;
1534  *out << " <RUN_TYPE>Pixel FED Configuration</RUN_TYPE>" << std::endl;
1535  *out << " <RUN_NUMBER>1</RUN_NUMBER>" << std::endl;
1536  *out << " <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl;
1537  *out << " <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl;
1538  *out << " <LOCATION>CERN TAC</LOCATION>" << std::endl;
1539  *out << " <CREATED_BY_USER>Dario Menasce</CREATED_BY_USER>" << std::endl;
1540  *out << " </RUN>" << std::endl;
1541  *out << " </HEADER>" << std::endl;
1542  *out << "" << std::endl;
1543  *out << " <DATA_SET>" << std::endl;
1544  *out << "" << std::endl;
1545  *out << " <VERSION>" << version << "</VERSION>" << std::endl;
1546  *out << " <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl;
1547  *out << "" << std::endl;
1548  *out << " <PART>" << std::endl;
1549  *out << " <NAME_LABEL>CMS-PIXEL-ROOT</NAME_LABEL>" << std::endl;
1550  *out << " <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl;
1551  *out << " </PART>" << std::endl;
1552 }
1553 //=============================================================================================
1554 void PixelFEDCard::writeXML(std::ofstream *out) const {
1555  std::string mthn = "[PixelFEDCard::writeXML()]\t\t\t ";
1556 
1557  *out << " <DATA>" << std::endl;
1558  *out << " " << std::endl;
1559  *out << " <PXLFED_NAME>PxlFED_" << fedNumber << "</PXLFED_NAME>" << std::endl;
1560  *out << " <VME_ADDRESS>268435456</VME_ADDRESS>" << std::endl;
1561  // *out << " <CRATE_NUMBER>1</CRATE_NUMBER>" << std::endl ;
1562  // *out << " <SLOT_NUMBER>5</SLOT_NUMBER> " << std::endl ;
1563  // *out << " <VME_ADDRESS>268435456</VME_ADDRESS>" << std::endl ;
1564  // *out << " <CRATE_LABEL>S1G03e</CRATE_LABEL>" << std::endl ;
1565  *out << "" << std::endl;
1566  *out << " <CHANNEL_ID>1</CHANNEL_ID>" << std::endl;
1567  *out << " <NUMBER_OF_ROCS>21</NUMBER_OF_ROCS>" << std::endl;
1568  *out << " <CHANNEL_OFFSET_DAC_SETTINGS>0</CHANNEL_OFFSET_DAC_SETTINGS>" << std::endl;
1569  *out << " <CHANNEL_DELAY_SETTINGS>3</CHANNEL_DELAY_SETTINGS>" << std::endl;
1570  *out << " <CHANNEL_BLACK_HIGH>400</CHANNEL_BLACK_HIGH>" << std::endl;
1571  *out << " <CHANNEL_BLACK_LOW>150</CHANNEL_BLACK_LOW>" << std::endl;
1572  *out << " <CHANNEL_ULTRA_BLACK>120</CHANNEL_ULTRA_BLACK>" << std::endl;
1573  *out << "" << std::endl;
1574  *out << " <OPT1_CAP>0</OPT1_CAP>" << std::endl;
1575  *out << " <OPT2_CAP>0</OPT2_CAP>" << std::endl;
1576  *out << " <OPT3_CAP>0</OPT3_CAP>" << std::endl;
1577  *out << " <OPT1_INP>0</OPT1_INP>" << std::endl;
1578  *out << " <OPT2_INP>0</OPT2_INP>" << std::endl;
1579  *out << " <OPT3_INP>0</OPT3_INP>" << std::endl;
1580  *out << " <OPT1_OUT>0</OPT1_OUT>" << std::endl;
1581  *out << " <OPT2_OUT>0</OPT2_OUT>" << std::endl;
1582  *out << " <OPT3_OUT>0</OPT3_OUT>" << std::endl;
1583  *out << " <NORTH_CLKPHB>511</NORTH_CLKPHB>" << std::endl;
1584  *out << " <NORTHCENTER_CLKPHB>511</NORTHCENTER_CLKPHB>" << std::endl;
1585  *out << " <SOUTHCENTER_CLKPHB>511</SOUTHCENTER_CLKPHB>" << std::endl;
1586  *out << " <SOUTH_CLKPHB>511</SOUTH_CLKPHB>" << std::endl;
1587  *out << " <NORTH_CTRL>0</NORTH_CTRL> " << std::endl;
1588  *out << " <NORTHCENTER_CTRL>0</NORTHCENTER_CTRL>" << std::endl;
1589  *out << " <SOUTHCENTER_CTRL>0</SOUTHCENTER_CTRL>" << std::endl;
1590  *out << " <SOUTH_CTRL>0</SOUTH_CTRL>" << std::endl;
1591  *out << " <REG1_TTCRX_FDLA>5</REG1_TTCRX_FDLA>" << std::endl;
1592  *out << " <REG2_TTCRX_CDLA>0</REG2_TTCRX_CDLA>" << std::endl;
1593  *out << " <REG3_TTCRX_CLKD2>155</REG3_TTCRX_CLKD2>" << std::endl;
1594  *out << " <CENTER_CTRL>0</CENTER_CTRL>" << std::endl;
1595  *out << " <CENTER_MODE>0</CENTER_MODE>" << std::endl;
1596  *out << " <B1_ADCGN>0</B1_ADCGN>" << std::endl;
1597  *out << " <B2_ADCGN>0</B2_ADCGN>" << std::endl;
1598  *out << " <B3_ADCGN>0</B3_ADCGN>" << std::endl;
1599  *out << " <B4_ADCGN>0</B4_ADCGN>" << std::endl;
1600  *out << " <NORTH_BADJ>330</NORTH_BADJ>" << std::endl;
1601  *out << " <NORTHCENTER_BADJ>330</NORTHCENTER_BADJ>" << std::endl;
1602  *out << " <SOUTHCENTER_BADJ>330</SOUTHCENTER_BADJ>" << std::endl;
1603  *out << " <SOUTH_BADJ>330</SOUTH_BADJ>" << std::endl;
1604  *out << " <NORTH_TBMMASK>2</NORTH_TBMMASK>" << std::endl;
1605  *out << " <NORTHCENTER_TBMMASK>2</NORTHCENTER_TBMMASK>" << std::endl;
1606  *out << " <SOUTHCENTER_TBMMASK>2</SOUTHCENTER_TBMMASK>" << std::endl;
1607  *out << " <SOUTH_TBMMASK>2</SOUTH_TBMMASK>" << std::endl;
1608  *out << " <NORTH_PWORD>177</NORTH_PWORD>" << std::endl;
1609  *out << " <NORTHCENTER_PWORD>178</NORTHCENTER_PWORD>" << std::endl;
1610  *out << " <SOUTHCENTER_PWORD>179</SOUTHCENTER_PWORD>" << std::endl;
1611  *out << " <SOUTH_PWORD>180</SOUTH_PWORD>" << std::endl;
1612  *out << " <SPECDAC>0</SPECDAC>" << std::endl;
1613  *out << " <OOS_LVL>0</OOS_LVL>" << std::endl;
1614  *out << " <ERR_LVL>0</ERR_LVL>" << std::endl;
1615  *out << " <NORTH_FIFO1_BZ_LVL>900</NORTH_FIFO1_BZ_LVL>" << std::endl;
1616  *out << " <NORTHCENTER_FIFO1_BZ_LVL>900</NORTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1617  *out << " <SOUTHCENTER_FIFO1_BZ_LVL>900</SOUTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1618  *out << " <SOUTH_FIFO1_BZ_LVL>900</SOUTH_FIFO1_BZ_LVL>" << std::endl;
1619  *out << " <FIFO3_WRN_LVL>7680</FIFO3_WRN_LVL> " << std::endl;
1620  *out << " <FED_MASTER_DELAY>0</FED_MASTER_DELAY>" << std::endl;
1621  *out << " <NO_HITLIMIT>0</NO_HITLIMIT>" << std::endl;
1622  *out << " <NC_HITLIMIT>0</NC_HITLIMIT>" << std::endl;
1623  *out << " <SC_HITLIMIT>0</SC_HITLIMIT>" << std::endl;
1624  *out << " <SO_HITLIMIT>0</SO_HITLIMIT>" << std::endl;
1625  *out << " <NO_TESTREG>0</NO_TESTREG>" << std::endl;
1626  *out << " <NC_TESTREG>0</NC_TESTREG>" << std::endl;
1627  *out << " <SC_TESTREG>0</SC_TESTREG>" << std::endl;
1628  *out << " <SO_TESTREG>0</SO_TESTREG>" << std::endl;
1629  *out << " <BUSYWHENBEHIND>4</BUSYWHENBEHIND>" << std::endl;
1630  *out << " <FEATUREREGISTER>0X1234</FEATUREREGISTER>" << std::endl;
1631  *out << " <FIFO2LIMIT>0X1C00</FIFO2LIMIT>" << std::endl;
1632  *out << " <TIMEOUTOROOSLIMIT>0</TIMEOUTOROOSLIMIT>" << std::endl;
1633  *out << " <LASTDACOFF>0</LASTDACOFF>" << std::endl;
1634  *out << " <SIMHITSPERROC>0</SIMHITSPERROC>" << std::endl;
1635  *out << " <BUSYHOLDMIN>0</BUSYHOLDMIN>" << std::endl;
1636  *out << " <SPARE1>0</SPARE1>" << std::endl;
1637  *out << " <SPARE2>0</SPARE2>" << std::endl;
1638  *out << " <SPARE3>0</SPARE3>" << std::endl;
1639  *out << " <SPARE4>0</SPARE4>" << std::endl;
1640  *out << " <SPARE5>0</SPARE5>" << std::endl;
1641  *out << " <SPARE6>0</SPARE6>" << std::endl;
1642  *out << " <SPARE7>0</SPARE7>" << std::endl;
1643  *out << " <SPARE8>0</SPARE8>" << std::endl;
1644  *out << " <SPARE9>0</SPARE9>" << std::endl;
1645  *out << " <SPARE10>0</SPARE10>" << std::endl;
1646  *out << " " << std::endl;
1647  *out << " </DATA>" << std::endl;
1648  *out << " " << std::endl;
1649 }
1650 
1651 //=============================================================================================
1652 void PixelFEDCard::writeXML(std::ofstream *fedstream, std::ofstream *rocstream, std::ofstream *tbmstream) const {
1653  std::string mthn = "[PixelFEDCard::writeXML()]\t\t\t ";
1654 
1655  for (int i = 0; i < 36; i++) {
1656  *fedstream << " <DATA>" << std::endl;
1657  *fedstream << " " << std::endl;
1658  *fedstream << " <PIXEL_FED>" << fedNumber << "</PIXEL_FED>" << std::endl;
1659  *fedstream << " <VME_ADDRS_HEX>0x" << hex << FEDBASE_0 << dec << "</VME_ADDRS_HEX>" << std::endl;
1660  *fedstream << "" << std::endl;
1661  *fedstream << " <CHANNEL_ID>" << i + 1 << "</CHANNEL_ID>" << std::endl;
1662  *fedstream << " <NUM_ROCS>" << NRocs[i] << "</NUM_ROCS>" << std::endl;
1663  *fedstream << " <CHAN_OFFST_DAC>" << offs_dac[i] << "</CHAN_OFFST_DAC>" << std::endl;
1664  *fedstream << " <CHAN_DELAY>" << DelayCh[i] << "</CHAN_DELAY>" << std::endl;
1665  *fedstream << " <CHAN_BHIGH>" << BlackHi[i] << "</CHAN_BHIGH>" << std::endl;
1666  *fedstream << " <CHAN_BLOW>" << BlackLo[i] << "</CHAN_BLOW>" << std::endl;
1667  *fedstream << " <CHAN_UB>" << Ublack[i] << "</CHAN_UB>" << std::endl;
1668  *fedstream << "" << std::endl;
1669  *fedstream << " <OPT1_CAP>" << opt_cap[0] << "</OPT1_CAP>" << std::endl;
1670  *fedstream << " <OPT2_CAP>" << opt_cap[1] << "</OPT2_CAP>" << std::endl;
1671  *fedstream << " <OPT3_CAP>" << opt_cap[2] << "</OPT3_CAP>" << std::endl;
1672  *fedstream << " <OPT1_INP>" << opt_inadj[0] << "</OPT1_INP>" << std::endl;
1673  *fedstream << " <OPT2_INP>" << opt_inadj[1] << "</OPT2_INP>" << std::endl;
1674  *fedstream << " <OPT3_INP>" << opt_inadj[2] << "</OPT3_INP>" << std::endl;
1675  *fedstream << " <OPT1_OUT>" << opt_ouadj[0] << "</OPT1_OUT>" << std::endl;
1676  *fedstream << " <OPT2_OUT>" << opt_ouadj[1] << "</OPT2_OUT>" << std::endl;
1677  *fedstream << " <OPT3_OUT>" << opt_ouadj[2] << "</OPT3_OUT>" << std::endl;
1678  *fedstream << " <NORTH_CLKPHB>" << clkphs1_9 << "</NORTH_CLKPHB>" << std::endl;
1679  *fedstream << " <NORTHCENTER_CLKPHB>" << clkphs10_18 << "</NORTHCENTER_CLKPHB>" << std::endl;
1680  *fedstream << " <SOUTHCENTER_CLKPHB>" << clkphs19_27 << "</SOUTHCENTER_CLKPHB>" << std::endl;
1681  *fedstream << " <SOUTH_CLKPHB>" << clkphs28_36 << "</SOUTH_CLKPHB>" << std::endl;
1682  *fedstream << " <NORTH_CTRL>" << Ncntrl << "</NORTH_CTRL> " << std::endl;
1683  *fedstream << " <NORTHCENTER_CTRL>" << NCcntrl << "</NORTHCENTER_CTRL>" << std::endl;
1684  *fedstream << " <SOUTHCENTER_CTRL>" << SCcntrl << "</SOUTHCENTER_CTRL>" << std::endl;
1685  *fedstream << " <SOUTH_CTRL>" << Scntrl << "</SOUTH_CTRL>" << std::endl;
1686  *fedstream << " <REG0_TTCRX_FDLA>" << FineDes1Del << "</REG0_TTCRX_FDLA>" << std::endl;
1687  *fedstream << " <REG1_TTCRX_FDLA>" << FineDes2Del << "</REG1_TTCRX_FDLA>" << std::endl;
1688  *fedstream << " <REG2_TTCRX_CDLA>" << CoarseDel << "</REG2_TTCRX_CDLA>" << std::endl;
1689  *fedstream << " <REG3_TTCRX_CLKD2>" << ClkDes2 << "</REG3_TTCRX_CLKD2>" << std::endl;
1690  *fedstream << " <CENTER_CTRL>" << Ccntrl << "</CENTER_CTRL>" << std::endl;
1691  *fedstream << " <CENTER_MODE>" << modeRegister << "</CENTER_MODE>" << std::endl;
1692  *fedstream << " <B1_ADCGN>" << Nadcg << "</B1_ADCGN>" << std::endl;
1693  *fedstream << " <B2_ADCGN>" << NCadcg << "</B2_ADCGN>" << std::endl;
1694  *fedstream << " <B3_ADCGN>" << SCadcg << "</B3_ADCGN>" << std::endl;
1695  *fedstream << " <B4_ADCGN>" << Sadcg << "</B4_ADCGN>" << std::endl;
1696  // std::cout << "PixelFEDCard::WriteXML()\tNbaseln:" << Nbaseln << std::endl ;
1697  // std::cout << "PixelFEDCard::WriteXML()\tNbaseln:" << std::hex << Nbaseln << std::dec << std::endl ;
1698  *fedstream << " <NORTH_BADJ>" << Nbaseln << "</NORTH_BADJ>" << std::endl;
1699  *fedstream << " <NORTHCENTER_BADJ>" << NCbaseln << "</NORTHCENTER_BADJ>" << std::endl;
1700  *fedstream << " <SOUTHCENTER_BADJ>" << SCbaseln << "</SOUTHCENTER_BADJ>" << std::endl;
1701  *fedstream << " <SOUTH_BADJ>" << Sbaseln << "</SOUTH_BADJ>" << std::endl;
1702  *fedstream << " <NORTH_TBMMASK>" << N_TBMmask << "</NORTH_TBMMASK>" << std::endl;
1703  *fedstream << " <NORTHCENTER_TBMMASK>" << NC_TBMmask << "</NORTHCENTER_TBMMASK>" << std::endl;
1704  *fedstream << " <SOUTHCENTER_TBMMASK>" << SC_TBMmask << "</SOUTHCENTER_TBMMASK>" << std::endl;
1705  *fedstream << " <SOUTH_TBMMASK>" << S_TBMmask << "</SOUTH_TBMMASK>" << std::endl;
1706  *fedstream << " <NORTH_PWORD>" << N_Pword << "</NORTH_PWORD>" << std::endl;
1707  *fedstream << " <NORTHCENTER_PWORD>" << NC_Pword << "</NORTHCENTER_PWORD>" << std::endl;
1708  *fedstream << " <SOUTHCENTER_PWORD>" << SC_Pword << "</SOUTHCENTER_PWORD>" << std::endl;
1709  *fedstream << " <SOUTH_PWORD>" << S_Pword << "</SOUTH_PWORD>" << std::endl;
1710  *fedstream << " <SPECDAC>" << SpecialDac << "</SPECDAC>" << std::endl;
1711  *fedstream << " <OOS_LVL>" << Ooslvl << "</OOS_LVL>" << std::endl;
1712  *fedstream << " <ERR_LVL>" << Errlvl << "</ERR_LVL>" << std::endl;
1713  *fedstream << " <NORTH_FIFO1_BZ_LVL>" << Nfifo1Bzlvl << "</NORTH_FIFO1_BZ_LVL>" << std::endl;
1714  *fedstream << " <NORTHCENTER_FIFO1_BZ_LVL>" << NCfifo1Bzlvl << "</NORTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1715  *fedstream << " <SOUTHCENTER_FIFO1_BZ_LVL>" << SCfifo1Bzlvl << "</SOUTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1716  *fedstream << " <SOUTH_FIFO1_BZ_LVL>" << Sfifo1Bzlvl << "</SOUTH_FIFO1_BZ_LVL>" << std::endl;
1717  *fedstream << " <FIFO3_WRN_LVL>" << fifo3Wrnlvl << "</FIFO3_WRN_LVL>" << std::endl;
1718  *fedstream << " <FED_MASTER_DELAY>" << FedTTCDelay << "</FED_MASTER_DELAY>" << std::endl;
1719  *fedstream << " <NO_HITLIMIT>" << N_hitlimit << "</NO_HITLIMIT>" << std::endl;
1720  *fedstream << " <NC_HITLIMIT>" << NC_hitlimit << "</NC_HITLIMIT>" << std::endl;
1721  *fedstream << " <SC_HITLIMIT>" << SC_hitlimit << "</SC_HITLIMIT>" << std::endl;
1722  *fedstream << " <SO_HITLIMIT>" << S_hitlimit << "</SO_HITLIMIT>" << std::endl;
1723  *fedstream << " <NO_TESTREG>" << N_testreg << "</NO_TESTREG>" << std::endl;
1724  *fedstream << " <NC_TESTREG>" << NC_testreg << "</NC_TESTREG>" << std::endl;
1725  *fedstream << " <SC_TESTREG>" << SC_testreg << "</SC_TESTREG>" << std::endl;
1726  *fedstream << " <SO_TESTREG>" << S_testreg << "</SO_TESTREG>" << std::endl;
1727  *fedstream << " <BUSYWHENBEHIND>" << BusyWhenBehind << "</BUSYWHENBEHIND>" << std::endl;
1728  *fedstream << " <BUSYHOLDMIN>" << BusyHoldMin << "</BUSYHOLDMIN>" << std::endl;
1729  *fedstream << " <FEATUREREGISTER>" << FeatureRegister << "</FEATUREREGISTER>" << std::endl;
1730  *fedstream << " <FIFO2LIMIT>" << FIFO2Limit << "</FIFO2LIMIT>" << std::endl;
1731  *fedstream << " <LASTDACOFF>" << LastDacOff << "</LASTDACOFF>" << std::endl;
1732  *fedstream << " <SIMHITSPERROC>" << SimHitsPerRoc << "</SIMHITSPERROC>" << std::endl;
1733  *fedstream << " <TIMEOUTOROOSLIMIT>" << TimeoutOROOSLimit << "</TIMEOUTOROOSLIMIT>" << std::endl;
1734  *fedstream << " <TRIGGERHOLDOFF>" << TriggerHoldoff << "</TRIGGERHOLDOFF>" << std::endl;
1735  *fedstream << " <SPARE1>" << SPARE1 << "</SPARE1>" << std::endl;
1736  *fedstream << " <SPARE2>" << SPARE2 << "</SPARE2>" << std::endl;
1737  *fedstream << " <SPARE3>" << SPARE3 << "</SPARE3>" << std::endl;
1738  *fedstream << " <SPARE4>" << SPARE4 << "</SPARE4>" << std::endl;
1739  *fedstream << " <SPARE5>" << SPARE5 << "</SPARE5>" << std::endl;
1740  *fedstream << " <SPARE6>" << SPARE6 << "</SPARE6>" << std::endl;
1741  *fedstream << " <SPARE7>" << SPARE7 << "</SPARE7>" << std::endl;
1742  *fedstream << " <SPARE8>" << SPARE8 << "</SPARE8>" << std::endl;
1743  *fedstream << " <SPARE9>" << SPARE9 << "</SPARE9>" << std::endl;
1744  *fedstream << " <SPARE10>" << SPARE10 << "</SPARE10>" << std::endl;
1745  *fedstream << " " << std::endl;
1746  *fedstream << " </DATA>" << std::endl;
1747  *fedstream << " " << std::endl;
1748  }
1749 
1750  //ROC & TBM LEVELS
1751  for (int i = 0; i < 36; i++) {
1752  for (int j = 0; j < NRocs[i]; j++) {
1753  *rocstream << "" << std::endl;
1754  *rocstream << " <DATA>" << std::endl;
1755  *rocstream << " <PIXEL_FED>" << fedNumber << "</PIXEL_FED>" << std::endl;
1756  *rocstream << " <FED_CHAN>" << i + 1 << "</FED_CHAN>" << std::endl;
1757  *rocstream << " <FED_ROC_NUM>" << j << "</FED_ROC_NUM>" << std::endl;
1758  *rocstream << " <ROC_L0>" << ROC_L0[i][j] << "</ROC_L0>" << std::endl;
1759  *rocstream << " <ROC_L1>" << ROC_L1[i][j] << "</ROC_L1>" << std::endl;
1760  *rocstream << " <ROC_L2>" << ROC_L2[i][j] << "</ROC_L2>" << std::endl;
1761  *rocstream << " <ROC_L3>" << ROC_L3[i][j] << "</ROC_L3>" << std::endl;
1762  *rocstream << " <ROC_L4>" << ROC_L4[i][j] << "</ROC_L4>" << std::endl;
1763  *rocstream << " </DATA>" << std::endl << std::endl;
1764  *rocstream << " " << std::endl;
1765  }
1766 
1767  *tbmstream << "" << std::endl;
1768  *tbmstream << " <DATA>" << std::endl;
1769  *tbmstream << " <PIXEL_FED>" << fedNumber << "</PIXEL_FED>" << std::endl;
1770  *tbmstream << " <FED_CHAN>" << i + 1 << "</FED_CHAN>" << std::endl;
1771  *tbmstream << " <TBMA_HEAD_L0>" << TBM_L0[i] << "</TBMA_HEAD_L0>" << std::endl;
1772  *tbmstream << " <TBMA_HEAD_L1>" << TBM_L1[i] << "</TBMA_HEAD_L1>" << std::endl;
1773  *tbmstream << " <TBMA_HEAD_L2>" << TBM_L2[i] << "</TBMA_HEAD_L2>" << std::endl;
1774  *tbmstream << " <TBMA_HEAD_L3>" << TBM_L3[i] << "</TBMA_HEAD_L3>" << std::endl;
1775  *tbmstream << " <TBMA_HEAD_L4>" << TBM_L4[i] << "</TBMA_HEAD_L4>" << std::endl;
1776  *tbmstream << " <TBMA_TRAIL_L0>" << TRL_L0[i] << "</TBMA_TRAIL_L0>" << std::endl;
1777  *tbmstream << " <TBMA_TRAIL_L1>" << TRL_L1[i] << "</TBMA_TRAIL_L1>" << std::endl;
1778  *tbmstream << " <TBMA_TRAIL_L2>" << TRL_L2[i] << "</TBMA_TRAIL_L2>" << std::endl;
1779  *tbmstream << " <TBMA_TRAIL_L3>" << TRL_L3[i] << "</TBMA_TRAIL_L3>" << std::endl;
1780  *tbmstream << " <TBMA_TRAIL_L4>" << TRL_L4[i] << "</TBMA_TRAIL_L4>" << std::endl;
1781  *tbmstream << " </DATA>" << std::endl << std::endl;
1782  *tbmstream << "" << std::endl;
1783  }
1784 }
1785 
1786 //=============================================================================================
1787 void PixelFEDCard::writeXMLTrailer(std::ofstream *fedstream, std::ofstream *rocstream, std::ofstream *tbmstream) const {
1788  std::string mthn = "[PixelFEDCard::writeXMLTrailer()]\t\t\t ";
1789 
1790  // Main FED
1791  *fedstream << " </DATA_SET>" << std::endl;
1792  *fedstream << "</ROOT>" << std::endl;
1793 
1794  fedstream->close();
1795  std::cout << __LINE__ << "]\t" << mthn << "Data written for main fed" << std::endl;
1796 
1797  // ROC LVLS
1798  *rocstream << " </DATA_SET>" << std::endl;
1799  *rocstream << "</ROOT>" << std::endl;
1800 
1801  rocstream->close();
1802  std::cout << __LINE__ << "]\t" << mthn << "Data written for roc analog levels" << std::endl;
1803 
1804  // TBM LVLS
1805  *tbmstream << " </DATA_SET>" << std::endl;
1806  *tbmstream << "</ROOT>" << std::endl;
1807 
1808  tbmstream->close();
1809  std::cout << __LINE__ << "]\t" << mthn << "Data written for tbm analog levels" << std::endl;
1810 }
1811 
1812 //=============================================================================================
1813 void PixelFEDCard::writeXMLTrailer(std::ofstream *out) const {
1814  std::string mthn = "[PixelFEDCard::writeXMLTrailer()]\t\t\t ";
1815 
1816  *out << " </DATA_SET>" << std::endl;
1817  *out << "</ROOT>" << std::endl;
1818 
1819  out->close();
1820  std::cout << __LINE__ << "]\t" << mthn << "Data written" << std::endl;
1821 }
1822 
1823 //=============================================================================================
1824 void PixelFEDCard::writeXML(pos::PixelConfigKey key, int version, std::string path) const {
1825  std::string mthn = "[PixelFEDCard::writeXML()]\t\t\t ";
1826  std::stringstream fullPath;
1827 
1828  fullPath << path << "/fedcard.xml";
1829  std::cout << __LINE__ << "]\t" << mthn << "Writing to: |" << fullPath.str() << "|" << std::endl;
1830 
1831  std::ofstream out(fullPath.str().c_str());
1832 
1833  out << "<ROOT>" << std::endl;
1834  out << "" << std::endl;
1835  out << " <HEADER>" << std::endl;
1836  out << " <TYPE>" << std::endl;
1837  out << " <EXTENSION_TABLE_NAME>FED_CONFIGURATION</EXTENSION_TABLE_NAME>" << std::endl;
1838  out << " <NAME>Pixel FED Configuration</NAME>" << std::endl;
1839  out << " </TYPE>" << std::endl;
1840  out << " <RUN>" << std::endl;
1841  out << " <RUN_TYPE>Pixel FED Configuration</RUN_TYPE>" << std::endl;
1842  out << " <RUN_NUMBER>1</RUN_NUMBER>" << std::endl;
1843  out << " <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl;
1844  out << " <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl;
1845  out << " <LOCATION>CERN TAC</LOCATION>" << std::endl;
1846  out << " <CREATED_BY_USER>Dario Menasce</CREATED_BY_USER>" << std::endl;
1847  out << " </RUN>" << std::endl;
1848  out << " </HEADER>" << std::endl;
1849  out << "" << std::endl;
1850  out << " <DATA_SET>" << std::endl;
1851  out << "" << std::endl;
1852  out << " <VERSION>T_E_S_T</VERSION>" << std::endl;
1853  out << " <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl;
1854  out << "" << std::endl;
1855  out << " <PART>" << std::endl;
1856  out << " <NAME_LABEL>CMS-PIXEL-ROOT</NAME_LABEL>" << std::endl;
1857  out << " <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl;
1858  out << " </PART>" << std::endl;
1859  out << "" << std::endl;
1860  out << " <DATA>" << std::endl;
1861  out << " <PXLFED_NAME>PxlFED_32</PXLFED_NAME>" << std::endl;
1862  out << " <CRATE_NUMBER>1</CRATE_NUMBER>" << std::endl;
1863  out << " <SLOT_NUMBER>5</SLOT_NUMBER> " << std::endl;
1864  out << " <VME_ADDRESS>268435456</VME_ADDRESS>" << std::endl;
1865  out << " <CRATE_LABEL>S1G03e</CRATE_LABEL>" << std::endl;
1866  out << "" << std::endl;
1867  out << " <CHANNEL_ID>1</CHANNEL_ID>" << std::endl;
1868  out << " <NUMBER_OF_ROCS>21</NUMBER_OF_ROCS>" << std::endl;
1869  out << " <CHANNEL_OFFSET_DAC_SETTINGS>0</CHANNEL_OFFSET_DAC_SETTINGS>" << std::endl;
1870  out << " <CHANNEL_DELAY_SETTINGS>3</CHANNEL_DELAY_SETTINGS>" << std::endl;
1871  out << " <CHANNEL_BLACK_HIGH>400</CHANNEL_BLACK_HIGH>" << std::endl;
1872  out << " <CHANNEL_BLACK_LOW>150</CHANNEL_BLACK_LOW>" << std::endl;
1873  out << " <CHANNEL_ULTRA_BLACK>120</CHANNEL_ULTRA_BLACK>" << std::endl;
1874  out << "" << std::endl;
1875  out << " <OPT1_CAP>0</OPT1_CAP>" << std::endl;
1876  out << " <OPT2_CAP>0</OPT2_CAP>" << std::endl;
1877  out << " <OPT3_CAP>0</OPT3_CAP>" << std::endl;
1878  out << " <OPT1_INP>0</OPT1_INP>" << std::endl;
1879  out << " <OPT2_INP>0</OPT2_INP>" << std::endl;
1880  out << " <OPT3_INP>0</OPT3_INP>" << std::endl;
1881  out << " <OPT1_OUT>0</OPT1_OUT>" << std::endl;
1882  out << " <OPT2_OUT>0</OPT2_OUT>" << std::endl;
1883  out << " <OPT3_OUT>0</OPT3_OUT>" << std::endl;
1884  out << " <NORTH_CLKPHB>511</NORTH_CLKPHB>" << std::endl;
1885  out << " <NORTHCENTER_CLKPHB>511</NORTHCENTER_CLKPHB>" << std::endl;
1886  out << " <SOUTHCENTER_CLKPHB>511</SOUTHCENTER_CLKPHB>" << std::endl;
1887  out << " <SOUTH_CLKPHB>511</SOUTH_CLKPHB>" << std::endl;
1888  out << " <NORTH_CTRL>0</NORTH_CTRL> " << std::endl;
1889  out << " <NORTHCENTER_CTRL>0</NORTHCENTER_CTRL>" << std::endl;
1890  out << " <SOUTHCENTER_CTRL>0</SOUTHCENTER_CTRL>" << std::endl;
1891  out << " <SOUTH_CTRL>0</SOUTH_CTRL>" << std::endl;
1892  out << " <REG1_TTCRX_FDLA>5</REG1_TTCRX_FDLA>" << std::endl;
1893  out << " <REG2_TTCRX_CDLA>0</REG2_TTCRX_CDLA>" << std::endl;
1894  out << " <REG3_TTCRX_CLKD2>155</REG3_TTCRX_CLKD2>" << std::endl;
1895  out << " <CENTER_CTRL>0</CENTER_CTRL>" << std::endl;
1896  out << " <CENTER_MODE>0</CENTER_MODE>" << std::endl;
1897  out << " <B1_ADCGN>0</B1_ADCGN>" << std::endl;
1898  out << " <B2_ADCGN>0</B2_ADCGN>" << std::endl;
1899  out << " <B3_ADCGN>0</B3_ADCGN>" << std::endl;
1900  out << " <B4_ADCGN>0</B4_ADCGN>" << std::endl;
1901  out << " <NORTH_BADJ>330</NORTH_BADJ>" << std::endl;
1902  out << " <NORTHCENTER_BADJ>330</NORTHCENTER_BADJ>" << std::endl;
1903  out << " <SOUTHCENTER_BADJ>330</SOUTHCENTER_BADJ>" << std::endl;
1904  out << " <SOUTH_BADJ>330</SOUTH_BADJ>" << std::endl;
1905  out << " <NORTH_TBMMASK>2</NORTH_TBMMASK>" << std::endl;
1906  out << " <NORTHCENTER_TBMMASK>2</NORTHCENTER_TBMMASK>" << std::endl;
1907  out << " <SOUTHCENTER_TBMMASK>2</SOUTHCENTER_TBMMASK>" << std::endl;
1908  out << " <SOUTH_TBMMASK>2</SOUTH_TBMMASK>" << std::endl;
1909  out << " <NORTH_PWORD>177</NORTH_PWORD>" << std::endl;
1910  out << " <NORTHCENTER_PWORD>178</NORTHCENTER_PWORD>" << std::endl;
1911  out << " <SOUTHCENTER_PWORD>179</SOUTHCENTER_PWORD>" << std::endl;
1912  out << " <SOUTH_PWORD>180</SOUTH_PWORD>" << std::endl;
1913  out << " <SPECDAC>0</SPECDAC>" << std::endl;
1914  out << " <OOS_LVL>0</OOS_LVL>" << std::endl;
1915  out << " <ERR_LVL>0</ERR_LVL>" << std::endl;
1916  out << " <NORTH_FIFO1_BZ_LVL>900</NORTH_FIFO1_BZ_LVL>" << std::endl;
1917  out << " <NORTHCENTER_FIFO1_BZ_LVL>900</NORTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1918  out << " <SOUTHCENTER_FIFO1_BZ_LVL>900</SOUTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1919  out << " <SOUTH_FIFO1_BZ_LVL>900</SOUTH_FIFO1_BZ_LVL>" << std::endl;
1920  out << " <FIFO3_WRN_LVL>7680</FIFO3_WRN_LVL> " << std::endl;
1921  out << " <FED_MASTER_DELAY>0</FED_MASTER_DELAY>" << std::endl;
1922  out << " <NO_HITLIMIT>0</NO_HITLIMIT>" << std::endl;
1923  out << " <NC_HITLIMIT>0</NC_HITLIMIT>" << std::endl;
1924  out << " <SC_HITLIMIT>0</SC_HITLIMIT>" << std::endl;
1925  out << " <SO_HITLIMIT>0</SO_HITLIMIT>" << std::endl;
1926  out << " <NO_TESTREG>0</NO_TESTREG>" << std::endl;
1927  out << " <NC_TESTREG>0</NC_TESTREG>" << std::endl;
1928  out << " <SC_TESTREG>0</SC_TESTREG>" << std::endl;
1929  out << " <SO_TESTREG>0</SO_TESTREG>" << std::endl;
1930  out << " <BUSYWHENBEHIND>4</BUSYWHENBEHIND>" << std::endl;
1931  out << " <FEATUREREGISTER>0X1234</FEATUREREGISTER>" << std::endl;
1932  out << " <FIFO2LIMIT>0X1C00</FIFO2LIMIT>" << std::endl;
1933  out << " <TIMEOUTOROOSLIMIT>0</TIMEOUTOROOSLIMIT>" << std::endl;
1934  out << " <LASTDACOFF>0</LASTDACOFF>" << std::endl;
1935  out << " <SIMHITSPERROC>0</SIMHITSPERROC>" << std::endl;
1936  out << " <BUSYHOLDMIN>0</BUSYHOLDMIN>" << std::endl;
1937  out << " <SPARE1>0</SPARE1>" << std::endl;
1938  out << " <SPARE2>0</SPARE2>" << std::endl;
1939  out << " <SPARE3>0</SPARE3>" << std::endl;
1940  out << " <SPARE4>0</SPARE4>" << std::endl;
1941  out << " <SPARE5>0</SPARE5>" << std::endl;
1942  out << " <SPARE6>0</SPARE6>" << std::endl;
1943  out << " <SPARE7>0</SPARE7>" << std::endl;
1944  out << " <SPARE8>0</SPARE8>" << std::endl;
1945  out << " <SPARE9>0</SPARE9>" << std::endl;
1946  out << " <SPARE10>0</SPARE10>" << std::endl;
1947  out << " </DATA>" << std::endl;
1948  /*
1949  out<< " <DATA>
1950  <OPT1_CAP>0</OPT1_CAP>
1951  <OPT2_CAP>0</OPT2_CAP>
1952  <OPT3_CAP>0</OPT3_CAP>
1953  <OPT1_INP>0</OPT1_INP>
1954  <OPT2_INP>0</OPT2_INP>
1955  <OPT3_INP>0</OPT3_INP>
1956  <OPT1_OUT>0</OPT1_OUT>
1957  <OPT2_OUT>0</OPT2_OUT>
1958  <OPT3_OUT>0</OPT3_OUT>
1959  <NORTH_CLKPHB>511</NORTH_CLKPHB>
1960  <NORTHCENTER_CLKPHB>511</NORTHCENTER_CLKPHB>
1961  <SOUTHCENTER_CLKPHB>511</SOUTHCENTER_CLKPHB>
1962  <SOUTH_CLKPHB>511</SOUTH_CLKPHB>
1963  <NORTH_CTRL>0</NORTH_CTRL>
1964  <NORTHCENTER_CTRL>0</NORTHCENTER_CTRL>
1965  <SOUTHCENTER_CTRL>0</SOUTHCENTER_CTRL>
1966  <SOUTH_CTRL>0</SOUTH_CTRL>
1967  <REG1_TTCRX_FDLA>5</REG1_TTCRX_FDLA>
1968  <REG2_TTCRX_CDLA>0</REG2_TTCRX_CDLA>
1969  <REG3_TTCRX_CLKD2>155</REG3_TTCRX_CLKD2>
1970  <CENTER_CTRL>0</CENTER_CTRL>
1971  <CENTER_MODE>0</CENTER_MODE>
1972  <B1_ADCGN>0</B1_ADCGN>
1973  <B2_ADCGN>0</B2_ADCGN>
1974  <B3_ADCGN>0</B3_ADCGN>
1975  <B4_ADCGN>0</B4_ADCGN>
1976  <NORTH_BADJ>330</NORTH_BADJ>
1977  <NORTHCENTER_BADJ>330</NORTHCENTER_BADJ>
1978  <SOUTHCENTER_BADJ>330</SOUTHCENTER_BADJ>
1979  <SOUTH_BADJ>330</SOUTH_BADJ>
1980  <NORTH_TBMMASK>2</NORTH_TBMMASK>
1981  <NORTHCENTER_TBMMASK>2</NORTHCENTER_TBMMASK>
1982  <SOUTHCENTER_TBMMASK>2</SOUTHCENTER_TBMMASK>
1983  <SOUTH_TBMMASK>2</SOUTH_TBMMASK>
1984  <NORTH_PWORD>177</NORTH_PWORD>
1985  <NORTHCENTER_PWORD>178</NORTHCENTER_PWORD>
1986  <SOUTHCENTER_PWORD>179</SOUTHCENTER_PWORD>
1987  <SOUTH_PWORD>180</SOUTH_PWORD>
1988  <SPECDAC>0</SPECDAC>
1989  <OOS_LVL>0</OOS_LVL>
1990  <ERR_LVL>0</ERR_LVL>
1991  <NORTH_FIFO1_BZ_LVL>900</NORTH_FIFO1_BZ_LVL>
1992  <NORTHCENTER_FIFO1_BZ_LVL>900</NORTHCENTER_FIFO1_BZ_LVL>
1993  <SOUTHCENTER_FIFO1_BZ_LVL>900</SOUTHCENTER_FIFO1_BZ_LVL>
1994  <SOUTH_FIFO1_BZ_LVL>900</SOUTH_FIFO1_BZ_LVL>
1995  <FIFO3_WRN_LVL>7680</FIFO3_WRN_LVL>
1996  </DATA>
1997 
1998  </DATA_SET>
1999  out << " </DATA_SET>" << std::endl ;
2000  out << "</ROOT>" << std::endl ;
2001 
2002  out.close() ;
2003 */
2004  std::cout << __LINE__ << "]\t" << mthn << "Data written" << std::endl;
2005 }
2006 
2007 //=============================================================================================
2008 uint64_t PixelFEDCard::enabledChannels() {
2009  uint64_t channels = 0;
2010  // return a 64-bit word with low 36 bits set if a channel is enabled
2011  // if bits are set in the control registers, transfer of data from
2012  // fifo1 to fifo 2 is not done, meaning the channel is disabled.
2013  channels = (Ncntrl & 0x1ffLL); // Add LL for SLC4, d.k. 12/07
2014  channels += (NCcntrl & 0x1ffLL) << 9;
2015  channels += (SCcntrl & 0x1ffLL) << 18;
2016  channels += (Scntrl & 0x1ffLL) << 27;
2017  return ~channels; //bitwise complement to get enabled channels
2018 }
2019 
2020 bool PixelFEDCard::useChannel(unsigned int iChannel) {
2021  assert(iChannel > 0 && iChannel < 37);
2022  return (enabledChannels() >> (iChannel - 1)) & 0x1LL;
2023 }
2024 
2025 void PixelFEDCard::setChannel(unsigned int iChannel, bool mode) {
2026  assert(iChannel > 0 && iChannel < 37);
2027  long long mask = enabledChannels();
2028  long long bit = 0x1LL << (iChannel - 1);
2029  if (mode) {
2030  mask = mask | bit;
2031  } else {
2032  bit = ~bit;
2033  mask = mask & bit;
2034  }
2035  mask = ~mask;
2036  Ncntrl = (Ncntrl & 0xffff0000LL) | (mask & 0x1ffLL);
2037  mask = mask >> 9;
2038  NCcntrl = (NCcntrl & 0xffff0000LL) | (mask & 0x1ffLL);
2039  mask = mask >> 9;
2040  SCcntrl = (SCcntrl & 0xffff0000LL) | (mask & 0x1ffLL);
2041  mask = mask >> 9;
2042  Scntrl = (Scntrl & 0xffff0000LL) | (mask & 0x1ffLL);
2043 }
2044 
2045 void PixelFEDCard::restoreBaselinAndChannelMasks() {
2046  Ncntrl = Ncntrl_original;
2047  NCcntrl = NCcntrl_original;
2048  SCcntrl = SCcntrl_original;
2049  Scntrl = Scntrl_original;
2050 
2051  Nbaseln = Nbaseln_original;
2052  NCbaseln = NCbaseln_original;
2053  SCbaseln = SCbaseln_original;
2054  Sbaseln = Sbaseln_original;
2055 }
2056 
2057 void PixelFEDCard::restoreControlAndModeRegister() {
2058  Ccntrl = Ccntrl_original;
2059  modeRegister = modeRegister_original;
2060 }
2061 
2062 /* Emacs specific customization
2063  ;;; Local Variables: ***
2064  ;;; indent-tabs-mode:nil ***
2065  ;;; c-set-style:gnu ***
2066  ;;; End: ***
2067 */
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Write out results.
Definition: findQualityFiles.py:443
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Definition: PixelClustering.h:35
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This file contains the base class for "pixel configuration data" management.
Definition: PixelConfigBase.h:32
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Definition: mps_fire.py:429
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Definition: PixelFEDCard.h:106
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Definition: L1DTConfigBti_cff.py:25
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Definition: AlCaHLTBitMon_QueryRunRegistry.py:256
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Definition: PixelFEDCard.cc:2020
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Definition: PixelFEDCard.cc:396
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Definition: PixelConfigKey.h:20
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Definition: PixelFEDCard.h:72
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