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SiStripRegFEDSelector.cc
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1 // system include files
2 #include <memory>
3 
4 // user include files
14 
21 
23 public:
25  ~SiStripRegFEDSelector() override;
26 
27  static void fillDescriptions(edm::ConfigurationDescriptions& descriptions);
28 
29 private:
30  void beginJob() override {}
31  void produce(edm::StreamID, edm::Event&, const edm::EventSetup&) const override;
32  void endJob() override {}
33 
37  const double delta_;
38 };
39 
41  : tok_seed_(consumes<trigger::TriggerFilterObjectWithRefs>(iConfig.getParameter<edm::InputTag>("regSeedLabel"))),
42  tok_raw_(consumes<FEDRawDataCollection>(iConfig.getParameter<edm::InputTag>("rawInputLabel"))),
44  delta_(iConfig.getParameter<double>("delta")) {
45  produces<FEDRawDataCollection>();
46 }
47 
49 
51  auto producedData = std::make_unique<FEDRawDataCollection>();
52 
54 
55  std::vector<edm::Ref<reco::IsolatedPixelTrackCandidateCollection> > isoPixTrackRefs;
56  trigSeedTrks->getObjects(trigger::TriggerTrack, isoPixTrackRefs);
57 
58  const edm::Handle<FEDRawDataCollection>& rawIn = iEvent.getHandle(tok_raw_);
59 
60  const SiStripRegionCabling* strip_cabling = &iSetup.getData(tok_strip_);
61  std::vector<int> stripFEDVec;
62 
63  //get vector of regions
64  const SiStripRegionCabling::Cabling& ccab = strip_cabling->getRegionCabling();
65 
66  //size of region (eta,phi)
67  const std::pair<double, double> regDim = strip_cabling->regionDimensions();
68 
70 
71  bool fedSaved[1000];
72  for (int i = 0; i < 1000; i++)
73  fedSaved[i] = false;
74 
75  //cycle on seeds
76  for (uint32_t p = 0; p < isoPixTrackRefs.size(); p++) {
77  double etaObj_ = isoPixTrackRefs[p]->track()->eta();
78  double phiObj_ = isoPixTrackRefs[p]->track()->phi();
79 
80  //cycle on regions
81  for (uint32_t i = 0; i < ccab.size(); i++) {
82  SiStripRegionCabling::Position pos = strip_cabling->position(i);
83  double dphi = fabs(pos.second - phiObj_);
84  if (dphi > acos(-1))
85  dphi = 2 * acos(-1) - dphi;
86  double R = sqrt(pow(pos.first - etaObj_, 2) + dphi * dphi);
87  if (R - sqrt(pow(regDim.first / 2, 2) + pow(regDim.second / 2, 2)) > delta_)
88  continue;
89  //get vector of subdets within region
90  const SiStripRegionCabling::RegionCabling regSubdets = ccab[i];
91  //cycle on subdets
92  for (uint32_t idet = 0; idet < SiStripRegionCabling::ALLSUBDETS; idet++) {
93  //get vector of layers within subdet of region
94  const SiStripRegionCabling::WedgeCabling& regSubdetLayers = regSubdets[idet];
95  for (uint32_t ilayer = 0; ilayer < SiStripRegionCabling::ALLLAYERS; ilayer++) {
96  //get map of vectors of feds withing the layer of subdet of region
97  const SiStripRegionCabling::ElementCabling& fedVectorMap = regSubdetLayers[ilayer];
98  SiStripRegionCabling::ElementCabling::const_iterator it = fedVectorMap.begin();
99  for (; it != fedVectorMap.end(); it++) {
100  for (uint32_t op = 0; op < (it->second).size(); op++) {
101  //get fed id
102  int fediid = (it->second)[op].fedId();
103  if (!fedSaved[fediid]) {
104  stripFEDVec.push_back(fediid);
105  }
106  fedSaved[fediid] = true;
107  }
108  }
109  }
110  }
111  }
112  }
113 
115 
116  const FEDRawDataCollection* rdc = rawIn.product();
117 
118  // if ( ( rawData[i].provenance()->processName() != e.processHistory().rbegin()->processName() ) )
119  // continue ; // skip all raw collections not produced by the current process
120 
121  for (int j = 0; j <= FEDNumbering::MAXFEDID; ++j) {
122  bool rightFED = false;
123  for (uint32_t k = 0; k < stripFEDVec.size(); k++) {
124  if (j == stripFEDVec[k]) {
125  rightFED = true;
126  }
127  }
128  if (!rightFED)
129  continue;
130  const FEDRawData& fedData = rdc->FEDData(j);
131  size_t size = fedData.size();
132 
133  if (size > 0) {
134  // this fed has data -- lets copy it
135  FEDRawData& fedDataProd = producedData->FEDData(j);
136  if (fedDataProd.size() != 0) {
137  edm::LogVerbatim("HcalIsoTrack") << " More than one FEDRawDataCollection with data in FED " << j
138  << " Skipping the 2nd *****";
139  continue;
140  }
141  fedDataProd.resize(size);
142  unsigned char* dataProd = fedDataProd.data();
143  const unsigned char* data = fedData.data();
144  for (unsigned int k = 0; k < size; ++k) {
145  dataProd[k] = data[k];
146  }
147  }
148  }
149 
150  iEvent.put(std::move(producedData));
151 }
152 
155  desc.add<edm::InputTag>("regSeedLabel", edm::InputTag("hltIsolPixelTrackFilter"));
156  desc.add<edm::InputTag>("rawInputLabel", edm::InputTag("rawDataCollector"));
157  desc.add<double>("delta", 1.0);
158  descriptions.add("stripFED", desc);
159 }
160 
163 
size
Write out results.
SiStripRegFEDSelector(const edm::ParameterSet &)
Log< level::Info, true > LogVerbatim
ESGetTokenH3DDVariant esConsumes(std::string const &Record, edm::ConsumesCollector &)
Definition: DeDxTools.cc:283
T const & getData(const ESGetToken< T, R > &iToken) const noexcept(false)
Definition: EventSetup.h:119
T const * product() const
Definition: Handle.h:70
size_t size() const
Lenght of the data buffer in bytes.
Definition: FEDRawData.h:48
const edm::EDGetTokenT< FEDRawDataCollection > tok_raw_
const Cabling & getRegionCabling() const
std::vector< Element > ElementCabling
const Position position(const uint32_t) const
int iEvent
Definition: GenABIO.cc:224
T sqrt(T t)
Definition: SSEVec.h:23
const edm::EDGetTokenT< trigger::TriggerFilterObjectWithRefs > tok_seed_
static void fillDescriptions(edm::ConfigurationDescriptions &descriptions)
#define DEFINE_FWK_MODULE(type)
Definition: MakerMacros.h:16
std::vector< RegionCabling > Cabling
const FEDRawData & FEDData(int fedid) const
retrieve data for fed
void produce(edm::StreamID, edm::Event &, const edm::EventSetup &) const override
void resize(size_t newsize, size_t wordsize=8)
Definition: FEDRawData.cc:28
std::pair< double, double > Position
void add(std::string const &label, ParameterSetDescription const &psetDescription)
static constexpr int ALLLAYERS
std::vector< WedgeCabling > RegionCabling
HLT enums.
char data[epos_bytes_allocation]
Definition: EPOS_Wrapper.h:80
const std::pair< double, double > regionDimensions() const
const unsigned char * data() const
Return a const pointer to the beginning of the data buffer.
Definition: FEDRawData.cc:24
std::vector< ElementCabling > WedgeCabling
const edm::ESGetToken< SiStripRegionCabling, SiStripRegionCablingRcd > tok_strip_
Power< A, B >::type pow(const A &a, const B &b)
Definition: Power.h:29
def move(src, dest)
Definition: eostools.py:511
static constexpr int ALLSUBDETS