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SiStripSpyDigiConverterModule.cc
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1 #include <string>
2 #include <memory>
3 #include <vector>
4 #include <utility>
5 
13 
19 
22 
32 namespace sistrip {
33 
35  public:
37  ~SpyDigiConverterModule() override;
38  void produce(edm::StreamID, edm::Event&, const edm::EventSetup&) const override;
39 
40  private:
43  const bool storeAPVAddress_;
47  const uint32_t expectedHeaderBit_;
48 
49  //utilities for cabling etc...
51  };
52 
53 } // namespace sistrip
54 
55 namespace sistrip {
56 
58  : productLabel_(pset.getParameter<edm::InputTag>("InputProductLabel")),
59  storeAPVAddress_(pset.getParameter<bool>("StoreAPVAddress")),
60  storePayloadDigis_(pset.getParameter<bool>("StorePayloadDigis")),
61  storeReorderedDigis_(pset.getParameter<bool>("StoreReorderedDigis")),
62  storeModuleDigis_(pset.getParameter<bool>("StoreModuleDigis")),
63  discardDigisWithAPVAddressError_(pset.getParameter<bool>("DiscardDigisWithWrongAPVAddress")),
64  expectedHeaderBit_(pset.getParameter<uint32_t>("ExpectedPositionOfFirstHeaderBit")) {
65  productToken_ = consumes<sistrip::SpyDigiConverter::DSVRawDigis>(productLabel_);
66  if (edm::isDebugEnabled()) {
67  LogTrace("SiStripSpyDigiConverter") << "[sistrip::SpyDigiConverterModule::" << __func__ << "]"
68  << " Constructing object...";
69  }
70  if (storeModuleDigis_) {
71  fedCablingToken_ = esConsumes<>();
72  }
73 
75  produces<edm::DetSetVector<SiStripRawDigi> >("SpyPayload");
77  produces<edm::DetSetVector<SiStripRawDigi> >("SpyReordered");
79  produces<edm::DetSetVector<SiStripRawDigi> >("SpyVirginRaw");
80 
81  if (storeAPVAddress_) {
82  produces<std::vector<uint32_t> >("APVAddress");
83  //produces<uint8_t>("APVAddress");
84  }
85 
86  frameQuality_.minDigiRange = static_cast<uint16_t>(pset.getParameter<uint32_t>("MinDigiRange"));
87  frameQuality_.maxDigiRange = static_cast<uint16_t>(pset.getParameter<uint32_t>("MaxDigiRange"));
88  frameQuality_.minZeroLight = static_cast<uint16_t>(pset.getParameter<uint32_t>("MinZeroLight"));
89  frameQuality_.maxZeroLight = static_cast<uint16_t>(pset.getParameter<uint32_t>("MaxZeroLight"));
90  frameQuality_.minTickHeight = static_cast<uint16_t>(pset.getParameter<uint32_t>("MinTickHeight"));
91  frameQuality_.maxTickHeight = static_cast<uint16_t>(pset.getParameter<uint32_t>("MaxTickHeight"));
92 
93  } // end of constructor.
94 
96  if (edm::isDebugEnabled()) {
97  LogTrace("SiStripSpyDigiConverter") << "[sistrip::SpyDigiConverterModule::" << __func__ << "]"
98  << " Destructing object...";
99  }
100  } // end of destructor.
101 
110  return;
111 
112  //retrieve the scope mode digis
114  event.getByToken(productToken_, scopeDigisHandle);
115 
116  //32-bit to accomodate known CMSSW container
117  std::unique_ptr<std::vector<uint32_t> > pAPVAddresses(new std::vector<uint32_t>);
118 
119  std::unique_ptr<sistrip::SpyDigiConverter::DSVRawDigis> payloadDigis, reorderedDigis, moduleDigis;
120 
121  //get the majority value for expected position of first header bit
122  //from first event, compare to expected one, else output warning.
123  auto run_once = [this](auto digis) {
124  uint16_t lFirstHeaderBit;
125  sistrip::SpyUtilities::getMajorityHeader(digis, lFirstHeaderBit);
126 
127  if (lFirstHeaderBit != static_cast<uint16_t>(expectedHeaderBit_)) {
128  edm::LogWarning("") << " -- Majority position for firstHeaderBit in first event (" << lFirstHeaderBit
129  << ") is not where expected: " << static_cast<uint16_t>(expectedHeaderBit_) << std::endl;
130  }
131  return false;
132  };
133 
134  [[maybe_unused]] static const bool lFirstEvent = run_once(scopeDigisHandle.product());
135 
136  //extract frame digis and APV addresses
137  payloadDigis = sistrip::SpyDigiConverter::extractPayloadDigis(scopeDigisHandle.product(),
138  pAPVAddresses.get(),
141  static_cast<uint16_t>(expectedHeaderBit_));
142 
143  // Reorder
145  reorderedDigis = sistrip::SpyDigiConverter::reorderDigis(payloadDigis.get());
146  }
147 
148  // Merge into modules
149  if (storeModuleDigis_) {
150  auto const& fedCabling = setup.getData(fedCablingToken_);
151  moduleDigis = sistrip::SpyDigiConverter::mergeModuleChannels(reorderedDigis.get(), fedCabling);
152  }
153 
154  //add to event
155  if (storePayloadDigis_)
156  event.put(std::move(payloadDigis), "SpyPayload");
158  event.put(std::move(reorderedDigis), "SpyReordered");
159  if (storeModuleDigis_)
160  event.put(std::move(moduleDigis), "SpyVirginRaw");
161  if (storeAPVAddress_) {
162  event.put(std::move(pAPVAddresses), "APVAddress");
163  }
164 
165  } // end of SpyDigiConverter::produce method.
166 
167 } // namespace sistrip
168 
170 #include <cstdint>
bool isDebugEnabled()
sistrip::SpyDigiConverterModule SiStripSpyDigiConverterModule
static std::unique_ptr< DSVRawDigis > reorderDigis(const DSVRawDigis *inputPayloadDigis)
edm::ESGetToken< SiStripFedCabling, SiStripFedCablingRcd > fedCablingToken_
T const * product() const
Definition: Handle.h:70
sistrip classes
#define LogTrace(id)
static std::unique_ptr< DSVRawDigis > extractPayloadDigis(const DSVRawDigis *inputScopeDigis, std::vector< uint32_t > *pAPVAddresses, const bool discardDigisWithAPVAddrErr, const sistrip::SpyUtilities::FrameQuality &aQuality, const uint16_t expectedPos)
Extract frames from the scope digis.
edm::EDGetTokenT< sistrip::SpyDigiConverter::DSVRawDigis > productToken_
void getMajorityHeader(const edm::DetSetVector< SiStripRawDigi > *aInputDigis, uint16_t &firstHeaderBit, bool printResult=true)
void produce(edm::StreamID, edm::Event &, const edm::EventSetup &) const override
#define DEFINE_FWK_MODULE(type)
Definition: MakerMacros.h:16
static std::unique_ptr< DSVRawDigis > mergeModuleChannels(const DSVRawDigis *inputPhysicalOrderChannelDigis, const SiStripFedCabling &cabling)
const bool storeAPVAddress_
True = store APVE address for each channel.
sistrip::SpyUtilities::FrameQuality frameQuality_
HLT enums.
Log< level::Warning, false > LogWarning
SpyDigiConverterModule(const edm::ParameterSet &)
def move(src, dest)
Definition: eostools.py:511
Definition: event.py:1
A plug-in module that takes the spy channel scope mode digis as input from the Event and creates EDPr...