Classes
struct	DetIdGPU

struct	Pixel

Functions
ALPAKA_FN_HOST_ACC ALPAKA_FN_INLINE constexpr uint32_t	pack (uint32_t row, uint32_t col, uint32_t adc, uint32_t flag=0)

ALPAKA_FN_HOST_ACC ALPAKA_FN_INLINE constexpr pixelchannelidentifierimpl::Packing	packing ()

constexpr uint32_t	pixelToChannel (int row, int col)

Variables
constexpr uint32_t	ADC_bits = 8

constexpr uint32_t	ADC_mask = ~(~uint32_t(0) << ADC_bits)

constexpr uint32_t	ADC_shift = 0

constexpr uint32_t	bladeMask = 0x3F

constexpr uint32_t	bladeStartBit = 12

constexpr uint32_t	COL_bits_l1 = 6

constexpr uint32_t	COL_mask = ~(~uint32_t(0) << COL_bits_l1)

constexpr uint32_t	COL_shift = ROW_shift + ROW_bits_l1

constexpr uint32_t	DCOL_bits = 5

constexpr uint32_t	DCOL_mask = ~(~uint32_t(0) << DCOL_bits)

constexpr uint32_t	DCOL_shift = PXID_shift + PXID_bits

constexpr uint32_t	diskMask = 0xF

constexpr uint32_t	diskStartBit = 18

constexpr uint32_t	ERROR_mask = ~(~uint32_t(0) << ROC_bits_l1)

constexpr uint32_t	ladderMask = 0xFF

constexpr uint32_t	ladderStartBit = 12

constexpr uint32_t	layerMask = 0xF

constexpr uint32_t	layerStartBit = 20

constexpr uint32_t	LINK_bits = 6

constexpr uint32_t	LINK_bits_l1 = 6

constexpr uint32_t	LINK_mask = ~(~uint32_t(0) << LINK_bits_l1)

constexpr uint32_t	LINK_shift = ROC_shift + ROC_bits_l1

constexpr auto	MAX_LINK = pixelgpudetails::MAX_LINK

constexpr auto	MAX_ROC = pixelgpudetails::MAX_ROC

constexpr auto	MAX_SIZE = pixelgpudetails::MAX_SIZE

constexpr uint32_t	MAX_WORD = 2000

constexpr uint32_t	maxROCIndex = 8

constexpr uint32_t	moduleMask = 0x3FF

constexpr uint32_t	moduleStartBit = 2

constexpr uint32_t	numColsInRoc = 52

constexpr uint32_t	numRowsInRoc = 80

constexpr uint32_t	OMIT_ERR_bits = 1

constexpr uint32_t	OMIT_ERR_mask = ~(~uint32_t(0) << OMIT_ERR_bits)

constexpr uint32_t	OMIT_ERR_shift = 20

constexpr uint32_t	panelMask = 0x3

constexpr uint32_t	panelStartBit = 10

constexpr uint32_t	PXID_bits = 8

constexpr uint32_t	PXID_mask = ~(~uint32_t(0) << PXID_bits)

constexpr uint32_t	PXID_shift = ADC_shift + ADC_bits

constexpr uint32_t	ROC_bits = 5

constexpr uint32_t	ROC_bits_l1 = 5

constexpr uint32_t	ROC_mask = ~(~uint32_t(0) << ROC_bits_l1)

constexpr uint32_t	ROC_shift = DCOL_shift + DCOL_bits

constexpr uint32_t	ROW_bits_l1 = 7

constexpr uint32_t	ROW_mask = ~(~uint32_t(0) << ROW_bits_l1)

constexpr uint32_t	ROW_shift = ADC_shift + ADC_bits

Function Documentation

◆ pack()

ALPAKA_FN_HOST_ACC ALPAKA_FN_INLINE constexpr uint32_t pixelDetails::pack	(	uint32_t	row,
		uint32_t	col,
		uint32_t	adc,
		uint32_t	flag = `0`
	)

Definition at line 103 of file SiPixelRawToClusterKernel.h.

References gpuClustering::adc, cuy::col, ALPAKA_ACCELERATOR_NAMESPACE::brokenline::constexpr(), SiStripPI::min, and packing().

                                                                                  {
     constexpr pixelchannelidentifierimpl::Packing thePacking = packing();
     adc = std::min(adc, uint32_t(thePacking.max_adc));
 
     return (row << thePacking.row_shift) | (col << thePacking.column_shift) | (adc << thePacking.adc_shift);
   }

◆ packing()

ALPAKA_FN_HOST_ACC ALPAKA_FN_INLINE constexpr pixelchannelidentifierimpl::Packing pixelDetails::packing ( )

Definition at line 99 of file SiPixelRawToClusterKernel.h.

References PixelChannelIdentifier::thePacking.

Referenced by pack(), and pixelToChannel().

                                                                                             {
     return PixelChannelIdentifier::thePacking;
   }

◆ pixelToChannel()

constexpr uint32_t pixelDetails::pixelToChannel	(	int	row,
		int	col
	)

Definition at line 113 of file SiPixelRawToClusterKernel.h.

References cuy::col, ALPAKA_ACCELERATOR_NAMESPACE::brokenline::constexpr(), and packing().

Referenced by Pixel3DDigitizerAlgorithm::induce_signal().

                                                       {
     constexpr pixelchannelidentifierimpl::Packing thePacking = packing();
     return (row << thePacking.column_width) | col;
   }