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SiStripFecCabling Class Reference

#include <SiStripFecCabling.h>

Public Member Functions

void addDevices (const FedChannelConnection &conn)
 
void buildFecCabling (const SiStripFedCabling &)
 
void connections (std::vector< FedChannelConnection > &) const
 
NumberOfDevices countDevices () const
 
const std::vector< SiStripFecCrate > & crates () const
 
std::vector< SiStripFecCrate > & crates ()
 
void dcuId (const FedChannelConnection &conn)
 
void detId (const FedChannelConnection &conn)
 
const std::vector< SiStripFec > & fecs () const
 
const SiStripModulemodule (const FedChannelConnection &conn) const
 
SiStripModulemodule (const FedChannelConnection &conn)
 
const SiStripModulemodule (const uint32_t &dcu_id) const
 
void nApvPairs (const FedChannelConnection &conn)
 
void print (std::stringstream &) const
 
 SiStripFecCabling (const SiStripFedCabling &)
 
 SiStripFecCabling ()
 
void terse (std::stringstream &) const
 
 ~SiStripFecCabling ()
 

Private Attributes

std::vector< SiStripFecCratecrates_
 

Detailed Description

Definition at line 24 of file SiStripFecCabling.h.

Constructor & Destructor Documentation

◆ SiStripFecCabling() [1/2]

SiStripFecCabling::SiStripFecCabling ( const SiStripFedCabling fed_cabling)

Definition at line 13 of file SiStripFecCabling.cc.

References buildFecCabling(), crates_, LogTrace, and sistrip::mlCabling_.

13  : crates_() {
14  LogTrace(mlCabling_) << "[SiStripFecCabling::" << __func__ << "]"
15  << " Constructing object...";
16  crates_.reserve(4);
17  buildFecCabling(fed_cabling);
18 }
std::vector< SiStripFecCrate > crates_
#define LogTrace(id)
static const char mlCabling_[]
void buildFecCabling(const SiStripFedCabling &)

◆ SiStripFecCabling() [2/2]

SiStripFecCabling::SiStripFecCabling ( )
inline

Definition at line 31 of file SiStripFecCabling.h.

31 { ; }

◆ ~SiStripFecCabling()

SiStripFecCabling::~SiStripFecCabling ( )
inline

Definition at line 33 of file SiStripFecCabling.h.

33 { ; } //@@ needs implementation!!

Member Function Documentation

◆ addDevices()

void SiStripFecCabling::addDevices ( const FedChannelConnection conn)

Definition at line 61 of file SiStripFecCabling.cc.

References getInfo::conn, and crates_.

Referenced by buildFecCabling(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDetIds(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices(), SiStripFedCablingBuilderFromDb::buildFecCablingFromFedConnections(), and SiStripFedCablingFakeESSource::make().

61  {
62  auto icrate = crates_.begin();
63  while (icrate != crates_.end() && (*icrate).fecCrate() != conn.fecCrate()) {
64  icrate++;
65  }
66  if (icrate == crates_.end()) {
67  crates_.push_back(SiStripFecCrate(conn));
68  } else {
69  icrate->addDevices(conn);
70  }
71 }
std::vector< SiStripFecCrate > crates_
conn
Definition: getInfo.py:9

◆ buildFecCabling()

void SiStripFecCabling::buildFecCabling ( const SiStripFedCabling fed_cabling)

Definition at line 22 of file SiStripFecCabling.cc.

References addDevices(), crates(), SiStripFedCabling::fedConnections(), SiStripFedCabling::fedIds(), l1tstage2emulator_dqm_sourceclient-live_cfg::feds, sistrip::invalid_, LogTrace, and sistrip::mlCabling_.

Referenced by SiStripFedCablingBuilderFromDb::getFecCabling(), and SiStripFecCabling().

22  {
23  LogTrace(mlCabling_) << "[SiStripFecCabling::" << __func__ << "]"
24  << " Building FEC cabling...";
25 
26  // Retrieve and iterate through FED ids
27  auto feds = fed_cabling.fedIds();
28  for (auto ifed = feds.begin(); ifed != feds.end(); ifed++) {
29  // Retrieve and iterate through FED channel connections
30  auto conns = fed_cabling.fedConnections(*ifed);
31  for (auto iconn = conns.begin(); iconn != conns.end(); iconn++) {
32  // Check that FED id is not invalid and add devices
33  if (iconn->fedId() != sistrip::invalid_) {
34  addDevices(*iconn);
35  }
36  }
37  }
38 
39  // Consistency checks
40  for (std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end();
41  ++icrate) {
42  for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
43  for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
44  ++iring) {
45  for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
46  ++iccu) {
47  for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
48  ++imod) {
49  //@@ need consistency checks here!
50  }
51  }
52  }
53  }
54  }
55  LogTrace(mlCabling_) << "[SiStripFecCabling::" << __func__ << "]"
56  << " Finished building FEC cabling";
57 }
void addDevices(const FedChannelConnection &conn)
#define LogTrace(id)
static const char mlCabling_[]
const std::vector< SiStripFecCrate > & crates() const
static const uint16_t invalid_
Definition: Constants.h:16
FedsConstIterRange fedIds() const
ConnsConstIterRange fedConnections(uint16_t fed_id) const

◆ connections()

void SiStripFecCabling::connections ( std::vector< FedChannelConnection > &  conns) const

Definition at line 75 of file SiStripFecCabling.cc.

References crates(), dqmdumpme::first, LogTrace, sistrip::mlCabling_, and edm::second().

Referenced by SiStripFedCablingBuilderFromDb::getFedCabling(), and SiStripFedCablingFakeESSource::make().

75  {
76  LogTrace(mlCabling_) << "[SiStripFecCabling::" << __func__ << "]"
77  << " Building vector of FedChannelConnection objects...";
78  conns.clear();
79  for (std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end();
80  ++icrate) {
81  for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
82  for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
83  ++iring) {
84  for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
85  ++iccu) {
86  for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
87  ++imod) {
88  for (uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++) {
89  conns.push_back(FedChannelConnection(icrate->fecCrate(),
90  ifec->fecSlot(),
91  iring->fecRing(),
92  iccu->ccuAddr(),
93  imod->ccuChan(),
94  imod->activeApvPair(imod->lldChannel(ipair)).first,
95  imod->activeApvPair(imod->lldChannel(ipair)).second,
96  imod->dcuId(),
97  imod->detId(),
98  imod->nApvPairs(),
99  imod->fedCh(ipair).fedId_,
100  imod->fedCh(ipair).fedCh_,
101  imod->length(),
102  imod->dcu(),
103  imod->pll(),
104  imod->mux(),
105  imod->lld()));
106  uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
107  uint16_t fed_slot = imod->fedCh(ipair).fedSlot_;
108  conns.back().fedCrate(fed_crate);
109  conns.back().fedSlot(fed_slot);
110  }
111  }
112  }
113  }
114  }
115  }
116 }
#define LogTrace(id)
U second(std::pair< T, U > const &p)
static const char mlCabling_[]
Class containning control, module, detector and connection information, at the level of a FED channel...
const std::vector< SiStripFecCrate > & crates() const

◆ countDevices()

NumberOfDevices SiStripFecCabling::countDevices ( ) const

Definition at line 219 of file SiStripFecCabling.cc.

References crates(), spr::find(), NumberOfDevices::nApvPairs0_, NumberOfDevices::nApvPairs1_, NumberOfDevices::nApvPairs2_, NumberOfDevices::nApvPairs3_, NumberOfDevices::nApvPairs_, NumberOfDevices::nApvPairsX_, NumberOfDevices::nApvs_, NumberOfDevices::nCcuAddrs_, NumberOfDevices::nCcuChans_, NumberOfDevices::nDcuIds_, NumberOfDevices::nDcus_, NumberOfDevices::nDetIds_, NumberOfDevices::nFecCrates_, NumberOfDevices::nFecRings_, NumberOfDevices::nFecSlots_, NumberOfDevices::nFedChans_, NumberOfDevices::nFedCrates_, NumberOfDevices::nFedIds_, NumberOfDevices::nFedSlots_, NumberOfDevices::nLlds_, NumberOfDevices::nMuxes_, and NumberOfDevices::nPlls_.

Referenced by SiStripFedCablingBuilderFromDb::buildFecCabling(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices(), and SiStripFedCablingFakeESSource::make().

219  {
220  NumberOfDevices num_of_devices; // simple container class used for counting
221 
222  std::vector<uint16_t> fed_crates;
223  std::vector<uint16_t> fed_slots;
224  std::vector<uint16_t> fed_ids;
225  for (std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end();
226  ++icrate) {
227  for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
228  for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
229  ++iring) {
230  for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
231  ++iccu) {
232  for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
233  ++imod) {
234  // APVs
235  if (imod->activeApv(32)) {
236  num_of_devices.nApvs_++;
237  }
238  if (imod->activeApv(33)) {
239  num_of_devices.nApvs_++;
240  }
241  if (imod->activeApv(34)) {
242  num_of_devices.nApvs_++;
243  }
244  if (imod->activeApv(35)) {
245  num_of_devices.nApvs_++;
246  }
247  if (imod->activeApv(36)) {
248  num_of_devices.nApvs_++;
249  }
250  if (imod->activeApv(37)) {
251  num_of_devices.nApvs_++;
252  }
253  if (imod->dcuId()) {
254  num_of_devices.nDcuIds_++;
255  }
256  if (imod->detId()) {
257  num_of_devices.nDetIds_++;
258  }
259 
260  // APV pairs
261  num_of_devices.nApvPairs_ += imod->nApvPairs();
262  if (imod->nApvPairs() == 0) {
263  num_of_devices.nApvPairs0_++;
264  } else if (imod->nApvPairs() == 1) {
265  num_of_devices.nApvPairs1_++;
266  } else if (imod->nApvPairs() == 2) {
267  num_of_devices.nApvPairs2_++;
268  } else if (imod->nApvPairs() == 3) {
269  num_of_devices.nApvPairs3_++;
270  } else {
271  num_of_devices.nApvPairsX_++;
272  }
273 
274  // FED crates, slots, ids, channels
275  for (uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++) {
276  uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
277  uint16_t fed_slot = imod->fedCh(ipair).fedSlot_;
278  uint16_t fed_id = imod->fedCh(ipair).fedId_;
279 
280  if (fed_id) {
281  num_of_devices.nFedChans_++;
282 
283  std::vector<uint16_t>::iterator icrate = find(fed_crates.begin(), fed_crates.end(), fed_crate);
284  if (icrate == fed_crates.end()) {
285  num_of_devices.nFedCrates_++;
286  fed_crates.push_back(fed_crate);
287  }
288 
289  std::vector<uint16_t>::iterator islot = find(fed_slots.begin(), fed_slots.end(), fed_slot);
290  if (islot == fed_slots.end()) {
291  num_of_devices.nFedSlots_++;
292  fed_slots.push_back(fed_slot);
293  }
294 
295  std::vector<uint16_t>::iterator ifed = find(fed_ids.begin(), fed_ids.end(), fed_id);
296  if (ifed == fed_ids.end()) {
297  num_of_devices.nFedIds_++;
298  fed_ids.push_back(fed_id);
299  }
300  }
301  }
302 
303  // FE devices
304  if (imod->dcu()) {
305  num_of_devices.nDcus_++;
306  }
307  if (imod->mux()) {
308  num_of_devices.nMuxes_++;
309  }
310  if (imod->pll()) {
311  num_of_devices.nPlls_++;
312  }
313  if (imod->lld()) {
314  num_of_devices.nLlds_++;
315  }
316 
317  // FE modules
318  num_of_devices.nCcuChans_++;
319  }
320  num_of_devices.nCcuAddrs_++;
321  }
322  num_of_devices.nFecRings_++;
323  }
324  num_of_devices.nFecSlots_++;
325  }
326  num_of_devices.nFecCrates_++;
327  }
328 
329  return num_of_devices;
330 }
uint32_t nFecCrates_
void find(edm::Handle< EcalRecHitCollection > &hits, DetId thisDet, std::vector< EcalRecHitCollection::const_iterator > &hit, bool debug=false)
Definition: FindCaloHit.cc:19
uint32_t nApvPairs3_
const std::vector< SiStripFecCrate > & crates() const
uint32_t nApvPairsX_
uint32_t nApvPairs0_
Simple container class for counting devices.
uint32_t nApvPairs2_
uint32_t nApvPairs1_
uint32_t nFedCrates_

◆ crates() [1/2]

const std::vector< SiStripFecCrate > & SiStripFecCabling::crates ( ) const
inline

◆ crates() [2/2]

std::vector< SiStripFecCrate > & SiStripFecCabling::crates ( )
inline

Definition at line 77 of file SiStripFecCabling.h.

References crates_.

77 { return crates_; }
std::vector< SiStripFecCrate > crates_

◆ dcuId()

void SiStripFecCabling::dcuId ( const FedChannelConnection conn)
inline

Definition at line 89 of file SiStripFecCabling.h.

References getInfo::conn, visualization-live-secondInstance_cfg::m, and module().

Referenced by SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices().

89  {
90  auto m = module(conn);
91  if (m) {
92  m->dcuId(conn.dcuId());
93  }
94 }
const SiStripModule & module(const FedChannelConnection &conn) const
conn
Definition: getInfo.py:9

◆ detId()

void SiStripFecCabling::detId ( const FedChannelConnection conn)
inline

Definition at line 96 of file SiStripFecCabling.h.

References getInfo::conn, visualization-live-secondInstance_cfg::m, and module().

96  {
97  auto m = module(conn);
98  if (m) {
99  m->detId(conn.detId());
100  }
101 }
const SiStripModule & module(const FedChannelConnection &conn) const
conn
Definition: getInfo.py:9

◆ fecs()

const std::vector< SiStripFec > & SiStripFecCabling::fecs ( ) const
inline

Definition at line 80 of file SiStripFecCabling.h.

References crates_.

80  {
81  const static std::vector<SiStripFec> my_fecs;
82  if (!crates_.empty()) {
83  return crates_[0].fecs();
84  } else {
85  return my_fecs;
86  }
87 }
std::vector< SiStripFecCrate > crates_

◆ module() [1/3]

const SiStripModule & SiStripFecCabling::module ( const FedChannelConnection conn) const

Definition at line 181 of file SiStripFecCabling.cc.

References getInfo::conn, and crates().

Referenced by dcuId(), detId(), SiStripCommissioningSource::fillCablingHistos(), module(), and nApvPairs().

181  {
182  auto module = moduleFrom(crates(), conn);
183  if (module) {
184  return *module;
185  }
186 
187  static const SiStripModule s_module{FedChannelConnection{}};
188  return s_module;
189 }
Device and connection information at the level of a front-end module.
Definition: SiStripModule.h:24
const SiStripModule & module(const FedChannelConnection &conn) const
Class containning control, module, detector and connection information, at the level of a FED channel...
const std::vector< SiStripFecCrate > & crates() const
conn
Definition: getInfo.py:9

◆ module() [2/3]

SiStripModule * SiStripFecCabling::module ( const FedChannelConnection conn)

Definition at line 191 of file SiStripFecCabling.cc.

References getInfo::conn, and crates().

191 { return moduleFrom(crates(), conn); }
const std::vector< SiStripFecCrate > & crates() const
conn
Definition: getInfo.py:9

◆ module() [3/3]

const SiStripModule & SiStripFecCabling::module ( const uint32_t &  dcu_id) const

Definition at line 195 of file SiStripFecCabling.cc.

References crates(), and module().

195  {
196  for (std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end();
197  ++icrate) {
198  for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
199  for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
200  ++iring) {
201  for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
202  ++iccu) {
203  for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
204  ++imod) {
205  if ((*imod).dcuId() == dcu_id) {
206  return *imod;
207  }
208  }
209  }
210  }
211  }
212  }
213  static const SiStripModule module{FedChannelConnection{}};
214  return module;
215 }
Device and connection information at the level of a front-end module.
Definition: SiStripModule.h:24
const SiStripModule & module(const FedChannelConnection &conn) const
Class containning control, module, detector and connection information, at the level of a FED channel...
const std::vector< SiStripFecCrate > & crates() const

◆ nApvPairs()

void SiStripFecCabling::nApvPairs ( const FedChannelConnection conn)
inline

Definition at line 103 of file SiStripFecCabling.h.

References getInfo::conn, visualization-live-secondInstance_cfg::m, and module().

103  {
104  auto m = module(conn);
105  if (m) {
106  m->nApvPairs(conn.nApvPairs());
107  }
108 }
const SiStripModule & module(const FedChannelConnection &conn) const
conn
Definition: getInfo.py:9

◆ print()

void SiStripFecCabling::print ( std::stringstream &  ss) const

Definition at line 334 of file SiStripFecCabling.cc.

References crates(), cuy::ii, sistrip::invalid_, findQualityFiles::jj, contentValuesCheck::ss, dqmMemoryStats::total, and validateGeometry_cfg::valid.

Referenced by SiStripFedCablingReader::beginRun(), and operator<<().

334  {
335  uint32_t valid = 0;
336  uint32_t total = 0;
337  ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
338  ss << "Printing cabling for " << crates().size() << " crates" << std::endl;
339  for (std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); ++icrate) {
340  ss << "Printing cabling for " << icrate->fecs().size() << " FECs for crate " << icrate->fecCrate() << std::endl;
341  for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
342  ss << "Printing cabling for " << ifec->rings().size() << " rings for FEC " << ifec->fecSlot() << std::endl;
343  for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
344  ++iring) {
345  ss << "Printing cabling for " << iring->ccus().size() << " CCUs for ring " << iring->fecRing() << std::endl;
346  for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
347  ++iccu) {
348  ss << "Printing cabling for " << iccu->modules().size() << " modules for CCU " << iccu->ccuAddr()
349  << std::endl;
350  for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
351  ++imod) {
352  SiStripModule::FedCabling conns = imod->fedChannels();
353  SiStripModule::FedCabling::const_iterator ii = conns.begin();
354  SiStripModule::FedCabling::const_iterator jj = conns.end();
355  for (; ii != jj; ++ii) {
356  if (ii->second.fedId_ != sistrip::invalid_ && ii->second.fedCh_ != sistrip::invalid_) {
357  valid++;
358  }
359  total++;
360  }
361  ss << *imod << std::endl;
362  }
363  }
364  }
365  }
366  }
367  ss << "Number of connected: " << valid << std::endl << "Number of connections: " << total << std::endl;
368 }
std::map< uint16_t, FedChannel > FedCabling
Definition: SiStripModule.h:58
const std::vector< SiStripFecCrate > & crates() const
ii
Definition: cuy.py:589
static const uint16_t invalid_
Definition: Constants.h:16

◆ terse()

void SiStripFecCabling::terse ( std::stringstream &  ss) const

Definition at line 372 of file SiStripFecCabling.cc.

References crates(), and contentValuesCheck::ss.

372  {
373  ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
374  for (std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); ++icrate) {
375  for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
376  for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
377  ++iring) {
378  for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
379  ++iccu) {
380  for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
381  ++imod) {
382  imod->terse(ss);
383  ss << std::endl;
384  }
385  }
386  }
387  }
388  }
389 }
const std::vector< SiStripFecCrate > & crates() const

Member Data Documentation

◆ crates_

std::vector<SiStripFecCrate> SiStripFecCabling::crates_
private

Definition at line 71 of file SiStripFecCabling.h.

Referenced by addDevices(), crates(), fecs(), and SiStripFecCabling().