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SiStripFedCablingFakeESSource.cc
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11 #include <sstream>
12 #include <vector>
13 #include <map>
14 
15 using namespace sistrip;
16 
17 // -----------------------------------------------------------------------------
18 //
20  : SiStripFedCablingESProducer(pset), fedIds_(pset.getParameter<edm::FileInPath>("FedIdsFile")), pset_(pset) {
21  findingRecord<SiStripFedCablingRcd>();
22  m_detInfo = SiStripDetInfoFileReader::read(pset.getParameter<edm::FileInPath>("SiStripDetInfoFile").fullPath());
23  edm::LogVerbatim("FedCabling") << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
24  << " Constructing object...";
25 }
26 
27 // -----------------------------------------------------------------------------
28 //
30  edm::LogVerbatim("FedCabling") << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
31  << " Destructing object...";
32 }
33 
34 // -----------------------------------------------------------------------------
35 //
37  edm::LogVerbatim("FedCabling") << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
38  << " Building \"fake\" FED cabling map"
39  << " from real DetIds and FedIds (read from ascii file)";
40 
41  // Create FEC cabling object
42  SiStripFecCabling* fec_cabling = new SiStripFecCabling();
43 
44  // Read DetId list from file
45  typedef std::vector<uint32_t> Dets;
46  Dets dets = m_detInfo.getAllDetIds();
47 
48  // Read FedId list from file
49  typedef std::vector<uint16_t> Feds;
51 
52  bool populateAllFeds = pset_.getParameter<bool>("PopulateAllFeds");
53 
54  // Iterator through DetInfo objects and populate FEC cabling object
55  uint32_t imodule = 0;
56  Dets::const_iterator idet = dets.begin();
57  Dets::const_iterator jdet = dets.end();
58  for (; idet != jdet; ++idet) {
59  uint16_t npairs = m_detInfo.getNumberOfApvsAndStripLength(*idet).first / 2;
60  for (uint16_t ipair = 0; ipair < npairs; ++ipair) {
61  uint16_t addr = 0;
62  if (npairs == 2 && ipair == 0) {
63  addr = 32;
64  } else if (npairs == 2 && ipair == 1) {
65  addr = 36;
66  } else if (npairs == 3 && ipair == 0) {
67  addr = 32;
68  } else if (npairs == 3 && ipair == 1) {
69  addr = 34;
70  } else if (npairs == 3 && ipair == 2) {
71  addr = 36;
72  } else {
73  edm::LogWarning("FedCabling") << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
74  << " Inconsistent values for nPairs (" << npairs << ") and ipair (" << ipair
75  << ")!";
76  }
77  uint32_t module_key =
78  SiStripFecKey(fecCrate(imodule), fecSlot(imodule), fecRing(imodule), ccuAddr(imodule), ccuChan(imodule)).key();
80  fecSlot(imodule),
81  fecRing(imodule),
82  ccuAddr(imodule),
83  ccuChan(imodule),
84  addr,
85  addr + 1, // apv i2c addresses
86  module_key, // dcu id
87  *idet, // det id
88  npairs); // apv pairs
89  fec_cabling->addDevices(conn);
90  }
91  imodule++;
92  }
93 
94  // Assign "dummy" FED ids/chans
95  bool insufficient = false;
96  Feds::const_iterator ifed = feds.begin();
97  uint16_t fed_ch = 0;
98  for (std::vector<SiStripFecCrate>::const_iterator icrate = fec_cabling->crates().begin();
99  icrate != fec_cabling->crates().end();
100  icrate++) {
101  for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++) {
102  for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
103  iring++) {
104  for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
105  iccu++) {
106  for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
107  imod++) {
108  if (populateAllFeds) {
109  for (uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++) {
110  if (ifed == feds.end()) {
111  fed_ch++;
112  ifed = feds.begin();
113  }
114  if (fed_ch == 96) {
115  insufficient = true;
116  break;
117  }
118 
119  std::pair<uint16_t, uint16_t> addr = imod->activeApvPair(imod->lldChannel(ipair));
120  SiStripModule::FedChannel fed_channel((*ifed) / 16 + 1, // 16 FEDs per crate, numbering starts from 1
121  (*ifed) % 16 + 2, // FED slot starts from 2
122  *ifed,
123  fed_ch);
124  const_cast<SiStripModule&>(*imod).fedCh(addr.first, fed_channel);
125  ifed++;
126  }
127  } else {
128  // Patch introduced by D.Giordano 2/12/08
129  //to reproduce the fake cabling used in 2x
130  //that was designed to fill each fed iteratively
131  //filling all channels of a fed before going to the next one
132  if (96 - fed_ch < imod->nApvPairs()) {
133  ifed++;
134  fed_ch = 0;
135  } // move to next FED
136  for (uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++) {
137  std::pair<uint16_t, uint16_t> addr = imod->activeApvPair((*imod).lldChannel(ipair));
138  SiStripModule::FedChannel fed_channel((*ifed) / 16 + 1, // 16 FEDs per crate, numbering starts from 1
139  (*ifed) % 16 + 2, // FED slot starts from 2
140  (*ifed),
141  fed_ch);
142  const_cast<SiStripModule&>(*imod).fedCh(addr.first, fed_channel);
143  fed_ch++;
144  }
145  }
146  }
147  }
148  }
149  }
150  }
151 
152  if (insufficient) {
153  edm::LogWarning(mlCabling_) << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
154  << " Insufficient FED channels to cable entire system!";
155  }
156 
157  // Some debug
158  std::stringstream ss;
159  ss << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
160  << " First count devices of FEC cabling " << std::endl;
161  fec_cabling->countDevices().print(ss);
162  LogTrace(mlCabling_) << ss.str();
163 
164  // Build FED cabling using FedChannelConnections
165  std::vector<FedChannelConnection> conns;
166  fec_cabling->connections(conns);
167  SiStripFedCabling* cabling = new SiStripFedCabling(conns);
168 
169  return cabling;
170 }
171 
172 // -----------------------------------------------------------------------------
173 //
175  const edm::IOVSyncValue& iov_sync,
176  edm::ValidityInterval& iov_validity) {
177  edm::ValidityInterval infinity(iov_sync.beginOfTime(), iov_sync.endOfTime());
178  iov_validity = infinity;
179 }
Log< level::Info, true > LogVerbatim
Device and connection information at the level of a front-end module.
Definition: SiStripModule.h:24
static uint16_t ccuAddr(const uint16_t &nth_module)
T getParameter(std::string const &) const
Definition: ParameterSet.h:307
static uint16_t fecCrate(const uint16_t &nth_module)
std::string fullPath() const
Definition: FileInPath.cc:161
for(int i=first, nt=offsets[nh];i< nt;i+=gridDim.x *blockDim.x)
void addDevices(const FedChannelConnection &conn)
NumberOfDevices countDevices() const
static const IOVSyncValue & endOfTime()
Definition: IOVSyncValue.cc:82
static uint16_t fecSlot(const uint16_t &nth_module)
static uint16_t fecRing(const uint16_t &nth_module)
sistrip classes
#define LogTrace(id)
Utility class that identifies a position within the strip tracker control structure, down to the level of an APV25.
Definition: SiStripFecKey.h:45
static const char mlCabling_[]
static const IOVSyncValue & beginOfTime()
Definition: IOVSyncValue.cc:88
Class containning control, module, detector and connection information, at the level of a FED channel...
void print(std::stringstream &) const
const uint32_t & key() const
Definition: SiStripKey.h:120
const double infinity
FedChannel fedCh(const uint16_t &apv_pair_num) const
Abstract base class for producer of SiStripFedCabling record.
void connections(std::vector< FedChannelConnection > &) const
SiStripDetInfo read(std::string filePath)
const std::vector< SiStripFecCrate > & crates() const
SiStripFedCablingFakeESSource(const edm::ParameterSet &)
static uint16_t ccuChan(const uint16_t &nth_module)
const std::pair< unsigned short, double > getNumberOfApvsAndStripLength(uint32_t detId) const
Contains cabling info at the device level, including DetId, APV pair numbers, hardware addresses...
SiStripFedCabling * make(const SiStripFedCablingRcd &) override
HLT enums.
conn
Definition: getInfo.py:9
Log< level::Warning, false > LogWarning
const std::vector< uint32_t > & getAllDetIds() const noexcept
void setIntervalFor(const edm::eventsetup::EventSetupRecordKey &, const edm::IOVSyncValue &, edm::ValidityInterval &) override