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parameters.cc File Reference
#include "parameters.h"
#include "CondFormats/L1TObjects/interface/L1MuCSCTFConfiguration.h"
#include "FWCore/ParameterSet/interface/ParameterSet.h"
#include "FWCore/MessageLogger/interface/MessageLogger.h"
#include <sstream>

Go to the source code of this file.

Functions

edm::ParameterSet parameters (L1MuCSCTFConfiguration const &iConfig, int sp)
 

Function Documentation

◆ parameters()

edm::ParameterSet parameters ( L1MuCSCTFConfiguration const &  iConfig,
int  sp 
)

Definition at line 23 of file parameters.cc.

References csctfTrackDigis_cfi::AllowALCTonly, csctfTrackDigis_cfi::AllowCLCTonly, csctfTrackDigis_cfi::BXAdepth, csctfTrackDigis_cfi::CoreLatency, csctfTrackDigis_cfi::curvedp, muonTiming_cfi::etamax, muonTiming_cfi::etamin, csctfTrackDigis_cfi::firmwareDD, csctfTrackDigis_cfi::firmwareFA, csctfTrackDigis_cfi::firmwareSP, csctfTrackDigis_cfi::firmwareVM, createfilelist::int, csctfTrackDigis_cfi::kill_fiber, mps_splice::line, LogDebug, csctfTrackDigis_cfi::maxdeta112_accp, csctfTrackDigis_cfi::maxdeta113_accp, csctfTrackDigis_cfi::maxdeta12_accp, csctfTrackDigis_cfi::maxdeta13_accp, csctfTrackDigis_cfi::maxdphi112_accp, csctfTrackDigis_cfi::maxdphi113_accp, csctfTrackDigis_cfi::maxdphi12_accp, csctfTrackDigis_cfi::maxdphi13_accp, csctfTrackDigis_cfi::mbaPhiOff, csctfTrackDigis_cfi::mbbPhiOff, csctfTrackDigis_cfi::mindeta112_accp, csctfTrackDigis_cfi::mindeta113_accp, csctfTrackDigis_cfi::mindeta12_accp, csctfTrackDigis_cfi::mindeta13_accp, csctfTrackDigis_cfi::mindetap, csctfTrackDigis_cfi::mindetap_halo, csctfTrackDigis_cfi::mindphip, csctfTrackDigis_cfi::mindphip_halo, csctfTrackDigis_cfi::PreTrigger, muonDTDigis_cfi::pset, csctfTrackDigis_cfi::QualityEnableME1a, csctfTrackDigis_cfi::QualityEnableME1b, csctfTrackDigis_cfi::QualityEnableME1c, csctfTrackDigis_cfi::QualityEnableME1d, csctfTrackDigis_cfi::QualityEnableME1e, csctfTrackDigis_cfi::QualityEnableME1f, csctfTrackDigis_cfi::QualityEnableME2a, csctfTrackDigis_cfi::QualityEnableME2b, csctfTrackDigis_cfi::QualityEnableME2c, csctfTrackDigis_cfi::QualityEnableME3a, csctfTrackDigis_cfi::QualityEnableME3b, csctfTrackDigis_cfi::QualityEnableME3c, csctfTrackDigis_cfi::QualityEnableME4a, csctfTrackDigis_cfi::QualityEnableME4b, csctfTrackDigis_cfi::QualityEnableME4c, csctfTrackDigis_cfi::rescaleSinglesPhi, csctfTrackDigis_cfi::run_core, csctfTrackDigis_cfi::singlesTrackOutput, csctfTrackDigis_cfi::straightp, AlCaHLTBitMon_QueryRunRegistry::string, csctfTrackDigis_cfi::trigger_on_MB1a, csctfTrackDigis_cfi::trigger_on_MB1d, csctfTrackDigis_cfi::trigger_on_ME1a, csctfTrackDigis_cfi::trigger_on_ME1b, csctfTrackDigis_cfi::trigger_on_ME2, csctfTrackDigis_cfi::trigger_on_ME3, csctfTrackDigis_cfi::trigger_on_ME4, csctfTrackDigis_cfi::useDT, relativeConstraints::value, and csctfTrackDigis_cfi::widePhi.

23  {
24  LogDebug("L1MuCSCTFConfiguration") << "SP:" << int(sp) << std::endl;
25 
26  edm::ParameterSet pset;
27  if (sp >= 12)
28  return pset;
29 
30  // ------------------------------------------------------
31  // core configuration
32  // by default everything is disabled: we need to set them
33  // coincidence and singles
34  bool run_core = false;
35  bool trigger_on_ME1a = false;
36  bool trigger_on_ME1b = false;
37  bool trigger_on_ME2 = false;
38  bool trigger_on_ME3 = false;
39  bool trigger_on_ME4 = false;
40  bool trigger_on_MB1a = false;
41  bool trigger_on_MB1d = false;
42 
43  unsigned int BXAdepth = 0;
44  unsigned int useDT = 0;
45  unsigned int widePhi = 0;
46  unsigned int PreTrigger = 0;
47  // ------------------------------------------------------
48 
49  // ------------------------------------------------------
50  // these are very important parameters.
51  // Double check with Alex
52  unsigned int CoreLatency = 7;
53  bool rescaleSinglesPhi = true;
54 
55  // ask Alex if use or remove them or what
56  bool AllowALCTonly = false;
57  bool AllowCLCTonly = false;
58 
59  // other useful parameters in general not set in the OMDS
60  unsigned int QualityEnableME1a = 0xFFFF;
61  unsigned int QualityEnableME1b = 0xFFFF;
62  unsigned int QualityEnableME1c = 0xFFFF;
63  unsigned int QualityEnableME1d = 0xFFFF;
64  unsigned int QualityEnableME1e = 0xFFFF;
65  unsigned int QualityEnableME1f = 0xFFFF;
66  unsigned int QualityEnableME2a = 0xFFFF;
67  unsigned int QualityEnableME2b = 0xFFFF;
68  unsigned int QualityEnableME2c = 0xFFFF;
69  unsigned int QualityEnableME3a = 0xFFFF;
70  unsigned int QualityEnableME3b = 0xFFFF;
71  unsigned int QualityEnableME3c = 0xFFFF;
72  unsigned int QualityEnableME4a = 0xFFFF;
73  unsigned int QualityEnableME4b = 0xFFFF;
74  unsigned int QualityEnableME4c = 0xFFFF;
75 
76  unsigned int kill_fiber = 0;
77  unsigned int singlesTrackOutput = 1;
78  // ------------------------------------------------------
79 
80  //initialization of the DAT_ETA registers with default values
81  //the DAT_ETA registers meaning are explained at Table 2 of
82  //http://www.phys.ufl.edu/~uvarov/SP05/LU-SP_ReferenceGuide_090915_Update.pdf
83  std::vector<unsigned int> etamin(8), etamax(8), etawin(7);
84 
85  unsigned int mindetap = 8;
86  unsigned int mindetap_halo = 8;
87 
88  etamin[0] = 22;
89  etamin[1] = 22;
90  etamin[2] = 14;
91  etamin[3] = 14;
92  etamin[4] = 14;
93  etamin[5] = 14;
94  etamin[6] = 10;
95  etamin[7] = 22;
96 
97  unsigned int mindeta12_accp = 8;
98  unsigned int mindeta13_accp = 19;
99  unsigned int mindeta112_accp = 19;
100  unsigned int mindeta113_accp = 30;
101 
102  etamax[0] = 127;
103  etamax[1] = 127;
104  etamax[2] = 127;
105  etamax[3] = 127;
106  etamax[4] = 127;
107  etamax[5] = 24;
108  etamax[6] = 24;
109  etamax[7] = 127;
110 
111  unsigned int maxdeta12_accp = 14;
112  unsigned int maxdeta13_accp = 25;
113  unsigned int maxdeta112_accp = 25;
114  unsigned int maxdeta113_accp = 36;
115 
116  etawin[0] = 4;
117  etawin[1] = 4;
118  etawin[2] = 4;
119  etawin[3] = 4;
120  etawin[4] = 4;
121  etawin[5] = 4;
122  etawin[6] = 4;
123 
124  unsigned int maxdphi12_accp = 64;
125  unsigned int maxdphi13_accp = 64;
126  unsigned int maxdphi112_accp = 64;
127  unsigned int maxdphi113_accp = 64;
128 
129  unsigned int mindphip = 128;
130  unsigned int mindphip_halo = 128;
131 
132  unsigned int straightp = 60;
133  unsigned int curvedp = 200;
134 
135  unsigned int mbaPhiOff = 0;
136  // this differ from the default value in the documentation because during
137  // craft 09 it mbbPhiOff, as well as mbaPhiOff were not existing, thus set to 0 (they are offsets)
138  // and for backward compatibility it needs to be set to 0. Anyway mbbPhiOff since its introduction in the
139  // core will have to be ALWAYS part of the configuration, so it won't be never initialized to the
140  // default value 2048.
141  unsigned int mbbPhiOff = 0;
142 
143  int eta_cnt = 0;
144 
145  // default firmware versions (the ones used from run 132440)
146  unsigned int firmwareSP = 20100210;
147  unsigned int firmwareFA = 20090521;
148  unsigned int firmwareDD = 20090521;
149  unsigned int firmwareVM = 20090521;
150 
151  // default printout
152  LogDebug("L1MuCSCTFConfiguration")
153  << "\nCORE CONFIGURATION DEFAULT VALUES"
154  << "\nrun_core=" << run_core << "\ntrigger_on_ME1a=" << trigger_on_ME1a << "\ntrigger_on_ME1b=" << trigger_on_ME1b
155  << "\ntrigger_on_ME2=" << trigger_on_ME2 << "\ntrigger_on_ME3=" << trigger_on_ME3
156  << "\ntrigger_on_ME4=" << trigger_on_ME4 << "\ntrigger_on_MB1a=" << trigger_on_MB1a
157  << "\ntrigger_on_MB1d=" << trigger_on_MB1d
158 
159  << "\nBXAdepth=" << BXAdepth << "\nuseDT=" << useDT << "\nwidePhi=" << widePhi << "\nPreTrigger=" << PreTrigger
160 
161  << "\nCoreLatency=" << CoreLatency << "\nrescaleSinglesPhi=" << rescaleSinglesPhi
162 
163  << "\n\nVARIOUS CONFIGURATION PARAMETERS DEFAULT VALUES"
164  << "\nAllowALCTonly=" << AllowALCTonly << "\nAllowCLCTonly=" << AllowCLCTonly
165 
166  << "\nQualityEnableME1a=" << QualityEnableME1a << "\nQualityEnableME1b=" << QualityEnableME1b
167  << "\nQualityEnableME1c=" << QualityEnableME1c << "\nQualityEnableME1d=" << QualityEnableME1d
168  << "\nQualityEnableME1e=" << QualityEnableME1e << "\nQualityEnableME1f=" << QualityEnableME1f
169  << "\nQualityEnableME2a=" << QualityEnableME2a << "\nQualityEnableME2b=" << QualityEnableME2b
170  << "\nQualityEnableME2c=" << QualityEnableME2c << "\nQualityEnableME3a=" << QualityEnableME3a
171  << "\nQualityEnableME3b=" << QualityEnableME3b << "\nQualityEnableME3c=" << QualityEnableME3c
172  << "\nQualityEnableME4a=" << QualityEnableME4a << "\nQualityEnableME4b=" << QualityEnableME4b
173  << "\nQualityEnableME4c=" << QualityEnableME4c
174 
175  << "\nkill_fiber=" << kill_fiber << "\nsinglesTrackOutput=" << singlesTrackOutput
176 
177  << "\n\nDEFAULT VALUES FOR DAT_ETA"
178  << "\nmindetap =" << mindetap << "\nmindetap_halo=" << mindetap_halo
179 
180  << "\netamin[0]=" << etamin[0] << "\netamin[1]=" << etamin[1] << "\netamin[2]=" << etamin[2]
181  << "\netamin[3]=" << etamin[3] << "\netamin[4]=" << etamin[4] << "\netamin[5]=" << etamin[5]
182  << "\netamin[6]=" << etamin[6] << "\netamin[7]=" << etamin[7]
183 
184  << "\nmindeta12_accp =" << mindeta12_accp << "\nmindeta13_accp =" << mindeta13_accp
185  << "\nmindeta112_accp=" << mindeta112_accp << "\nmindeta113_accp=" << mindeta113_accp
186 
187  << "\netamax[0]=" << etamax[0] << "\netamax[1]=" << etamax[1] << "\netamax[2]=" << etamax[2]
188  << "\netamax[3]=" << etamax[3] << "\netamax[4]=" << etamax[4] << "\netamax[5]=" << etamax[5]
189  << "\netamax[6]=" << etamax[6] << "\netamax[7]=" << etamax[7]
190 
191  << "\nmaxdeta12_accp =" << maxdeta12_accp << "\nmaxdeta13_accp =" << maxdeta13_accp
192  << "\nmaxdeta112_accp=" << maxdeta112_accp << "\nmaxdeta113_accp=" << maxdeta113_accp
193 
194  << "\netawin[0]=" << etawin[0] << "\netawin[1]=" << etawin[1] << "\netawin[2]=" << etawin[2]
195  << "\netawin[3]=" << etawin[3] << "\netawin[4]=" << etawin[4] << "\netawin[5]=" << etawin[5]
196  << "\netawin[6]=" << etawin[6]
197 
198  << "\nmaxdphi12_accp =" << maxdphi12_accp << "\nmaxdphi13_accp =" << maxdphi13_accp
199  << "\nmaxdphi112_accp=" << maxdphi112_accp << "\nmaxdphi113_accp=" << maxdphi113_accp
200 
201  << "\nmindphip =" << mindphip << "\nmindphip_halo=" << mindphip_halo
202 
203  << "\nstraightp=" << straightp << "\ncurvedp =" << curvedp << "\nmbaPhiOff=" << mbaPhiOff
204  << "\nmbbPhiOff=" << mbbPhiOff
205 
206  << "\n\nFIRMWARE VERSIONS"
207  << "\nSP: " << firmwareSP << "\nFA: " << firmwareFA << "\nDD: " << firmwareDD << "\nVM: " << firmwareVM;
208 
209  // start filling the registers with the values in the DBS
210  std::stringstream conf(iConfig[sp]);
211  while (!conf.eof()) {
212  char buff[1024];
213  conf.getline(buff, 1024);
214  std::stringstream line(buff);
215  //std::cout<<"buff:"<<buff<<std::endl;
216  std::string register_;
217  line >> register_;
218  std::string chip_;
219  line >> chip_;
220  std::string muon_;
221  line >> muon_;
222  std::string writeValue_;
223  line >> writeValue_;
224  std::string comments_;
225  std::getline(line, comments_);
226 
227  if (register_ == "CSR_REQ" && chip_ == "SP") {
228  unsigned int value = ::strtol(writeValue_.c_str(), nullptr, 16);
229  run_core = (value & 0x8000);
230  trigger_on_ME1a = (value & 0x0001);
231  trigger_on_ME1b = (value & 0x0002);
232  trigger_on_ME2 = (value & 0x0004);
233  trigger_on_ME3 = (value & 0x0008);
234  trigger_on_ME4 = (value & 0x0010);
235  trigger_on_MB1a = (value & 0x0100);
236  trigger_on_MB1d = (value & 0x0200);
237  }
238 
239  if (register_ == "CSR_SCC" && chip_ == "SP") {
240  unsigned int value = ::strtol(writeValue_.c_str(), nullptr, 16);
241 
242  BXAdepth = (value & 0x3);
243  useDT = ((value & 0x80) >> 7);
244  widePhi = ((value & 0x40) >> 6);
245  PreTrigger = ((value & 0x300) >> 8);
246  }
247 
248  if (register_ == "CSR_LQE" && chip_ == "F1" && muon_ == "M1")
249  QualityEnableME1a = ::strtol(writeValue_.c_str(), nullptr, 16);
250  if (register_ == "CSR_LQE" && chip_ == "F1" && muon_ == "M2")
251  QualityEnableME1b = ::strtol(writeValue_.c_str(), nullptr, 16);
252  if (register_ == "CSR_LQE" && chip_ == "F1" && muon_ == "M3")
253  QualityEnableME1c = ::strtol(writeValue_.c_str(), nullptr, 16);
254  if (register_ == "CSR_LQE" && chip_ == "F2" && muon_ == "M1")
255  QualityEnableME1d = ::strtol(writeValue_.c_str(), nullptr, 16);
256  if (register_ == "CSR_LQE" && chip_ == "F2" && muon_ == "M2")
257  QualityEnableME1e = ::strtol(writeValue_.c_str(), nullptr, 16);
258  if (register_ == "CSR_LQE" && chip_ == "F2" && muon_ == "M3")
259  QualityEnableME1f = ::strtol(writeValue_.c_str(), nullptr, 16);
260  if (register_ == "CSR_LQE" && chip_ == "F3" && muon_ == "M1")
261  QualityEnableME2a = ::strtol(writeValue_.c_str(), nullptr, 16);
262  if (register_ == "CSR_LQE" && chip_ == "F3" && muon_ == "M2")
263  QualityEnableME2b = ::strtol(writeValue_.c_str(), nullptr, 16);
264  if (register_ == "CSR_LQE" && chip_ == "F3" && muon_ == "M3")
265  QualityEnableME2c = ::strtol(writeValue_.c_str(), nullptr, 16);
266  if (register_ == "CSR_LQE" && chip_ == "F4" && muon_ == "M1")
267  QualityEnableME3a = ::strtol(writeValue_.c_str(), nullptr, 16);
268  if (register_ == "CSR_LQE" && chip_ == "F4" && muon_ == "M2")
269  QualityEnableME3b = ::strtol(writeValue_.c_str(), nullptr, 16);
270  if (register_ == "CSR_LQE" && chip_ == "F4" && muon_ == "M3")
271  QualityEnableME3c = ::strtol(writeValue_.c_str(), nullptr, 16);
272  if (register_ == "CSR_LQE" && chip_ == "F5" && muon_ == "M1")
273  QualityEnableME4a = ::strtol(writeValue_.c_str(), nullptr, 16);
274  if (register_ == "CSR_LQE" && chip_ == "F5" && muon_ == "M2")
275  QualityEnableME4b = ::strtol(writeValue_.c_str(), nullptr, 16);
276  if (register_ == "CSR_LQE" && chip_ == "F5" && muon_ == "M3")
277  QualityEnableME4c = ::strtol(writeValue_.c_str(), nullptr, 16);
278 
279  if (register_ == "CSR_KFL")
280  kill_fiber = ::strtol(writeValue_.c_str(), nullptr, 16);
281 
282  if (register_ == "CSR_SFC" && chip_ == "SP") {
283  unsigned int value = ::strtol(writeValue_.c_str(), nullptr, 16);
284  singlesTrackOutput = ((value & 0x3000) >> 12);
285  }
286 
287  if (register_ == "CNT_ETA" && chip_ == "SP") {
288  unsigned int value = ::strtol(writeValue_.c_str(), nullptr, 16);
289  eta_cnt = value;
290  }
291 
292  // LATEST VERSION FROM CORE 2010-01-22 at http://www.phys.ufl.edu/~madorsky/sp/2010-01-22
293  if (register_ == "DAT_ETA" && chip_ == "SP") {
294  unsigned int value = ::strtol(writeValue_.c_str(), nullptr, 16);
295 
296  //std::cout<<"DAT_ETA SP value:"<<value<<std::endl;
297 
298  if (eta_cnt == 0)
299  mindetap = value;
300  if (eta_cnt == 1)
301  mindetap_halo = value;
302 
303  if (eta_cnt >= 2 && eta_cnt < 10)
304  etamin[eta_cnt - 2] = value;
305 
306  if (eta_cnt == 10)
307  mindeta12_accp = value;
308  if (eta_cnt == 11)
309  mindeta13_accp = value;
310  if (eta_cnt == 12)
311  mindeta112_accp = value;
312  if (eta_cnt == 13)
313  mindeta113_accp = value;
314 
315  if (eta_cnt >= 14 && eta_cnt < 22)
316  etamax[eta_cnt - 14] = value;
317 
318  if (eta_cnt == 22)
319  maxdeta12_accp = value;
320  if (eta_cnt == 23)
321  maxdeta13_accp = value;
322  if (eta_cnt == 24)
323  maxdeta112_accp = value;
324  if (eta_cnt == 25)
325  maxdeta113_accp = value;
326 
327  if (eta_cnt >= 26 && eta_cnt < 33)
328  etawin[eta_cnt - 26] = value;
329 
330  if (eta_cnt == 33)
331  maxdphi12_accp = value;
332  if (eta_cnt == 34)
333  maxdphi13_accp = value;
334  if (eta_cnt == 35)
335  maxdphi112_accp = value;
336  if (eta_cnt == 36)
337  maxdphi113_accp = value;
338 
339  if (eta_cnt == 37)
340  mindphip = value;
341  if (eta_cnt == 38)
342  mindphip_halo = value;
343 
344  if (eta_cnt == 39)
345  straightp = value;
346  if (eta_cnt == 40)
347  curvedp = value;
348  if (eta_cnt == 41)
349  mbaPhiOff = value;
350  if (eta_cnt == 42)
351  mbbPhiOff = value;
352 
353  eta_cnt++;
354  }
355 
356  // filling the firmware variables: SP MEZZANINE
357  if (register_ == "FIRMWARE" && muon_ == "SP") {
358  unsigned int value = atoi(writeValue_.c_str());
359  firmwareSP = value;
360  }
361 
362  // filling the firmware variables: Front FPGAs
363  if (register_ == "FIRMWARE" && muon_ == "FA") {
364  unsigned int value = atoi(writeValue_.c_str());
365  firmwareFA = value;
366  }
367 
368  // filling the firmware variables: DDU
369  if (register_ == "FIRMWARE" && muon_ == "DD") {
370  unsigned int value = atoi(writeValue_.c_str());
371  firmwareDD = value;
372  }
373 
374  // filling the firmware variables: VM
375  if (register_ == "FIRMWARE" && muon_ == "VM") {
376  unsigned int value = atoi(writeValue_.c_str());
377  firmwareVM = value;
378  }
379  }
380 
381  pset.addParameter<bool>("run_core", run_core);
382  pset.addParameter<bool>("trigger_on_ME1a", trigger_on_ME1a);
383  pset.addParameter<bool>("trigger_on_ME1b", trigger_on_ME1b);
384  pset.addParameter<bool>("trigger_on_ME2", trigger_on_ME2);
385  pset.addParameter<bool>("trigger_on_ME3", trigger_on_ME3);
386  pset.addParameter<bool>("trigger_on_ME4", trigger_on_ME4);
387  pset.addParameter<bool>("trigger_on_MB1a", trigger_on_MB1a);
388  pset.addParameter<bool>("trigger_on_MB1d", trigger_on_MB1d);
389 
390  pset.addParameter<unsigned int>("BXAdepth", BXAdepth);
391  pset.addParameter<unsigned int>("useDT", useDT);
392  pset.addParameter<unsigned int>("widePhi", widePhi);
393  pset.addParameter<unsigned int>("PreTrigger", PreTrigger);
394 
395  // this were two old settings, not used anymore. Set them to zero
396  // ask Alex if he can remove them altogether
397  pset.addParameter<bool>("AllowALCTonly", AllowALCTonly);
398  pset.addParameter<bool>("AllowCLCTonly", AllowCLCTonly);
399 
400  pset.addParameter<int>("CoreLatency", CoreLatency);
401  pset.addParameter<bool>("rescaleSinglesPhi", rescaleSinglesPhi);
402 
403  pset.addParameter<unsigned int>("QualityEnableME1a", QualityEnableME1a);
404  pset.addParameter<unsigned int>("QualityEnableME1b", QualityEnableME1b);
405  pset.addParameter<unsigned int>("QualityEnableME1c", QualityEnableME1c);
406  pset.addParameter<unsigned int>("QualityEnableME1d", QualityEnableME1d);
407  pset.addParameter<unsigned int>("QualityEnableME1e", QualityEnableME1e);
408  pset.addParameter<unsigned int>("QualityEnableME1f", QualityEnableME1f);
409  pset.addParameter<unsigned int>("QualityEnableME2a", QualityEnableME2a);
410  pset.addParameter<unsigned int>("QualityEnableME2b", QualityEnableME2b);
411  pset.addParameter<unsigned int>("QualityEnableME2c", QualityEnableME2c);
412  pset.addParameter<unsigned int>("QualityEnableME3a", QualityEnableME3a);
413  pset.addParameter<unsigned int>("QualityEnableME3b", QualityEnableME3b);
414  pset.addParameter<unsigned int>("QualityEnableME3c", QualityEnableME3c);
415  pset.addParameter<unsigned int>("QualityEnableME4a", QualityEnableME4a);
416  pset.addParameter<unsigned int>("QualityEnableME4b", QualityEnableME4b);
417  pset.addParameter<unsigned int>("QualityEnableME4c", QualityEnableME4c);
418 
419  pset.addParameter<unsigned int>("kill_fiber", kill_fiber);
420  pset.addParameter<unsigned int>("singlesTrackOutput", singlesTrackOutput);
421 
422  // add the DAT_ETA registers to the pset
423  pset.addParameter<unsigned int>("mindetap", mindetap);
424  pset.addParameter<unsigned int>("mindetap_halo", mindetap_halo);
425 
426  pset.addParameter<std::vector<unsigned int> >("EtaMin", etamin);
427 
428  pset.addParameter<unsigned int>("mindeta12_accp", mindeta12_accp);
429  pset.addParameter<unsigned int>("mindeta13_accp", mindeta13_accp);
430  pset.addParameter<unsigned int>("mindeta112_accp", mindeta112_accp);
431  pset.addParameter<unsigned int>("mindeta113_accp", mindeta113_accp);
432 
433  pset.addParameter<std::vector<unsigned int> >("EtaMax", etamax);
434 
435  pset.addParameter<unsigned int>("maxdeta12_accp", maxdeta12_accp);
436  pset.addParameter<unsigned int>("maxdeta13_accp", maxdeta13_accp);
437  pset.addParameter<unsigned int>("maxdeta112_accp", maxdeta112_accp);
438  pset.addParameter<unsigned int>("maxdeta113_accp", maxdeta113_accp);
439 
440  pset.addParameter<std::vector<unsigned int> >("EtaWindows", etawin);
441 
442  pset.addParameter<unsigned int>("maxdphi12_accp", maxdphi12_accp);
443  pset.addParameter<unsigned int>("maxdphi13_accp", maxdphi13_accp);
444  pset.addParameter<unsigned int>("maxdphi112_accp", maxdphi112_accp);
445  pset.addParameter<unsigned int>("maxdphi113_accp", maxdphi113_accp);
446 
447  pset.addParameter<unsigned int>("mindphip", mindphip);
448  pset.addParameter<unsigned int>("mindphip_halo", mindphip_halo);
449 
450  pset.addParameter<unsigned int>("straightp", straightp);
451  pset.addParameter<unsigned int>("curvedp", curvedp);
452  pset.addParameter<unsigned int>("mbaPhiOff", mbaPhiOff);
453  pset.addParameter<unsigned int>("mbbPhiOff", mbbPhiOff);
454 
455  pset.addParameter<unsigned int>("firmwareSP", firmwareSP);
456  pset.addParameter<unsigned int>("firmwareFA", firmwareFA);
457  pset.addParameter<unsigned int>("firmwareDD", firmwareDD);
458  pset.addParameter<unsigned int>("firmwareVM", firmwareVM);
459 
460  // printout
461  LogDebug("L1MuCSCTFConfiguration")
462  << "\nCORE CONFIGURATION AFTER READING THE DBS VALUES"
463  << "\nrun_core=" << run_core << "\ntrigger_on_ME1a=" << trigger_on_ME1a << "\ntrigger_on_ME1b=" << trigger_on_ME1b
464  << "\ntrigger_on_ME2=" << trigger_on_ME2 << "\ntrigger_on_ME3=" << trigger_on_ME3
465  << "\ntrigger_on_ME4=" << trigger_on_ME4 << "\ntrigger_on_MB1a=" << trigger_on_MB1a
466  << "\ntrigger_on_MB1d=" << trigger_on_MB1d
467 
468  << "\nBXAdepth=" << BXAdepth << "\nuseDT=" << useDT << "\nwidePhi=" << widePhi << "\nPreTrigger=" << PreTrigger
469 
470  << "\nCoreLatency=" << CoreLatency << "\nrescaleSinglesPhi=" << rescaleSinglesPhi
471 
472  << "\n\nVARIOUS CONFIGURATION PARAMETERS AFTER READING THE DBS VALUES"
473  << "\nAllowALCTonly=" << AllowALCTonly << "\nAllowCLCTonly=" << AllowCLCTonly
474 
475  << "\nQualityEnableME1a=" << QualityEnableME1a << "\nQualityEnableME1b=" << QualityEnableME1b
476  << "\nQualityEnableME1c=" << QualityEnableME1c << "\nQualityEnableME1d=" << QualityEnableME1d
477  << "\nQualityEnableME1e=" << QualityEnableME1e << "\nQualityEnableME1f=" << QualityEnableME1f
478  << "\nQualityEnableME2a=" << QualityEnableME2a << "\nQualityEnableME2b=" << QualityEnableME2b
479  << "\nQualityEnableME2c=" << QualityEnableME2c << "\nQualityEnableME3a=" << QualityEnableME3a
480  << "\nQualityEnableME3b=" << QualityEnableME3b << "\nQualityEnableME3c=" << QualityEnableME3c
481  << "\nQualityEnableME4a=" << QualityEnableME4a << "\nQualityEnableME4b=" << QualityEnableME4b
482  << "\nQualityEnableME4c=" << QualityEnableME4c
483 
484  << "\nkill_fiber=" << kill_fiber << "\nsinglesTrackOutput=" << singlesTrackOutput
485 
486  << "\n\nDAT_ETA AFTER READING THE DBS VALUES"
487  << "\nmindetap =" << mindetap << "\nmindetap_halo=" << mindetap_halo
488 
489  << "\netamin[0]=" << etamin[0] << "\netamin[1]=" << etamin[1] << "\netamin[2]=" << etamin[2]
490  << "\netamin[3]=" << etamin[3] << "\netamin[4]=" << etamin[4] << "\netamin[5]=" << etamin[5]
491  << "\netamin[6]=" << etamin[6] << "\netamin[7]=" << etamin[7]
492 
493  << "\nmindeta12_accp =" << mindeta12_accp << "\nmindeta13_accp =" << mindeta13_accp
494  << "\nmindeta112_accp=" << mindeta112_accp << "\nmindeta113_accp=" << mindeta113_accp
495 
496  << "\netamax[0]=" << etamax[0] << "\netamax[1]=" << etamax[1] << "\netamax[2]=" << etamax[2]
497  << "\netamax[3]=" << etamax[3] << "\netamax[4]=" << etamax[4] << "\netamax[5]=" << etamax[5]
498  << "\netamax[6]=" << etamax[6] << "\netamax[7]=" << etamax[7]
499 
500  << "\nmaxdeta12_accp =" << maxdeta12_accp << "\nmaxdeta13_accp =" << maxdeta13_accp
501  << "\nmaxdeta112_accp=" << maxdeta112_accp << "\nmaxdeta113_accp=" << maxdeta113_accp
502 
503  << "\netawin[0]=" << etawin[0] << "\netawin[1]=" << etawin[1] << "\netawin[2]=" << etawin[2]
504  << "\netawin[3]=" << etawin[3] << "\netawin[4]=" << etawin[4] << "\netawin[5]=" << etawin[5]
505  << "\netawin[6]=" << etawin[6]
506 
507  << "\nmaxdphi12_accp =" << maxdphi12_accp << "\nmaxdphi13_accp =" << maxdphi13_accp
508  << "\nmaxdphi112_accp=" << maxdphi112_accp << "\nmaxdphi113_accp=" << maxdphi113_accp
509 
510  << "\nmindphip =" << mindphip << "\nmindphip_halo=" << mindphip_halo
511 
512  << "\nstraightp=" << straightp << "\ncurvedp =" << curvedp << "\nmbaPhiOff=" << mbaPhiOff
513  << "\nmbbPhiOff=" << mbbPhiOff
514 
515  << "\n\nFIRMWARE VERSIONS AFTER READING THE DBS VALUES"
516  << "\nSP: " << firmwareSP << "\nFA: " << firmwareFA << "\nDD: " << firmwareDD << "\nVM: " << firmwareVM;
517 
518  // ---------------------------------------------------------
519 
520  return pset;
521 }
csctfTrackDigis_cfi.maxdeta13_accp
maxdeta13_accp
Definition: csctfTrackDigis_cfi.py:71
csctfTrackDigis_cfi.BXAdepth
BXAdepth
Definition: csctfTrackDigis_cfi.py:52
csctfTrackDigis_cfi.trigger_on_ME1a
trigger_on_ME1a
Definition: csctfTrackDigis_cfi.py:43
csctfTrackDigis_cfi.trigger_on_MB1a
trigger_on_MB1a
Definition: csctfTrackDigis_cfi.py:41
csctfTrackDigis_cfi.QualityEnableME4b
QualityEnableME4b
Definition: csctfTrackDigis_cfi.py:105
csctfTrackDigis_cfi.useDT
useDT
Definition: csctfTrackDigis_cfi.py:122
csctfTrackDigis_cfi.QualityEnableME1f
QualityEnableME1f
Definition: csctfTrackDigis_cfi.py:97
csctfTrackDigis_cfi.QualityEnableME3a
QualityEnableME3a
Definition: csctfTrackDigis_cfi.py:101
csctfTrackDigis_cfi.run_core
run_core
Definition: csctfTrackDigis_cfi.py:40
csctfTrackDigis_cfi.singlesTrackOutput
singlesTrackOutput
Definition: csctfTrackDigis_cfi.py:48
csctfTrackDigis_cfi.QualityEnableME2a
QualityEnableME2a
Definition: csctfTrackDigis_cfi.py:98
csctfTrackDigis_cfi.QualityEnableME3c
QualityEnableME3c
Definition: csctfTrackDigis_cfi.py:103
csctfTrackDigis_cfi.firmwareSP
firmwareSP
Definition: csctfTrackDigis_cfi.py:108
csctfTrackDigis_cfi.mindphip
mindphip
Definition: csctfTrackDigis_cfi.py:82
csctfTrackDigis_cfi.trigger_on_ME4
trigger_on_ME4
Definition: csctfTrackDigis_cfi.py:47
csctfTrackDigis_cfi.mindeta12_accp
mindeta12_accp
Definition: csctfTrackDigis_cfi.py:63
csctfTrackDigis_cfi.mbbPhiOff
mbbPhiOff
Definition: csctfTrackDigis_cfi.py:89
csctfTrackDigis_cfi.mindetap
mindetap
Definition: csctfTrackDigis_cfi.py:58
csctfTrackDigis_cfi.CoreLatency
CoreLatency
Definition: csctfTrackDigis_cfi.py:50
csctfTrackDigis_cfi.mindeta113_accp
mindeta113_accp
Definition: csctfTrackDigis_cfi.py:66
csctfTrackDigis_cfi.mindetap_halo
mindetap_halo
Definition: csctfTrackDigis_cfi.py:59
csctfTrackDigis_cfi.widePhi
widePhi
Definition: csctfTrackDigis_cfi.py:53
muonDTDigis_cfi.pset
pset
Definition: muonDTDigis_cfi.py:27
csctfTrackDigis_cfi.mindphip_halo
mindphip_halo
Definition: csctfTrackDigis_cfi.py:83
muonTiming_cfi.etamin
etamin
Definition: muonTiming_cfi.py:30
csctfTrackDigis_cfi.kill_fiber
kill_fiber
Definition: csctfTrackDigis_cfi.py:91
csctfTrackDigis_cfi.QualityEnableME1d
QualityEnableME1d
Definition: csctfTrackDigis_cfi.py:95
csctfTrackDigis_cfi.curvedp
curvedp
Definition: csctfTrackDigis_cfi.py:86
AlCaHLTBitMon_QueryRunRegistry.string
string string
Definition: AlCaHLTBitMon_QueryRunRegistry.py:256
csctfTrackDigis_cfi.trigger_on_ME1b
trigger_on_ME1b
Definition: csctfTrackDigis_cfi.py:44
csctfTrackDigis_cfi.rescaleSinglesPhi
rescaleSinglesPhi
Definition: csctfTrackDigis_cfi.py:39
csctfTrackDigis_cfi.mindeta13_accp
mindeta13_accp
Definition: csctfTrackDigis_cfi.py:64
csctfTrackDigis_cfi.maxdphi13_accp
maxdphi13_accp
Definition: csctfTrackDigis_cfi.py:78
csctfTrackDigis_cfi.QualityEnableME1a
QualityEnableME1a
Definition: csctfTrackDigis_cfi.py:92
csctfTrackDigis_cfi.AllowALCTonly
AllowALCTonly
Definition: csctfTrackDigis_cfi.py:37
csctfTrackDigis_cfi.mindeta112_accp
mindeta112_accp
Definition: csctfTrackDigis_cfi.py:65
csctfTrackDigis_cfi.straightp
straightp
Definition: csctfTrackDigis_cfi.py:85
mps_splice.line
line
Definition: mps_splice.py:76
csctfTrackDigis_cfi.AllowCLCTonly
AllowCLCTonly
Definition: csctfTrackDigis_cfi.py:38
csctfTrackDigis_cfi.maxdphi12_accp
maxdphi12_accp
Definition: csctfTrackDigis_cfi.py:77
csctfTrackDigis_cfi.QualityEnableME4a
QualityEnableME4a
Definition: csctfTrackDigis_cfi.py:104
csctfTrackDigis_cfi.maxdphi113_accp
maxdphi113_accp
Definition: csctfTrackDigis_cfi.py:80
csctfTrackDigis_cfi.QualityEnableME1e
QualityEnableME1e
Definition: csctfTrackDigis_cfi.py:96
value
Definition: value.py:1
csctfTrackDigis_cfi.QualityEnableME3b
QualityEnableME3b
Definition: csctfTrackDigis_cfi.py:102
csctfTrackDigis_cfi.maxdeta112_accp
maxdeta112_accp
Definition: csctfTrackDigis_cfi.py:72
csctfTrackDigis_cfi.QualityEnableME2b
QualityEnableME2b
Definition: csctfTrackDigis_cfi.py:99
muonTiming_cfi.etamax
etamax
Definition: muonTiming_cfi.py:23
csctfTrackDigis_cfi.firmwareVM
firmwareVM
Definition: csctfTrackDigis_cfi.py:111
csctfTrackDigis_cfi.mbaPhiOff
mbaPhiOff
Definition: csctfTrackDigis_cfi.py:88
csctfTrackDigis_cfi.maxdphi112_accp
maxdphi112_accp
Definition: csctfTrackDigis_cfi.py:79
csctfTrackDigis_cfi.maxdeta113_accp
maxdeta113_accp
Definition: csctfTrackDigis_cfi.py:73
csctfTrackDigis_cfi.trigger_on_MB1d
trigger_on_MB1d
Definition: csctfTrackDigis_cfi.py:42
csctfTrackDigis_cfi.firmwareDD
firmwareDD
Definition: csctfTrackDigis_cfi.py:110
csctfTrackDigis_cfi.QualityEnableME4c
QualityEnableME4c
Definition: csctfTrackDigis_cfi.py:106
csctfTrackDigis_cfi.trigger_on_ME2
trigger_on_ME2
Definition: csctfTrackDigis_cfi.py:45
csctfTrackDigis_cfi.QualityEnableME1b
QualityEnableME1b
Definition: csctfTrackDigis_cfi.py:93
csctfTrackDigis_cfi.trigger_on_ME3
trigger_on_ME3
Definition: csctfTrackDigis_cfi.py:46
csctfTrackDigis_cfi.maxdeta12_accp
maxdeta12_accp
Definition: csctfTrackDigis_cfi.py:70
csctfTrackDigis_cfi.firmwareFA
firmwareFA
Definition: csctfTrackDigis_cfi.py:109
csctfTrackDigis_cfi.PreTrigger
PreTrigger
Definition: csctfTrackDigis_cfi.py:51
csctfTrackDigis_cfi.QualityEnableME1c
QualityEnableME1c
Definition: csctfTrackDigis_cfi.py:94
LogDebug
#define LogDebug(id)
Definition: MessageLogger.h:233
csctfTrackDigis_cfi.QualityEnableME2c
QualityEnableME2c
Definition: csctfTrackDigis_cfi.py:100
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