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PixelFEDCard.cc
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1 // Read the pixelFED setup parameters from an ASCII file
2 // Will Johns & Danek Kotlinski 04/06.
3 
4 #include <iostream>
5 
6 #include "CalibFormats/SiPixelObjects/interface/PixelFEDCard.h"
7 #include "CalibFormats/SiPixelObjects/interface/PixelTimeFormatter.h"
8 
9 #include <cassert>
10 #include <sstream>
11 #include <map>
12 #include <stdexcept>
13 
14 using namespace std;
15 
16 using namespace pos;
17 
18 PixelFEDCard::PixelFEDCard() : PixelConfigBase(" ", " ", " ") { clear(); }
19 
20 // modified by MR on 24-04-2008 12:05:42
21 // Read configuration from DB
22 PixelFEDCard::PixelFEDCard(vector<vector<string> > &tableMat) : PixelConfigBase(" ", " ", " ") {
23  std::string mthn = "[PixelFEDCard::PixelFEDCard()]\t\t ";
24  vector<string> ins = tableMat[0];
25  map<string, int> colM;
26  vector<string> colNames;
27  bool first = true;
128  colNames.push_back("BUSYWHENBEHIND");
129  colNames.push_back("FEATUREREGISTER");
130  colNames.push_back("FIFO2LIMIT");
131  colNames.push_back("TIMEOUTOROOSLIMIT");
132  colNames.push_back("LASTDACOFF");
133  colNames.push_back("SIMHITSPERROC");
134  colNames.push_back("BUSYHOLDMIN");
135  colNames.push_back("SPARE1");
136  colNames.push_back("SPARE2");
137  colNames.push_back("SPARE3");
138  colNames.push_back("SPARE4");
139  colNames.push_back("SPARE5");
140  colNames.push_back("SPARE6");
141  colNames.push_back("SPARE7");
142  colNames.push_back("SPARE8");
143  colNames.push_back("SPARE9");
144  colNames.push_back("SPARE10");
145  colNames.push_back("CONFIG_KEY");
146  colNames.push_back("KEY_TYPE");
147  colNames.push_back("KEY_ALIAS_ID");
148  colNames.push_back("KEY_ALIAS");
149  colNames.push_back("VERSION");
150  colNames.push_back("KIND_OF_COND");
151  colNames.push_back("CRATE_LABEL");
152  colNames.push_back("CRATE_NUMBER");
153  colNames.push_back("SLOT_NUMBER");
154  colNames.push_back("VME_ADDRS_HEX");
155  colNames.push_back("PIXEL_FED");
156  colNames.push_back("CHANNEL_ID");
157  colNames.push_back("NUM_ROCS");
158  colNames.push_back("CHAN_OFFST_DAC");
159  colNames.push_back("CHAN_DELAY");
160  colNames.push_back("CHAN_BHIGH");
161  colNames.push_back("CHAN_BLOW");
162  colNames.push_back("CHAN_UB");
163  colNames.push_back("OPT1_CAP");
164  colNames.push_back("OPT2_CAP");
165  colNames.push_back("OPT3_CAP");
166  colNames.push_back("OPT1_INP");
167  colNames.push_back("OPT2_INP");
168  colNames.push_back("OPT3_INP");
169  colNames.push_back("OPT1_OUT");
170  colNames.push_back("OPT2_OUT");
171  colNames.push_back("OPT3_OUT");
172  colNames.push_back("NORTH_CLKPHB");
173  colNames.push_back("NORTHCENTER_CLKPHB");
174  colNames.push_back("SOUTHCENTER_CLKPHB");
175  colNames.push_back("SOUTH_CLKPHB");
176  colNames.push_back("NORTH_CTRL");
177  colNames.push_back("NORTHCENTER_CTRL");
178  colNames.push_back("SOUTHCENTER_CTRL");
179  colNames.push_back("SOUTH_CTRL");
180  colNames.push_back("REG0_TTCRX_FDLA");
181  colNames.push_back("REG1_TTCRX_FDLA");
182  colNames.push_back("REG2_TTCRX_CDLA");
183  colNames.push_back("REG3_TTCRX_CLKD2");
184  colNames.push_back("CENTER_CTRL");
185  colNames.push_back("CENTER_MODE");
186  colNames.push_back("B1_ADCGN");
187  colNames.push_back("B2_ADCGN");
188  colNames.push_back("B3_ADCGN");
189  colNames.push_back("B4_ADCGN");
190  colNames.push_back("NORTH_BADJ");
191  colNames.push_back("NORTHCENTER_BADJ");
192  colNames.push_back("SOUTHCENTER_BADJ");
193  colNames.push_back("SOUTH_BADJ");
194  colNames.push_back("NORTH_TBMMASK");
195  colNames.push_back("NORTHCENTER_TBMMASK");
196  colNames.push_back("SOUTHCENTER_TBMMASK");
197  colNames.push_back("SOUTH_TBMMASK");
198  colNames.push_back("NORTH_PWORD");
199  colNames.push_back("NORTHCENTER_PWORD");
200  colNames.push_back("SOUTH_PWORD");
201  colNames.push_back("SOUTHCENTER_PWORD");
202  colNames.push_back("SPECDAC");
203  colNames.push_back("OOS_LVL");
204  colNames.push_back("ERR_LVL");
205  colNames.push_back("NORTH_FIFO1_BZ_LVL");
206  colNames.push_back("NORTHCENTER_FIFO1_BZ_LVL");
207  colNames.push_back("SOUTHCENTER_FIFO1_BZ_LVL");
208  colNames.push_back("SOUTH_FIFO1_BZ_LVL");
209  colNames.push_back("FIFO3_WRN_LVL");
210  colNames.push_back("FED_MASTER_DELAY");
211  colNames.push_back("NO_HITLIMIT");
212  colNames.push_back("NC_HITLIMIT");
213  colNames.push_back("SC_HITLIMIT");
214  colNames.push_back("SO_HITLIMIT");
215  colNames.push_back("NO_TESTREG");
216  colNames.push_back("NC_TESTREG");
217  colNames.push_back("SC_TESTREG");
218  colNames.push_back("SO_TESTREG");
219  colNames.push_back("TRIGGERHOLDOFF");
220 
221  for (unsigned int c = 0; c < ins.size(); c++) {
222  for (unsigned int n = 0; n < colNames.size(); n++) {
223  if (tableMat[0][c] == colNames[n]) {
224  colM[colNames[n]] = c;
225  break;
226  }
227  }
228  } //end for
229  for (unsigned int n = 0; n < colNames.size(); n++) {
230  if (colM.find(colNames[n]) == colM.end()) {
231  std::cerr << __LINE__ << "]\t[PixelFEDCard::PixelFEDCard]\tCouldn't find in the database the column with name "
232  << colNames[n] << std::endl;
233  assert(0);
234  }
235  }
236  // disentagle different tables
237  int size[3];
238  int indexsize = 0;
239  for (unsigned int r = 0; r < tableMat.size(); r++) { //Goes to every row of the Matrix
240  if (tableMat[r].empty()) {
241  // cout << __LINE__ << "]\t" << mthn << "__________________ NEW TABLE __________________"<< endl ;
242  size[indexsize] = r;
243  // cout << __LINE__ << "]\t" << mthn << "size[" << indexsize << "] = " << size[indexsize] << endl ;
244  indexsize++;
245  continue;
246  }
247  for (vector<string>::iterator it = tableMat[r].begin(); it != tableMat[r].end(); ++it) {
248  // cout << __LINE__ << "]\t" << mthn << *it <<"["<<&*it<<"]\t" ;
249  // cout << __LINE__ << "]\t" << mthn << *it <<"\t" ;
250  }
251  // cout << __LINE__ << "]\t" << mthn << endl ;
252  }
253 
254  // Read below quantities pertaining to a single FED that are equal accross 36 channels
255  if (first) {
256  first = false;
257  //VME base address
258  //Fed Base Address
259  sscanf(tableMat[1][colM["VME_ADDRS_HEX"]].c_str(), "%lx", &FEDBASE_0);
260  // sscanf(tableMat[1][colM["PIXEL_FED"]].c_str(), "PxlFED_%ld",&fedNumber);
261  fedNumber = atoi(tableMat[1][colM["PIXEL_FED"]].c_str());
262  //Settable optical input parameters (one for each 12-receiver)
263  opt_cap[0] = atoi(tableMat[1][colM["OPT1_CAP"]].c_str());
264  opt_cap[1] = atoi(tableMat[1][colM["OPT2_CAP"]].c_str());
265  opt_cap[2] = atoi(tableMat[1][colM["OPT3_CAP"]].c_str());
266  opt_inadj[0] = atoi(tableMat[1][colM["OPT1_INP"]].c_str());
267  opt_inadj[1] = atoi(tableMat[1][colM["OPT2_INP"]].c_str());
268  opt_inadj[2] = atoi(tableMat[1][colM["OPT3_INP"]].c_str());
269  opt_ouadj[0] = atoi(tableMat[1][colM["OPT1_OUT"]].c_str());
270  opt_ouadj[1] = atoi(tableMat[1][colM["OPT2_OUT"]].c_str());
271  opt_ouadj[2] = atoi(tableMat[1][colM["OPT3_OUT"]].c_str());
272 
273  //clock phases, use bits 0-8, select the clock edged
274  clkphs1_9 = atoi(tableMat[1][colM["NORTH_CLKPHB"]].c_str()); // TO BE VERIFIED
275  clkphs10_18 = atoi(tableMat[1][colM["NORTHCENTER_CLKPHB"]].c_str()); // TO BE VERIFIED
276  clkphs19_27 = atoi(tableMat[1][colM["SOUTHCENTER_CLKPHB"]].c_str()); // TO BE VERIFIED
277  clkphs28_36 = atoi(tableMat[1][colM["SOUTH_CLKPHB"]].c_str()); // TO BE VERIFIED
278 
279  // Control register and delays for the TTCrx
280  FineDes1Del = atoi(tableMat[1][colM["REG0_TTCRX_FDLA"]].c_str());
281  FineDes2Del = atoi(tableMat[1][colM["REG1_TTCRX_FDLA"]].c_str());
282  CoarseDel = atoi(tableMat[1][colM["REG2_TTCRX_CDLA"]].c_str());
283  ClkDes2 = atoi(tableMat[1][colM["REG3_TTCRX_CLKD2"]].c_str());
284 
285  Ccntrl = atoi(tableMat[1][colM["CENTER_CTRL"]].c_str());
286  modeRegister = atoi(tableMat[1][colM["CENTER_MODE"]].c_str());
287 
288  //data Regs adjustable fifo Almost Full levels
289  Nfifo1Bzlvl = atoi(tableMat[1][colM["NORTH_FIFO1_BZ_LVL"]].c_str());
290  NCfifo1Bzlvl = atoi(tableMat[1][colM["NORTHCENTER_FIFO1_BZ_LVL"]].c_str());
291  SCfifo1Bzlvl = atoi(tableMat[1][colM["SOUTHCENTER_FIFO1_BZ_LVL"]].c_str());
292  Sfifo1Bzlvl = atoi(tableMat[1][colM["SOUTH_FIFO1_BZ_LVL"]].c_str());
293 
294  //Bits (1st 8) used to mask TBM trailer bits
295  N_TBMmask = atoi(tableMat[1][colM["NORTH_TBMMASK"]].c_str());
296  NC_TBMmask = atoi(tableMat[1][colM["NORTHCENTER_TBMMASK"]].c_str());
297  SC_TBMmask = atoi(tableMat[1][colM["SOUTHCENTER_TBMMASK"]].c_str());
298  S_TBMmask = atoi(tableMat[1][colM["SOUTH_TBMMASK"]].c_str());
299 
300  //Bits (1st 8) used to set the Private Word in the gap and filler words
301  N_Pword = atoi(tableMat[1][colM["NORTH_PWORD"]].c_str());
302  NC_Pword = atoi(tableMat[1][colM["NORTHCENTER_PWORD"]].c_str());
303  SC_Pword = atoi(tableMat[1][colM["SOUTHCENTER_PWORD"]].c_str());
304  S_Pword = atoi(tableMat[1][colM["SOUTH_PWORD"]].c_str());
305 
306  Nbaseln = atoi(tableMat[1][colM["NORTH_BADJ"]].c_str());
307  NCbaseln = atoi(tableMat[1][colM["NORTHCENTER_BADJ"]].c_str());
308  SCbaseln = atoi(tableMat[1][colM["SOUTHCENTER_BADJ"]].c_str());
309  Sbaseln = atoi(tableMat[1][colM["SOUTH_BADJ"]].c_str());
310 
311  Ncntrl = atoi(tableMat[1][colM["NORTH_CTRL"]].c_str());
312  NCcntrl = atoi(tableMat[1][colM["NORTHCENTER_CTRL"]].c_str());
313  SCcntrl = atoi(tableMat[1][colM["SOUTHCENTER_CTRL"]].c_str());
314  Scntrl = atoi(tableMat[1][colM["SOUTH_CTRL"]].c_str());
315 
316  //These bit sets the special dac mode for random triggers
317  SpecialDac = atoi(tableMat[1][colM["SPECDAC"]].c_str());
318 
319  //These bits set the number of Out of consecutive out of sync events until a TTs OOs
320  Ooslvl = atoi(tableMat[1][colM["OOS_LVL"]].c_str());
321  //These bits set the number of Empty events until a TTs Error
322  Errlvl = atoi(tableMat[1][colM["ERR_LVL"]].c_str());
323 
324  //Control Regs for setting ADC 1Vpp and 2Vpp
325  Nadcg = atoi(tableMat[1][colM["B1_ADCGN"]].c_str());
326  NCadcg = atoi(tableMat[1][colM["B2_ADCGN"]].c_str());
327  SCadcg = atoi(tableMat[1][colM["B3_ADCGN"]].c_str());
328  Sadcg = atoi(tableMat[1][colM["B4_ADCGN"]].c_str());
329  fifo3Wrnlvl = atoi(tableMat[1][colM["FIFO3_WRN_LVL"]].c_str());
330  FedTTCDelay = atoi(tableMat[1][colM["FED_MASTER_DELAY"]].c_str());
331  N_hitlimit = atoi(tableMat[1][colM["NO_HITLIMIT"]].c_str());
332  NC_hitlimit = atoi(tableMat[1][colM["NC_HITLIMIT"]].c_str());
333  SC_hitlimit = atoi(tableMat[1][colM["SC_HITLIMIT"]].c_str());
334  S_hitlimit = atoi(tableMat[1][colM["SO_HITLIMIT"]].c_str());
335  N_testreg = atoi(tableMat[1][colM["NO_TESTREG"]].c_str());
336  NC_testreg = atoi(tableMat[1][colM["NC_TESTREG"]].c_str());
337  SC_testreg = atoi(tableMat[1][colM["SC_TESTREG"]].c_str());
338  S_testreg = atoi(tableMat[1][colM["SO_TESTREG"]].c_str());
339  BusyHoldMin = atoi(tableMat[1][colM["BUSYHOLDMIN"]].c_str());
340  BusyWhenBehind = atoi(tableMat[1][colM["BUSYWHENBEHIND"]].c_str());
341  FeatureRegister = atoi(tableMat[1][colM["FEATUREREGISTER"]].c_str());
342  FIFO2Limit = atoi(tableMat[1][colM["FIFO2LIMIT"]].c_str());
343  LastDacOff = atoi(tableMat[1][colM["LASTDACOFF"]].c_str());
344  SimHitsPerRoc = atoi(tableMat[1][colM["SIMHITSPERROC"]].c_str());
345  TimeoutOROOSLimit = atoi(tableMat[1][colM["TIMEOUTOROOSLIMIT"]].c_str());
346  TriggerHoldoff = atoi(tableMat[1][colM["TRIGGERHOLDOFF"]].c_str());
347 
348  SPARE1 = atoi(tableMat[1][colM["SPARE1"]].c_str());
349  SPARE2 = atoi(tableMat[1][colM["SPARE2"]].c_str());
350  SPARE3 = atoi(tableMat[1][colM["SPARE3"]].c_str());
351  SPARE4 = atoi(tableMat[1][colM["SPARE4"]].c_str());
352  SPARE5 = atoi(tableMat[1][colM["SPARE5"]].c_str());
353  SPARE6 = atoi(tableMat[1][colM["SPARE6"]].c_str());
354  SPARE7 = atoi(tableMat[1][colM["SPARE7"]].c_str());
355  SPARE8 = atoi(tableMat[1][colM["SPARE8"]].c_str());
356  SPARE9 = atoi(tableMat[1][colM["SPARE9"]].c_str());
357  SPARE10 = atoi(tableMat[1][colM["SPARE10"]].c_str());
358 
359  } // end of 'first' condition
360  for (int r = 1; r < size[0]; r++) //Goes to every row of the FIRST Matrix (MUST BE 36, one for each FED channel)
361  {
362  //Number of ROCS per FED channel
363  NRocs[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["NUM_ROCS"]].c_str());
364  //input offset dac (one for each channel)
365  offs_dac[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["CHAN_OFFST_DAC"]].c_str());
366  //Channel delays, one for each channel, 0=15
367  DelayCh[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["CHAN_DELAY"]].c_str());
368  //Blacks and Ultra-blacks, 3 limit per channel
369  BlackHi[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["CHAN_BHIGH"]].c_str());
370  BlackLo[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["CHAN_BLOW"]].c_str());
371  Ublack[atoi(tableMat[r][colM["CHANNEL_ID"]].c_str()) - 1] = atoi(tableMat[r][colM["CHAN_UB"]].c_str());
372  }
373 
374  readDBTBMLevels(tableMat, size[0] + 1, size[1]);
375  readDBROCLevels(tableMat, size[1] + 1, size[2]);
376  Ccntrl_original = Ccntrl;
377  modeRegister_original = modeRegister;
378 
379  Ncntrl_original = Ncntrl;
380  NCcntrl_original = NCcntrl;
381  SCcntrl_original = SCcntrl;
382  Scntrl_original = Scntrl;
383 
384  Nbaseln_original = Nbaseln;
385  NCbaseln_original = NCbaseln;
386  SCbaseln_original = SCbaseln;
387  Sbaseln_original = Sbaseln;
388 
389  // Modified by MR on 17-11-2008
390  // This new variable has to be read from DB!!!!!
391  // We need to add a column in the DB. Talk to Umesh.
392  FineDes1Del = 14;
393 }
394 
395 void PixelFEDCard::readDBTBMLevels(std::vector<std::vector<std::string> > &tableMat, int firstRow, int lastRow) {
396  string mthn = "[PixelFEDCard::readDBTBMLevels()] ";
397  vector<string> ins = tableMat[firstRow];
398  map<string, int> colM;
399  vector<string> colNames;
400 
429  colNames.push_back("CONFIG_KEY");
430  colNames.push_back("KEY_TYPE");
431  colNames.push_back("KEY_ALIAS");
432  colNames.push_back("VERSION");
433  colNames.push_back("KIND_OF_COND");
434  colNames.push_back("TBM_NAME");
435  colNames.push_back("PIXEL_FED");
436  colNames.push_back("FED_CHAN");
437  colNames.push_back("TBMA_HEAD_L0");
438  colNames.push_back("TBMA_HEAD_L1");
439  colNames.push_back("TBMA_HEAD_L2");
440  colNames.push_back("TBMA_HEAD_L3");
441  colNames.push_back("TBMA_HEAD_L4");
442  colNames.push_back("TBMA_TRAIL_L0");
443  colNames.push_back("TBMA_TRAIL_L1");
444  colNames.push_back("TBMA_TRAIL_L2");
445  colNames.push_back("TBMA_TRAIL_L3");
446  colNames.push_back("TBMA_TRAIL_L4");
447  colNames.push_back("TBMA_HEAD_B");
448  colNames.push_back("TBMA_HEAD_UB");
449  colNames.push_back("TBMA_TRAIL_B");
450  colNames.push_back("TBMA_TRAIL_UB");
451  /*
452  colNames.push_back("CONFIG_KEY_ID" );
453  colNames.push_back("CONFIG_KEY" );
454  colNames.push_back("VERSION" );
455  colNames.push_back("CONDITION_DATA_SET_ID" );
456  colNames.push_back("KIND_OF_CONDITION_ID" );
457  colNames.push_back("KIND_OF_COND" );
458  colNames.push_back("PXLFED_NAME" );
459  colNames.push_back("FED_CHAN" );
460  colNames.push_back("TBM_PART_ID" );
461  colNames.push_back("TBM_SER_NUM" );
462  colNames.push_back("PANEL_NAME" );
463  colNames.push_back("HUB_ADDRS" );
464  colNames.push_back("TBMA_HEAD_L0" );
465  colNames.push_back("TBMA_HEAD_L1" );
466  colNames.push_back("TBMA_HEAD_L2" );
467  colNames.push_back("TBMA_HEAD_L3" );
468  colNames.push_back("TBMA_HEAD_L4" );
469  colNames.push_back("TBMA_TRAIL_L0" );
470  colNames.push_back("TBMA_TRAIL_L1" );
471  colNames.push_back("TBMA_TRAIL_L2" );
472  colNames.push_back("TBMA_TRAIL_L3" );
473  colNames.push_back("TBMA_TRAIL_L4" );
474 */
475  // Retrieve header row and cross check that everyfield is there.
476  for (unsigned int c = 0; c < ins.size(); c++) {
477  for (unsigned int n = 0; n < colNames.size(); n++) {
478  if (tableMat[firstRow][c] == colNames[n]) {
479  colM[colNames[n]] = c;
480  break;
481  }
482  }
483  } //end for
484  for (unsigned int n = 0; n < colNames.size(); n++) {
485  if (colM.find(colNames[n]) == colM.end()) {
486  std::cerr << mthn << "\tCouldn't find in the database the column with name " << colNames[n] << std::endl;
487  assert(0);
488  }
489  }
490  for (int r = firstRow + 1; r < lastRow; r++) //Goes to every row of the Matrix (MUST BE 36, one for each FED channel)
491  {
492  //Signal levels for the TBM, one per channel
493  TBM_L0[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_HEAD_L0"]].c_str());
494  TBM_L1[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_HEAD_L1"]].c_str());
495  TBM_L2[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_HEAD_L2"]].c_str());
496  TBM_L3[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_HEAD_L3"]].c_str());
497  TBM_L4[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_HEAD_L4"]].c_str());
498  TRL_L0[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_TRAIL_L0"]].c_str());
499  TRL_L1[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_TRAIL_L1"]].c_str());
500  TRL_L2[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_TRAIL_L2"]].c_str());
501  TRL_L3[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_TRAIL_L3"]].c_str());
502  TRL_L4[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1] = atoi(tableMat[r][colM["TBMA_TRAIL_L4"]].c_str());
503  }
504 }
505 
506 void PixelFEDCard::readDBROCLevels(std::vector<std::vector<std::string> > &tableMat, int firstRow, int lastRow) {
507  string mthn = "[PixelFEDCard::readDBROCLevels()] ";
508  map<string, int> colM;
509  vector<string> colNames;
510 
533  colNames.push_back("CONFIG_KEY");
534  colNames.push_back("KEY_TYPE");
535  colNames.push_back("KEY_ALIAS");
536  colNames.push_back("VERSION");
537  colNames.push_back("KIND_OF_COND");
538  colNames.push_back("ROC_NAME");
539  colNames.push_back("FED_ROC_NUM");
540  colNames.push_back("PIXEL_FED");
541  colNames.push_back("FED_CHAN");
542  colNames.push_back("ROC_L0");
543  colNames.push_back("ROC_L1");
544  colNames.push_back("ROC_L2");
545  colNames.push_back("ROC_L3");
546  colNames.push_back("ROC_L4");
547  colNames.push_back("ROC_B");
548  colNames.push_back("ROC_UB");
549  /*
550  colNames.push_back("CONFIG_KEY_ID" );
551  colNames.push_back("CONFIG_KEY" );
552  colNames.push_back("VERSION" );
553  colNames.push_back("KIND_OF_COND" );
554  colNames.push_back("PXLFED_NAME" );
555  colNames.push_back("FED_CHAN" );
556  colNames.push_back("AOH_CHAN" );
557  colNames.push_back("ROC_NAME" );
558  colNames.push_back("HUB_ADDRS" );
559  colNames.push_back("PORT_NUMBER" );
560  colNames.push_back("ROC_I2C_ADDR" );
561  colNames.push_back("GEOM_ROC_NUM" );
562  colNames.push_back("FED_ROC_NUM" );
563  colNames.push_back("ROC_L0" );
564  colNames.push_back("ROC_L1" );
565  colNames.push_back("ROC_L2" );
566  colNames.push_back("ROC_L3" );
567  colNames.push_back("ROC_L4" );
568 */
569  // Retrieve header row and cross check that everyfield is there.
570  for (unsigned int c = 0; c < tableMat[firstRow].size(); c++) {
571  for (unsigned int n = 0; n < colNames.size(); n++) {
572  if (tableMat[firstRow][c] == colNames[n]) {
573  colM[colNames[n]] = c;
574  break;
575  }
576  }
577  } //end for
578  for (unsigned int n = 0; n < colNames.size(); n++) {
579  if (colM.find(colNames[n]) == colM.end()) {
580  std::cerr << mthn << "\tCouldn't find in the database the column with name " << colNames[n] << std::endl;
581  assert(0);
582  }
583  }
584  // Address levels 1 per channel (36) per roc(max=26)
585  // int ROC_L0[36][26],ROC_L1[36][26],ROC_L2[36][26],ROC_L3[36][26],ROC_L4[36][26];
586 
587  for (int r = firstRow + 1; r < lastRow; r++) //Goes to every row of the Matrix (MUST BE 36, one for each FED channel)
588  {
589  ROC_L0[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] =
590  atoi(tableMat[r][colM["ROC_L0"]].c_str());
591  ROC_L1[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] =
592  atoi(tableMat[r][colM["ROC_L1"]].c_str());
593  ROC_L2[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] =
594  atoi(tableMat[r][colM["ROC_L2"]].c_str());
595  ROC_L3[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] =
596  atoi(tableMat[r][colM["ROC_L3"]].c_str());
597  ROC_L4[atoi(tableMat[r][colM["FED_CHAN"]].c_str()) - 1][atoi(tableMat[r][colM["FED_ROC_NUM"]].c_str())] =
598  atoi(tableMat[r][colM["ROC_L4"]].c_str());
599  }
600 }
601 
602 // Read the configuration parameters from file
603 PixelFEDCard::PixelFEDCard(string fileName) : PixelConfigBase(" ", " ", " ") {
604  std::string mthn = "]\t[PixelFEDCard::PixelFEDCard()]\t\t\t\t ";
605  //const bool localDEBUG = true;
606  const bool localDEBUG = false;
607 
608  // Added by Dario (March 26th, 2008): insure variables are all cleared before read-in
609  clear();
610 
611  // cout << __LINE__ << "]\t" << mthn <<" Get setup parameters from file "<<fileName<<endl;
612  FILE *infile = fopen((fileName.c_str()), "r");
613  if (infile == nullptr)
614  throw std::runtime_error("Failed to open FED Card parameter file: " + fileName);
615 
616  //Fed Base Address
617  fscanf(infile, "FED Base address :%lx\n", &FEDBASE_0);
618  fscanf(infile, "FEDID Number :%lx\n", &fedNumber);
619 
620  // if(localDEBUG) cout << __LINE__ << mthn << "FED Base address, FED # : " << std::hex << FEDBASE_0 << std::dec << std::endl ;
621  // if(localDEBUG) printf("FED Base address, FED # :%lx\n",FEDBASE_0);
622  //if(FEDBASE != FEDBASE_0) cout<< __LINE__ << "]\t" << mthn << " Inconsistent FED base address?"<<endl;
623  // if(localDEBUG) cout << __LINE__ << mthn << "FEDID # : " << std::hex << fedNumber << std::dec << std::endl ;
624  // if(localDEBUG) printf("FEDID # :%lx\n",fedNumber);
625 
626  // Number of ROCs
627  int ijx = 0;
628  for (int i = 0; i < 36; i++) {
629  ijx = i + 1;
630  fscanf(infile, "Number of ROCs Chnl %d:%d \n", &ijx, &NRocs[i]);
631  if (localDEBUG)
632  printf("Number of ROCs per Chnl %d:%d \n", ijx, NRocs[i]);
633  }
634 
635  //Settable optical input parameters
636  fscanf(infile, "Optical reciever 1 Capacitor Adjust(0-3):%d\n", &opt_cap[0]);
637  fscanf(infile, "Optical reciever 2 Capacitor Adjust(0-3):%d\n", &opt_cap[1]);
638  fscanf(infile, "Optical reciever 3 Capacitor Adjust(0-3):%d\n", &opt_cap[2]);
639  fscanf(infile, "Optical reciever 1 Input Offset (0-15) :%d\n", &opt_inadj[0]);
640  fscanf(infile, "Optical reciever 2 Input Offset (0-15) :%d\n", &opt_inadj[1]);
641  fscanf(infile, "Optical reciever 3 Input Offset (0-15) :%d\n", &opt_inadj[2]);
642  fscanf(infile, "Optical reciever 1 Output Offset (0-3) :%d\n", &opt_ouadj[0]);
643  fscanf(infile, "Optical reciever 2 Output Offset (0-3) :%d\n", &opt_ouadj[1]);
644  fscanf(infile, "Optical reciever 3 Output Offset (0-3) :%d\n", &opt_ouadj[2]);
645 
646  if (localDEBUG) {
647  printf("Optical reciever 1 Capacitor Adjust(0-3):%d\n", opt_cap[0]);
648  printf("Optical reciever 2 Capacitor Adjust(0-3):%d\n", opt_cap[1]);
649  printf("Optical reciever 3 Capacitor Adjust(0-3):%d\n", opt_cap[2]);
650  printf("Optical reciever 1 Input Offset (0-15) :%d\n", opt_inadj[0]);
651  printf("Optical reciever 2 Input Offset (0-15) :%d\n", opt_inadj[1]);
652  printf("Optical reciever 3 Input Offset (0-15) :%d\n", opt_inadj[2]);
653  printf("Optical reciever 1 Output Offset (0-3) :%d\n", opt_ouadj[0]);
654  printf("Optical reciever 2 Output Offset (0-3) :%d\n", opt_ouadj[1]);
655  printf("Optical reciever 3 Output Offset (0-3) :%d\n", opt_ouadj[2]);
656  }
657 
658  //input offset dac
659  for (int i = 0; i < 36; i++) {
660  fscanf(infile, "Offset DAC channel %d:%d\n", &ijx, &offs_dac[i]);
661  if (localDEBUG)
662  printf("Offset DAC channel %d:%d\n", i + 1, offs_dac[i]);
663  }
664 
665  //clock phases
666  fscanf(infile, "Clock Phase Bits ch 1-9:%x\n", &clkphs1_9);
667  fscanf(infile, "Clock Phase Bits ch 10-18:%x\n", &clkphs10_18);
668  fscanf(infile, "Clock Phase Bits ch 19-27:%x\n", &clkphs19_27);
669  fscanf(infile, "Clock Phase Bits ch 28-36:%x\n", &clkphs28_36);
670  if (localDEBUG)
671  printf("Clock Phase Bits ch 1-9:%x\n", clkphs1_9);
672  if (localDEBUG)
673  printf("Clock Phase Bits ch 10-18:%x\n", clkphs10_18);
674  if (localDEBUG)
675  printf("Clock Phase Bits ch 19-27:%x\n", clkphs19_27);
676  if (localDEBUG)
677  printf("Clock Phase Bits ch 28-36:%x\n", clkphs28_36);
678 
679  //Blacks
680  for (int i = 0; i < 36; i++) {
681  fscanf(infile, "Black HiThold ch %d:%d \n", &ijx, &BlackHi[i]);
682  fscanf(infile, "Black LoThold ch %d:%d \n", &ijx, &BlackLo[i]);
683  fscanf(infile, "ULblack Thold ch %d:%d \n", &ijx, &Ublack[i]);
684  if (localDEBUG)
685  printf("Black HiThold ch %d:%d\n", ijx, BlackHi[i]);
686  if (localDEBUG)
687  printf("Black LoThold ch %d:%d\n", ijx, BlackLo[i]);
688  if (localDEBUG)
689  printf("ULblack Thold ch %d:%d\n", ijx, Ublack[i]);
690  }
691 
692  //Channel delays
693  for (int i = 0; i < 36; i++) {
694  fscanf(infile, "Delay channel %d(0-15):%d\n", &ijx, &DelayCh[i]);
695  if (localDEBUG)
696  printf("Delay channel %d(0-15):%d\n", i + 1, DelayCh[i]);
697  }
698 
699  //Signal levels
700  for (int i = 0; i < 36; i++) {
701  fscanf(infile, "TBM level 0 Channel %d:%d\n", &ijx, &TBM_L0[i]);
702  fscanf(infile, "TBM level 1 Channel %d:%d\n", &ijx, &TBM_L1[i]);
703  fscanf(infile, "TBM level 2 Channel %d:%d\n", &ijx, &TBM_L2[i]);
704  fscanf(infile, "TBM level 3 Channel %d:%d\n", &ijx, &TBM_L3[i]);
705  fscanf(infile, "TBM level 4 Channel %d:%d\n", &ijx, &TBM_L4[i]);
706  if (localDEBUG)
707  printf("TBM level 0 Channel %d:%d\n", ijx, TBM_L0[i]);
708  if (localDEBUG)
709  printf("TBM level 1 Channel %d:%d\n", ijx, TBM_L1[i]);
710  if (localDEBUG)
711  printf("TBM level 2 Channel %d:%d\n", ijx, TBM_L2[i]);
712  if (localDEBUG)
713  printf("TBM level 3 Channel %d:%d\n", ijx, TBM_L3[i]);
714  if (localDEBUG)
715  printf("TBM level 4 Channel %d:%d\n", ijx, TBM_L4[i]);
716 
717  int ijy = 0;
718  for (int j = 0; j < NRocs[i]; j++) {
719  fscanf(infile, "ROC%d level 0 Channel %d :%d\n", &ijy, &ijx, &ROC_L0[i][j]);
720  fscanf(infile, "ROC%d level 1 Channel %d :%d\n", &ijy, &ijx, &ROC_L1[i][j]);
721  fscanf(infile, "ROC%d level 2 Channel %d :%d\n", &ijy, &ijx, &ROC_L2[i][j]);
722  fscanf(infile, "ROC%d level 3 Channel %d :%d\n", &ijy, &ijx, &ROC_L3[i][j]);
723  fscanf(infile, "ROC%d level 4 Channel %d :%d\n", &ijy, &ijx, &ROC_L4[i][j]);
724  if (localDEBUG)
725  printf("ROC%d level 0 Channel %d :%d\n", ijy, ijx, ROC_L0[i][j]);
726  if (localDEBUG)
727  printf("ROC%d level 1 Channel %d :%d\n", ijy, ijx, ROC_L1[i][j]);
728  if (localDEBUG)
729  printf("ROC%d level 2 Channel %d :%d\n", ijy, ijx, ROC_L2[i][j]);
730  if (localDEBUG)
731  printf("ROC%d level 3 Channel %d :%d\n", ijy, ijx, ROC_L3[i][j]);
732  if (localDEBUG)
733  printf("ROC%d level 4 Channel %d :%d\n", ijy, ijx, ROC_L4[i][j]);
734  }
735 
736  fscanf(infile, "TRLR level 0 Channel %d:%d\n", &ijx, &TRL_L0[i]);
737  fscanf(infile, "TRLR level 1 Channel %d:%d\n", &ijx, &TRL_L1[i]);
738  fscanf(infile, "TRLR level 2 Channel %d:%d\n", &ijx, &TRL_L2[i]);
739  fscanf(infile, "TRLR level 3 Channel %d:%d\n", &ijx, &TRL_L3[i]);
740  fscanf(infile, "TRLR level 4 Channel %d:%d\n", &ijx, &TRL_L4[i]);
741  if (localDEBUG)
742  printf("TRLR level 0 Channel %d:%d\n", ijx, TRL_L0[i]);
743  if (localDEBUG)
744  printf("TRLR level 1 Channel %d:%d\n", ijx, TRL_L1[i]);
745  if (localDEBUG)
746  printf("TRLR level 2 Channel %d:%d\n", ijx, TRL_L2[i]);
747  if (localDEBUG)
748  printf("TRLR level 3 Channel %d:%d\n", ijx, TRL_L3[i]);
749  if (localDEBUG)
750  printf("TRLR level 4 Channel %d:%d\n", ijx, TRL_L4[i]);
751  }
752 
753  //These bits turn off(1) and on(0) channels
754  fscanf(infile, "Channel Enbable bits chnls 1-9 (on = 0):%x\n", &Ncntrl);
755  fscanf(infile, "Channel Enbable bits chnls 10-18(on = 0):%x\n", &NCcntrl);
756  fscanf(infile, "Channel Enbable bits chnls 19-27(on = 0):%x\n", &SCcntrl);
757  fscanf(infile, "Channel Enbable bits chnls 28-36(on = 0):%x\n", &Scntrl);
758  if (localDEBUG)
759  printf("Channel Enbable bits chnls 1-9 (on = 0):%x\n", Ncntrl);
760  if (localDEBUG)
761  printf("Channel Enbable bits chnls 10-18(on = 0):%x\n", NCcntrl);
762  if (localDEBUG)
763  printf("Channel Enbable bits chnls 19-27(on = 0):%x\n", SCcntrl);
764  if (localDEBUG)
765  printf("Channel Enbable bits chnls 28-36(on = 0):%x\n", Scntrl);
766 
767  //These are delays to the TTCrx
768  fscanf(infile, "TTCrx Coarse Delay Register 2:%d\n", &CoarseDel);
769  fscanf(infile, "TTCrc ClkDes2 Register 3:%x\n", &ClkDes2);
770  fscanf(infile, "TTCrc Fine Dlay ClkDes2 Reg 1:%d\n", &FineDes2Del);
771  if (localDEBUG)
772  printf("TTCrx Coarse Delay Register 2:%d\n", CoarseDel);
773  if (localDEBUG)
774  printf("TTCrc ClkDes2 Register 3:%x\n", ClkDes2);
775  if (localDEBUG)
776  printf("TTCrc Fine Dlay ClkDes2 Reg 1:%d\n", FineDes2Del);
777 
778  // Control register
779  fscanf(infile, "Center Chip Control Reg:%x\n", &Ccntrl);
780  if (localDEBUG)
781  printf("Control Reg:0x%x\n", Ccntrl);
782  fscanf(infile, "Initial Slink DAQ mode:%d\n", &modeRegister);
783  if (localDEBUG)
784  printf("Mode Reg:%d\n", modeRegister);
785 
786  //These bits set ADC Gain/Range 1Vpp(0) and 2Vpp(1) for channels
787  fscanf(infile, "Channel ADC Gain bits chnls 1-12(1Vpp = 0):%x\n", &Nadcg);
788  fscanf(infile, "Channel ADC Gain bits chnls 13-20(1Vpp = 0):%x\n", &NCadcg);
789  fscanf(infile, "Channel ADC Gain bits chnls 21-28(1Vpp = 0):%x\n", &SCadcg);
790  fscanf(infile, "Channel ADC Gain bits chnls 29-36(1Vpp = 0):%x\n", &Sadcg);
791  if (localDEBUG)
792  printf("Channel ADC Gain bits chnls 1-12(1Vpp = 0):%x\n", Nadcg);
793  if (localDEBUG)
794  printf("Channel ADC Gain bits chnls 13-20(1Vpp = 0):%x\n", NCadcg);
795  if (localDEBUG)
796  printf("Channel ADC Gain bits chnls 21-28(1Vpp = 0):%x\n", SCadcg);
797  if (localDEBUG)
798  printf("Channel ADC Gain bits chnls 29-36(1Vpp = 0):%x\n", Sadcg);
799 
800  //These bits set Baseline adjustment value (common by FPGA)//can turn on by channel
801  fscanf(infile, "Channel Baseline Enbable chnls 1-9 (on = (0x1ff<<16)+):%x\n", &Nbaseln);
802  fscanf(infile, "Channel Baseline Enbable chnls 10-18(on = (0x1ff<<16)+):%x\n", &NCbaseln);
803  fscanf(infile, "Channel Baseline Enbable chnls 19-27(on = (0x1ff<<16)+):%x\n", &SCbaseln);
804  fscanf(infile, "Channel Baseline Enbable chnls 28-36(on = (0x1ff<<16)+):%x\n", &Sbaseln);
805  if (localDEBUG)
806  printf("Channel Baseline Enbable chnls 1-9 (on = (0x1ff<<16)+):%x\n", Nbaseln);
807  if (localDEBUG)
808  printf("Channel Baseline Enbable chnls 10-18(on = (0x1ff<<16)+):%x\n", NCbaseln);
809  if (localDEBUG)
810  printf("Channel Baseline Enbable chnls 19-27(on = (0x1ff<<16)+):%x\n", SCbaseln);
811  if (localDEBUG)
812  printf("Channel Baseline Enbable chnls 28-36(on = (0x1ff<<16)+):%x\n", Sbaseln);
813 
814  //These bits set TBM trailer mask (common by FPGA)
815  fscanf(infile, "TBM trailer mask chnls 1-9 (0xff = all masked):%x\n", &N_TBMmask);
816  fscanf(infile, "TBM trailer mask chnls 10-18(0xff = all masked):%x\n", &NC_TBMmask);
817  fscanf(infile, "TBM trailer mask chnls 19-27(0xff = all masked):%x\n", &SC_TBMmask);
818  fscanf(infile, "TBM trailer mask chnls 28-36(0xff = all masked):%x\n", &S_TBMmask);
819  if (localDEBUG)
820  printf("TBM trailer mask chnls 1-9 (0xff = all masked):%x\n", N_TBMmask);
821  if (localDEBUG)
822  printf("TBM trailer mask chnls 10-18(0xff = all masked):%x\n", NC_TBMmask);
823  if (localDEBUG)
824  printf("TBM trailer mask chnls 19-27(0xff = all masked):%x\n", SC_TBMmask);
825  if (localDEBUG)
826  printf("TBM trailer mask chnls 28-36(0xff = all masked):%x\n", S_TBMmask);
827 
828  //These bits set the Private fill/gap word value (common by FPGA)
829  fscanf(infile, "Private 8 bit word chnls 1-9 :%x\n", &N_Pword);
830  fscanf(infile, "Private 8 bit word chnls 10-18:%x\n", &NC_Pword);
831  fscanf(infile, "Private 8 bit word chnls 19-27:%x\n", &SC_Pword);
832  fscanf(infile, "Private 8 bit word chnls 28-36:%x\n", &S_Pword);
833  if (localDEBUG)
834  printf("Private 8 bit word chnls 1-9 :%x\n", N_Pword);
835  if (localDEBUG)
836  printf("Private 8 bit word chnls 10-18:%x\n", NC_Pword);
837  if (localDEBUG)
838  printf("Private 8 bit word chnls 19-27:%x\n", SC_Pword);
839  if (localDEBUG)
840  printf("Private 8 bit word chnls 28-36:%x\n", S_Pword);
841 
842  //These bit sets the special dac mode for random triggers
843  fscanf(infile, "Special Random testDAC mode (on = 0x1, off=0x0):%x\n", &SpecialDac);
844  if (localDEBUG)
845  printf("Special Random testDAC mode (on = 0x1, off=0x0):%x\n", SpecialDac);
846 
847  //These bits set the number of Out of consecutive out of sync events until a TTs OOs
848  fscanf(infile, "Number of Consecutive (max 1023) Out of Syncs till TTs OOS set:%d\n", &Ooslvl);
849  if (localDEBUG)
850  printf("Number of Consecutive (max 1023) Out of Syncs till TTs OOS set:%d\n", Ooslvl);
851 
852  //These bits set the number of Empty events until a TTs Error
853  fscanf(infile, "Number of Consecutive (max 1023) Empty events till TTs ERR set:%d\n", &Errlvl);
854  if (localDEBUG)
855  printf("Number of Consecutive (max 1023) Empty events till TTs ERR set:%d\n", Errlvl);
856 
857  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 N
858  fscanf(infile, "N Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", &Nfifo1Bzlvl);
859  if (localDEBUG)
860  printf("N Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", Nfifo1Bzlvl);
861 
862  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 NC
863  fscanf(infile, "NC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", &NCfifo1Bzlvl);
864  if (localDEBUG)
865  printf("NC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", NCfifo1Bzlvl);
866 
867  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 SC
868  fscanf(infile, "SC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", &SCfifo1Bzlvl);
869  if (localDEBUG)
870  printf("SC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", SCfifo1Bzlvl);
871 
872  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 S
873  fscanf(infile, "S Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", &Sfifo1Bzlvl);
874  if (localDEBUG)
875  printf("S Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", Sfifo1Bzlvl);
876 
877  //These bits set the Almost Full level in fifo-3, Almost full = TTs WARN in fifo-3
878  fscanf(infile, "Fifo-3 almost full level,sets TTs WARN (max 8191):%d\n", &fifo3Wrnlvl);
879  if (localDEBUG)
880  printf("Fifo-3 almost full level,sets TTs WARN (max 8191):%d\n", fifo3Wrnlvl);
881 
882  fscanf(infile, "FED Master delay 0=0,1=32,2=48,3=64:%d\n", &FedTTCDelay);
883  if (localDEBUG)
884  printf("FED Master delay 0=0,1=32,2=48,3=64:%d\n", FedTTCDelay);
885 
886  fscanf(infile, "TTCrx Register 0 fine delay ClkDes1:%d\n", &FineDes1Del);
887  if (localDEBUG)
888  printf("TTCrx Register 0 fine delay ClkDes1:%d\n", FineDes1Del);
889 
890  int checkword = 0;
891  fscanf(infile, "Params FED file check word:%d\n", &checkword);
892  if (checkword != 90508 && checkword != 91509 && checkword != 20211)
893  cout << __LINE__ << "]\t" << mthn << "FEDID: " << fedNumber << " Params FED File read error. Checkword read "
894  << checkword << " check word expected 090508 or 91509 or 20211" << endl;
895  assert((checkword == 90508) | (checkword == 91509) | (checkword == 20211));
896 
897  if (localDEBUG)
898  cout << __LINE__ << "]\t" << mthn << "Params FED file check word: " << checkword << endl;
899 
900  //These bits set the hit limit in fifo-1 for an event
901 
902  if (checkword == 20211) {
903  //These bits set the hit limit in fifo-1 for an event
904  fscanf(infile, "N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &N_hitlimit);
905  if (localDEBUG)
906  printf("N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", N_hitlimit);
907  fscanf(infile, "NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &NC_hitlimit);
908  if (localDEBUG)
909  printf("NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", NC_hitlimit);
910  fscanf(infile, "SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &SC_hitlimit);
911  if (localDEBUG)
912  printf("SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", SC_hitlimit);
913  fscanf(infile, "S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &S_hitlimit);
914  if (localDEBUG)
915  printf("S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", S_hitlimit);
916  //These bits allow a ROC to be skipped (1/fpga)
917 
918  fscanf(infile, "Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &N_testreg);
919  if (localDEBUG)
920  printf("Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", N_testreg);
921  fscanf(infile, "Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &NC_testreg);
922  if (localDEBUG)
923  printf("Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", NC_testreg);
924  fscanf(infile, "Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &SC_testreg);
925  if (localDEBUG)
926  printf("Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", SC_testreg);
927  fscanf(infile, "Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &S_testreg);
928  if (localDEBUG)
929  printf("Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", S_testreg);
930 
931  fscanf(infile, "Set BUSYWHENBEHIND by this many triggers with timeouts:%d\n", &BusyWhenBehind);
932  if (localDEBUG)
933  printf("Set BUSYWHENBEHIND by this many triggers with timeouts:%d\n", BusyWhenBehind);
934 
935  fscanf(infile, "D[0]=1 enable fed-stuck reset D[1]=1 disable ev# protect(dont):%x\n", &FeatureRegister);
936  if (localDEBUG)
937  printf("D[0]=1 enable fed-stuck reset D[1]=1 disable ev# protect(dont):%x\n", FeatureRegister);
938 
939  fscanf(infile, "Limit for fifo-2 almost full (point for the TTS flag):%x\n", &FIFO2Limit);
940  if (localDEBUG)
941  printf("Limit for fifo-2 almost full (point for the TTS flag):%x\n", FIFO2Limit);
942 
943  fscanf(infile, "Limit for consecutive timeout OR OOSs:%d\n", &TimeoutOROOSLimit);
944  if (localDEBUG)
945  printf("Limit for consecutive timeout OR OOSs:%d\n", TimeoutOROOSLimit);
946 
947  fscanf(infile, "Turn off filling of lastdac fifos(exc 1st ROC):%d\n", &LastDacOff);
948  if (localDEBUG)
949  printf("Turn off filling of lastdac fifos(exc 1st ROC):%d\n", LastDacOff);
950 
951  fscanf(infile, "Number of simulated hits per ROC for internal generator:%d\n", &SimHitsPerRoc);
952  if (localDEBUG)
953  printf("Number of simulated hits per ROC for internal generator:%d\n", SimHitsPerRoc);
954 
955  fscanf(infile, "Miniumum hold time for busy (changing definition):%d\n", &BusyHoldMin);
956  if (localDEBUG)
957  printf("Miniumum hold time for busy (changing definition):%d\n", BusyHoldMin);
958 
959  fscanf(infile, "Trigger Holdoff in units of 25us(0=none):%d\n", &TriggerHoldoff);
960  if (localDEBUG)
961  printf("Trigger Holdoff in units of 25us(0=none):%d\n", TriggerHoldoff);
962 
963  fscanf(infile, "Spare fedcard input 1:%d\n", &SPARE1);
964  if (localDEBUG)
965  printf("Spare fedcard input 1:%d\n", SPARE1);
966  fscanf(infile, "Spare fedcard input 2:%d\n", &SPARE2);
967  if (localDEBUG)
968  printf("Spare fedcard input 2:%d\n", SPARE2);
969  fscanf(infile, "Spare fedcard input 3:%d\n", &SPARE3);
970  if (localDEBUG)
971  printf("Spare fedcard input 3:%d\n", SPARE3);
972  fscanf(infile, "Spare fedcard input 4:%d\n", &SPARE4);
973  if (localDEBUG)
974  printf("Spare fedcard input 4:%d\n", SPARE4);
975  fscanf(infile, "Spare fedcard input 5:%d\n", &SPARE5);
976  if (localDEBUG)
977  printf("Spare fedcard input 5:%d\n", SPARE5);
978  fscanf(infile, "Spare fedcard input 6:%d\n", &SPARE6);
979  if (localDEBUG)
980  printf("Spare fedcard input 6:%d\n", SPARE6);
981  fscanf(infile, "Spare fedcard input 7:%d\n", &SPARE7);
982  if (localDEBUG)
983  printf("Spare fedcard input 7:%d\n", SPARE7);
984  fscanf(infile, "Spare fedcard input 8:%d\n", &SPARE8);
985  if (localDEBUG)
986  printf("Spare fedcard input 8:%d\n", SPARE8);
987  fscanf(infile, "Spare fedcard input 9:%d\n", &SPARE9);
988  if (localDEBUG)
989  printf("Spare fedcard input 9:%d\n", SPARE9);
990  fscanf(infile, "Spare fedcard input 10:%d\n", &SPARE10);
991  if (localDEBUG)
992  printf("Spare fedcard input 10:%d\n", SPARE10);
993 
994  } else if (checkword == 91509) {
995  //These bits set the hit limit in fifo-1 for an event
996  fscanf(infile, "N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &N_hitlimit);
997  if (localDEBUG)
998  printf("N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", N_hitlimit);
999  fscanf(infile, "NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &NC_hitlimit);
1000  if (localDEBUG)
1001  printf("NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", NC_hitlimit);
1002  fscanf(infile, "SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &SC_hitlimit);
1003  if (localDEBUG)
1004  printf("SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", SC_hitlimit);
1005  fscanf(infile, "S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", &S_hitlimit);
1006  if (localDEBUG)
1007  printf("S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n", S_hitlimit);
1008  //These bits allow a ROC to be skipped (1/fpga)
1009 
1010  fscanf(infile, "Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &N_testreg);
1011  if (localDEBUG)
1012  printf("Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", N_testreg);
1013  fscanf(infile, "Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &NC_testreg);
1014  if (localDEBUG)
1015  printf("Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", NC_testreg);
1016  fscanf(infile, "Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &SC_testreg);
1017  if (localDEBUG)
1018  printf("Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", SC_testreg);
1019  fscanf(infile, "Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", &S_testreg);
1020  if (localDEBUG)
1021  printf("Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", S_testreg);
1022 
1023  BusyWhenBehind = 8;
1024  FeatureRegister = 0x1;
1025  FIFO2Limit = 0x1C00;
1026  TimeoutOROOSLimit = 200;
1027  LastDacOff = 0;
1028  SimHitsPerRoc = 0;
1029  BusyHoldMin = 0;
1030  TriggerHoldoff = 0;
1031  SPARE1 = 0;
1032  SPARE2 = 0;
1033  SPARE3 = 0;
1034  SPARE4 = 0;
1035  SPARE5 = 0;
1036  SPARE6 = 0;
1037  SPARE7 = 0;
1038  SPARE8 = 0;
1039  SPARE9 = 0;
1040  SPARE10 = 0;
1041 
1042  } else {
1043  N_hitlimit = 192;
1044  NC_hitlimit = 192;
1045  SC_hitlimit = 192;
1046  S_hitlimit = 192;
1047 
1048  N_testreg = 0;
1049  NC_testreg = 0;
1050  SC_testreg = 0;
1051  S_testreg = 0;
1052 
1053  BusyWhenBehind = 8;
1054  FeatureRegister = 0x1;
1055  FIFO2Limit = 0x1c00;
1056  TimeoutOROOSLimit = 200;
1057  LastDacOff = 0;
1058  SimHitsPerRoc = 0;
1059  BusyHoldMin = 0;
1060  TriggerHoldoff = 0;
1061  SPARE1 = 0;
1062  SPARE2 = 0;
1063  SPARE3 = 0;
1064  SPARE4 = 0;
1065  SPARE5 = 0;
1066  SPARE6 = 0;
1067  SPARE7 = 0;
1068  SPARE8 = 0;
1069  SPARE9 = 0;
1070  SPARE10 = 0;
1071  }
1072 
1073  fclose(infile);
1074 
1075  Ccntrl_original = Ccntrl;
1076  modeRegister_original = modeRegister;
1077 
1078  Ncntrl_original = Ncntrl;
1079  NCcntrl_original = NCcntrl;
1080  SCcntrl_original = SCcntrl;
1081  Scntrl_original = Scntrl;
1082 
1083  Nbaseln_original = Nbaseln;
1084  NCbaseln_original = NCbaseln;
1085  SCbaseln_original = SCbaseln;
1086  Sbaseln_original = Sbaseln;
1087 
1088  return;
1089 }
1090 
1091 //==================================================================================
1092 // Added by Dario (March 26th 2008)
1093 void PixelFEDCard::clear(void) {
1094  FEDBASE_0 = 0;
1095  fedNumber = 999;
1096  for (int i = 0; i < 36; i++) {
1097  NRocs[i] = 0;
1098  offs_dac[i] = 0;
1099  BlackHi[i] = 0;
1100  BlackLo[i] = 0;
1101  Ublack[i] = 0;
1102  DelayCh[i] = 0;
1103  TBM_L0[i] = 0;
1104  TBM_L1[i] = 0;
1105  TBM_L2[i] = 0;
1106  TBM_L3[i] = 0;
1107  TBM_L4[i] = 0;
1108  TRL_L0[i] = 0;
1109  TRL_L1[i] = 0;
1110  TRL_L2[i] = 0;
1111  TRL_L3[i] = 0;
1112  TRL_L4[i] = 0;
1113  }
1114  for (int i = 0; i < 3; i++) {
1115  opt_cap[i] = 0;
1116  opt_inadj[i] = 0;
1117  opt_ouadj[i] = 0;
1118  }
1119  clkphs1_9 = 0;
1120  clkphs10_18 = 0;
1121  clkphs19_27 = 0;
1122  clkphs28_36 = 0;
1123 
1124  for (int i = 0; i < 36; i++) {
1125  for (int j = 0; j < 26; j++) {
1126  ROC_L0[i][j] = 0;
1127  ROC_L1[i][j] = 0;
1128  ROC_L2[i][j] = 0;
1129  ROC_L3[i][j] = 0;
1130  ROC_L4[i][j] = 0;
1131  }
1132  }
1133  Ncntrl = 0;
1134  NCcntrl = 0;
1135  SCcntrl = 0;
1136  Scntrl = 0;
1137  CoarseDel = 0;
1138  ClkDes2 = 0;
1139  FineDes2Del = 0;
1140  FineDes1Del = 0;
1141  Ccntrl = 0;
1142  modeRegister = 0;
1143  Nadcg = 0;
1144  NCadcg = 0;
1145  SCadcg = 0;
1146  Sadcg = 0;
1147  Nbaseln = 0;
1148  NCbaseln = 0;
1149  SCbaseln = 0;
1150  Sbaseln = 0;
1151  N_TBMmask = 0;
1152  NC_TBMmask = 0;
1153  SC_TBMmask = 0;
1154  S_TBMmask = 0;
1155  N_Pword = 0;
1156  NC_Pword = 0;
1157  SC_Pword = 0;
1158  S_Pword = 0;
1159  SpecialDac = 0;
1160  Ooslvl = 0;
1161  Errlvl = 0;
1162  Nfifo1Bzlvl = 0;
1163  NCfifo1Bzlvl = 0;
1164  SCfifo1Bzlvl = 0;
1165  Sfifo1Bzlvl = 0;
1166  fifo3Wrnlvl = 0;
1167 
1168  BusyHoldMin = 0;
1169  BusyWhenBehind = 0;
1170  FeatureRegister = 0;
1171  FIFO2Limit = 0;
1172  LastDacOff = 0;
1173  SimHitsPerRoc = 0;
1174  TimeoutOROOSLimit = 0;
1175  TriggerHoldoff = 0;
1176 
1177  SPARE1 = 0;
1178  SPARE2 = 0;
1179  SPARE3 = 0;
1180  SPARE4 = 0;
1181  SPARE5 = 0;
1182  SPARE6 = 0;
1183  SPARE7 = 0;
1184  SPARE8 = 0;
1185  SPARE9 = 0;
1186  SPARE10 = 0;
1187 }
1188 //==================================================================================
1189 
1190 void PixelFEDCard::writeASCII(std::string dir) const {
1191  std::string mthn = "[PixelFEDCard::writeASCII()]\t\t\t\t ";
1192 
1193  ostringstream s1;
1194  s1 << fedNumber;
1195  std::string fedNum = s1.str();
1196 
1197  if (!dir.empty())
1198  dir += "/";
1199 
1200  std::string filename = dir + "params_fed_" + fedNum + ".dat";
1201 
1202  FILE *outfile = fopen((filename.c_str()), "w");
1203  if (outfile == nullptr) {
1204  cout << __LINE__ << "]\t" << mthn << "Could not open file: " << filename << " for writing" << endl;
1205  return;
1206  }
1207 
1208  //Fed Base Address
1209  fprintf(outfile, "FED Base address :0x%lx\n", FEDBASE_0);
1210  fprintf(outfile, "FEDID Number :0x%lx\n", fedNumber);
1211 
1212  // Number of ROCs
1213  int ijx = 0;
1214  for (int i = 0; i < 36; i++) {
1215  ijx = i + 1;
1216  fprintf(outfile, "Number of ROCs Chnl %d:%d\n", ijx, NRocs[i]);
1217  }
1218 
1219  //Settable optical input parameters
1220  fprintf(outfile, "Optical reciever 1 Capacitor Adjust(0-3):%d\n", opt_cap[0]);
1221  fprintf(outfile, "Optical reciever 2 Capacitor Adjust(0-3):%d\n", opt_cap[1]);
1222  fprintf(outfile, "Optical reciever 3 Capacitor Adjust(0-3):%d\n", opt_cap[2]);
1223  fprintf(outfile, "Optical reciever 1 Input Offset (0-15) :%d\n", opt_inadj[0]);
1224  fprintf(outfile, "Optical reciever 2 Input Offset (0-15) :%d\n", opt_inadj[1]);
1225  fprintf(outfile, "Optical reciever 3 Input Offset (0-15) :%d\n", opt_inadj[2]);
1226  fprintf(outfile, "Optical reciever 1 Output Offset (0-3) :%d\n", opt_ouadj[0]);
1227  fprintf(outfile, "Optical reciever 2 Output Offset (0-3) :%d\n", opt_ouadj[1]);
1228  fprintf(outfile, "Optical reciever 3 Output Offset (0-3) :%d\n", opt_ouadj[2]);
1229 
1230  //input offset dac
1231  for (int i = 0; i < 36; i++) {
1232  fprintf(outfile, "Offset DAC channel %d:%d\n", i + 1, offs_dac[i]);
1233  }
1234 
1235  //clock phases
1236  fprintf(outfile, "Clock Phase Bits ch 1-9:0x%x\n", clkphs1_9);
1237  fprintf(outfile, "Clock Phase Bits ch 10-18:0x%x\n", clkphs10_18);
1238  fprintf(outfile, "Clock Phase Bits ch 19-27:0x%x\n", clkphs19_27);
1239  fprintf(outfile, "Clock Phase Bits ch 28-36:0x%x\n", clkphs28_36);
1240 
1241  //Blacks
1242  for (int i = 0; i < 36; i++) {
1243  fprintf(outfile, "Black HiThold ch %d:%d \n", i + 1, BlackHi[i]);
1244  fprintf(outfile, "Black LoThold ch %d:%d \n", i + 1, BlackLo[i]);
1245  fprintf(outfile, "ULblack Thold ch %d:%d \n", i + 1, Ublack[i]);
1246  }
1247 
1248  //Channel delays
1249  for (int i = 0; i < 36; i++) {
1250  fprintf(outfile, "Delay channel %d(0-15):%d\n", i + 1, DelayCh[i]);
1251  }
1252 
1253  //Signal levels
1254  for (int i = 0; i < 36; i++) {
1255  fprintf(outfile, "TBM level 0 Channel %d:%d\n", i + 1, TBM_L0[i]);
1256  fprintf(outfile, "TBM level 1 Channel %d:%d\n", i + 1, TBM_L1[i]);
1257  fprintf(outfile, "TBM level 2 Channel %d:%d\n", i + 1, TBM_L2[i]);
1258  fprintf(outfile, "TBM level 3 Channel %d:%d\n", i + 1, TBM_L3[i]);
1259  fprintf(outfile, "TBM level 4 Channel %d:%d\n", i + 1, TBM_L4[i]);
1260 
1261  for (int j = 0; j < NRocs[i]; j++) {
1262  fprintf(outfile, "ROC%d level 0 Channel %d :%d\n", j, i + 1, ROC_L0[i][j]);
1263  fprintf(outfile, "ROC%d level 1 Channel %d :%d\n", j, i + 1, ROC_L1[i][j]);
1264  fprintf(outfile, "ROC%d level 2 Channel %d :%d\n", j, i + 1, ROC_L2[i][j]);
1265  fprintf(outfile, "ROC%d level 3 Channel %d :%d\n", j, i + 1, ROC_L3[i][j]);
1266  fprintf(outfile, "ROC%d level 4 Channel %d :%d\n", j, i + 1, ROC_L4[i][j]);
1267  }
1268 
1269  fprintf(outfile, "TRLR level 0 Channel %d:%d\n", i + 1, TRL_L0[i]);
1270  fprintf(outfile, "TRLR level 1 Channel %d:%d\n", i + 1, TRL_L1[i]);
1271  fprintf(outfile, "TRLR level 2 Channel %d:%d\n", i + 1, TRL_L2[i]);
1272  fprintf(outfile, "TRLR level 3 Channel %d:%d\n", i + 1, TRL_L3[i]);
1273  fprintf(outfile, "TRLR level 4 Channel %d:%d\n", i + 1, TRL_L4[i]);
1274  }
1275 
1276  //These bits turn off(1) and on(0) channels
1277  fprintf(outfile, "Channel Enbable bits chnls 1-9 (on = 0):0x%x\n", Ncntrl);
1278  fprintf(outfile, "Channel Enbable bits chnls 10-18(on = 0):0x%x\n", NCcntrl);
1279  fprintf(outfile, "Channel Enbable bits chnls 19-27(on = 0):0x%x\n", SCcntrl);
1280  fprintf(outfile, "Channel Enbable bits chnls 28-36(on = 0):0x%x\n", Scntrl);
1281 
1282  //These are delays to the TTCrx
1283  fprintf(outfile, "TTCrx Coarse Delay Register 2:%d\n", CoarseDel);
1284  fprintf(outfile, "TTCrc ClkDes2 Register 3:0x%x\n", ClkDes2);
1285  fprintf(outfile, "TTCrc Fine Dlay ClkDes2 Reg 1:%d\n", FineDes2Del);
1286 
1287  // Control register
1288  fprintf(outfile, "Center Chip Control Reg:0x%x\n", Ccntrl);
1289  fprintf(outfile, "Initial Slink DAQ mode:%d\n", modeRegister);
1290 
1291  //These bits set ADC Gain/Range 1Vpp(0) and 2Vpp(1) for channels
1292  fprintf(outfile, "Channel ADC Gain bits chnls 1-12(1Vpp = 0):0x%x\n", Nadcg);
1293  fprintf(outfile, "Channel ADC Gain bits chnls 13-20(1Vpp = 0):0x%x\n", NCadcg);
1294  fprintf(outfile, "Channel ADC Gain bits chnls 21-28(1Vpp = 0):0x%x\n", SCadcg);
1295  fprintf(outfile, "Channel ADC Gain bits chnls 29-36(1Vpp = 0):0x%x\n", Sadcg);
1296 
1297  //These bits set Baseline adjustment value (common by FPGA)//can turn on by channel
1298  fprintf(outfile, "Channel Baseline Enbable chnls 1-9 (on = (0x1ff<<16)+):0x%x\n", Nbaseln);
1299  fprintf(outfile, "Channel Baseline Enbable chnls 10-18(on = (0x1ff<<16)+):0x%x\n", NCbaseln);
1300  fprintf(outfile, "Channel Baseline Enbable chnls 19-27(on = (0x1ff<<16)+):0x%x\n", SCbaseln);
1301  fprintf(outfile, "Channel Baseline Enbable chnls 28-36(on = (0x1ff<<16)+):0x%x\n", Sbaseln);
1302 
1303  //These bits set TBM trailer mask (common by FPGA)
1304  fprintf(outfile, "TBM trailer mask chnls 1-9 (0xff = all masked):0x%x\n", N_TBMmask);
1305  fprintf(outfile, "TBM trailer mask chnls 10-18(0xff = all masked):0x%x\n", NC_TBMmask);
1306  fprintf(outfile, "TBM trailer mask chnls 19-27(0xff = all masked):0x%x\n", SC_TBMmask);
1307  fprintf(outfile, "TBM trailer mask chnls 28-36(0xff = all masked):0x%x\n", S_TBMmask);
1308 
1309  //These bits set the Private fill/gap word value (common by FPGA)
1310  fprintf(outfile, "Private 8 bit word chnls 1-9 :0x%x\n", N_Pword);
1311  fprintf(outfile, "Private 8 bit word chnls 10-18:0x%x\n", NC_Pword);
1312  fprintf(outfile, "Private 8 bit word chnls 19-27:0x%x\n", SC_Pword);
1313  fprintf(outfile, "Private 8 bit word chnls 28-36:0x%x\n", S_Pword);
1314 
1315  //These bit sets the special dac mode for random triggers
1316  fprintf(outfile, "Special Random testDAC mode (on = 0x1, off=0x0):0x%x\n", SpecialDac);
1317 
1318  //These bits set the number of Out of consecutive out of sync events until a TTs OOs
1319  fprintf(outfile, "Number of Consecutive (max 1023) Out of Syncs till TTs OOS set:%d\n", Ooslvl);
1320 
1321  //These bits set the number of Empty events until a TTs Error
1322  fprintf(outfile, "Number of Consecutive (max 1023) Empty events till TTs ERR set:%d\n", Errlvl);
1323 
1324  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 N
1325  fprintf(outfile, "N Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", Nfifo1Bzlvl);
1326 
1327  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 NC
1328  fprintf(outfile, "NC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", NCfifo1Bzlvl);
1329 
1330  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 SC
1331  fprintf(outfile, "SC Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", SCfifo1Bzlvl);
1332 
1333  //These bits set the Almost Full level in fifo-1, Almost full = TTs BUSY in fifo-1 S
1334  fprintf(outfile, "S Fifo-1 almost full level,sets TTs BUSY (max 1023):%d\n", Sfifo1Bzlvl);
1335 
1336  //These bits set the Almost Full level in fifo-3, Almost full = TTs WARN in fifo-3
1337  fprintf(outfile, "Fifo-3 almost full level,sets TTs WARN (max 8191):%d\n", fifo3Wrnlvl);
1338 
1339  fprintf(outfile, "FED Master delay 0=0,1=32,2=48,3=64:%d\n", FedTTCDelay);
1340 
1341  fprintf(outfile, "TTCrx Register 0 fine delay ClkDes1:%d\n", FineDes1Del);
1342 
1343  int checkword = 20211;
1344 
1345  fprintf(outfile, "Params FED file check word:%d\n", checkword);
1346 
1347  //These bits set the hit limit in fifo-1 for an event
1348  fprintf(outfile, "N fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1349  N_hitlimit); //ch 1-9
1350 
1351  fprintf(outfile, "NC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1352  NC_hitlimit); //ch 10-18
1353 
1354  fprintf(outfile, "SC fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1355  SC_hitlimit); //ch 19-27
1356 
1357  fprintf(outfile, "S fifo-1 hit limit (max 1023 (hard) 900 (soft):%d\n",
1358  S_hitlimit); //ch 28-36
1359 
1360  //These bits allow a ROC to be skipped (1/fpga)
1361  fprintf(outfile, "Skip a ROC in ch 1-9, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", N_testreg);
1362 
1363  fprintf(outfile, "Skip a ROC in ch 10-18, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", NC_testreg);
1364 
1365  fprintf(outfile, "Skip a ROC in ch 19-27, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", SC_testreg);
1366 
1367  fprintf(outfile, "Skip a ROC in ch 28-36, bits 10-5 chnl, bits 0-4 ROC-1:%d\n", S_testreg);
1368 
1369  fprintf(outfile, "Set BUSYWHENBEHIND by this many triggers with timeouts:%d\n", BusyWhenBehind);
1370 
1371  fprintf(outfile, "D[0]=1 enable fed-stuck reset D[1]=1 disable ev# protect(dont):0x%x\n", FeatureRegister);
1372 
1373  fprintf(outfile, "Limit for fifo-2 almost full (point for the TTS flag):0x%x\n", FIFO2Limit);
1374 
1375  fprintf(outfile, "Limit for consecutive timeout OR OOSs:%d\n", TimeoutOROOSLimit);
1376 
1377  fprintf(outfile, "Turn off filling of lastdac fifos(exc 1st ROC):%d\n", LastDacOff);
1378 
1379  fprintf(outfile, "Number of simulated hits per ROC for internal generator:%d\n", SimHitsPerRoc);
1380 
1381  fprintf(outfile, "Miniumum hold time for busy (changing definition):%d\n", BusyHoldMin);
1382 
1383  fprintf(outfile, "Trigger Holdoff in units of 25us(0=none):%d\n", TriggerHoldoff);
1384 
1385  fprintf(outfile, "Spare fedcard input 1:%d\n", SPARE1);
1386  fprintf(outfile, "Spare fedcard input 2:%d\n", SPARE2);
1387  fprintf(outfile, "Spare fedcard input 3:%d\n", SPARE3);
1388  fprintf(outfile, "Spare fedcard input 4:%d\n", SPARE4);
1389  fprintf(outfile, "Spare fedcard input 5:%d\n", SPARE5);
1390  fprintf(outfile, "Spare fedcard input 6:%d\n", SPARE6);
1391  fprintf(outfile, "Spare fedcard input 7:%d\n", SPARE7);
1392  fprintf(outfile, "Spare fedcard input 8:%d\n", SPARE8);
1393  fprintf(outfile, "Spare fedcard input 9:%d\n", SPARE9);
1394  fprintf(outfile, "Spare fedcard input 10:%d\n", SPARE10);
1395 
1396  fclose(outfile);
1397 }
1398 
1399 //=============================================================================================
1400 void PixelFEDCard::writeXMLHeader(pos::PixelConfigKey key,
1401  int version,
1402  std::string path,
1403  std::ofstream *fedstream,
1404  std::ofstream *rocstream,
1405  std::ofstream *tbmstream) const {
1406  std::string mthn = "[PixelFEDCard::writeXMLHeader()]\t\t\t ";
1407  std::stringstream fedfullPath;
1408  std::stringstream rocfullPath;
1409  std::stringstream tbmfullPath;
1410 
1411  // modified by MR on 05-08-2008 16:50:28
1412  // FED MAIN XML FILE
1413  fedfullPath << path << "/FedConfiguration_Template_" << PixelTimeFormatter::getmSecTime() << ".xml";
1414  std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << fedfullPath.str() << "" << std::endl;
1415 
1416  fedstream->open(fedfullPath.str().c_str());
1417 
1418  *fedstream << "<?xml version='1.0' encoding='UTF-8' standalone='yes'?>" << std::endl;
1419  *fedstream << "<ROOT xmlns:xsi='http://www.w3.org/2001/XMLSchema-instance'>" << std::endl;
1420  *fedstream << "" << std::endl;
1421  *fedstream << " <HEADER>" << std::endl;
1422  *fedstream << " <HINTS mode='load-as-group' /> " << std::endl;
1423  *fedstream << " <TYPE>" << std::endl;
1424  *fedstream << " <EXTENSION_TABLE_NAME>FED_CONFIGURATION</EXTENSION_TABLE_NAME>" << std::endl;
1425  *fedstream << " <NAME>Pixel FED Configuration</NAME>" << std::endl;
1426  *fedstream << " </TYPE>" << std::endl;
1427  *fedstream << " <RUN>" << std::endl;
1428  *fedstream << " <RUN_TYPE>Pixel FED Configuration</RUN_TYPE>" << std::endl;
1429  *fedstream << " <RUN_NUMBER>1</RUN_NUMBER>" << std::endl;
1430  *fedstream << " <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl;
1431  *fedstream << " <LOCATION>CERN P5</LOCATION>" << std::endl;
1432  *fedstream << " </RUN>" << std::endl;
1433  *fedstream << " </HEADER>" << std::endl;
1434  *fedstream << "" << std::endl;
1435  *fedstream << " <DATA_SET>" << std::endl;
1436  *fedstream << "" << std::endl;
1437  *fedstream << " <VERSION>" << version << "</VERSION>" << std::endl;
1438  *fedstream << " <COMMENT_DESCRIPTION>" << getComment() << "</COMMENT_DESCRIPTION>" << std::endl;
1439  *fedstream << " <CREATED_BY_USER>" << getAuthor() << "</CREATED_BY_USER>" << std::endl;
1440  *fedstream << "" << std::endl;
1441  *fedstream << " <PART>" << std::endl;
1442  *fedstream << " <NAME_LABEL>CMS-PIXEL-ROOT</NAME_LABEL>" << std::endl;
1443  *fedstream << " <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl;
1444  *fedstream << " </PART>" << std::endl;
1445 
1446  // ROC LEVELS MAIN XML FILE
1447  rocfullPath << path << "/Pixel_RocAnalogLevels_" << PixelTimeFormatter::getmSecTime() << ".xml";
1448  std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << rocfullPath.str() << "" << std::endl;
1449 
1450  rocstream->open(rocfullPath.str().c_str());
1451 
1452  *rocstream << "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"yes\"?>" << std::endl;
1453  *rocstream << "<ROOT xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\">" << std::endl;
1454  *rocstream << "" << std::endl;
1455  *rocstream << " <HEADER>" << std::endl;
1456  *rocstream << " <HINTS mode='only-det-root,load-as-group'/>" << std::endl;
1457  *rocstream << " <TYPE>" << std::endl;
1458  *rocstream << " <EXTENSION_TABLE_NAME>ROC_ANALOG_LEVELS</EXTENSION_TABLE_NAME>" << std::endl;
1459  *rocstream << " <NAME>ROC Analog Levels</NAME>" << std::endl;
1460  *rocstream << " </TYPE>" << std::endl;
1461  *rocstream << " <RUN>" << std::endl;
1462  *rocstream << " <RUN_TYPE>ROC Analog Levels</RUN_TYPE>" << std::endl;
1463  *rocstream << " <RUN_NUMBER>1</RUN_NUMBER> " << std::endl;
1464  *rocstream << " <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl;
1465  *rocstream << " <CREATED_BY_USER>Umesh Joshi</CREATED_BY_USER> " << std::endl;
1466  *rocstream << " <LOCATION>CERN</LOCATION> " << std::endl;
1467  *rocstream << " <COMMENT_DESCRIPTION>ROC Analog Levels Template</COMMENT_DESCRIPTION>" << std::endl;
1468  *rocstream << " </RUN>" << std::endl;
1469  *rocstream << " </HEADER>" << std::endl;
1470  *rocstream << "" << std::endl;
1471  *rocstream << " <DATA_SET>" << std::endl;
1472  *rocstream << " <COMMENT_DESCRIPTION>ROC Analog Levels Template</COMMENT_DESCRIPTION>" << std::endl;
1473  *rocstream << " <VERSION>" << version << "</VERSION>" << std::endl;
1474  *rocstream << " " << std::endl;
1475  *rocstream << " <PART>" << std::endl;
1476  *rocstream << " <SERIAL_NUMBER>CMS-PIXEL-ROOT</SERIAL_NUMBER>" << std::endl;
1477  *rocstream << " <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl;
1478  *rocstream << " </PART>" << std::endl;
1479 
1480  // TBM LEVELS MAIN XML FILE
1481  tbmfullPath << path << "/Pixel_TbmAnalogLevels_" << PixelTimeFormatter::getmSecTime() << ".xml";
1482  std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << tbmfullPath.str() << "" << std::endl;
1483 
1484  tbmstream->open(tbmfullPath.str().c_str());
1485 
1486  *tbmstream << "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"yes\"?>" << std::endl;
1487  *tbmstream << "<ROOT xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\">" << std::endl;
1488  *tbmstream << "" << std::endl;
1489  *tbmstream << " <HEADER>" << std::endl;
1490  *tbmstream << " <HINTS mode='only-det-root,load-as-group' />" << std::endl;
1491  *tbmstream << " <TYPE>" << std::endl;
1492  *tbmstream << " <EXTENSION_TABLE_NAME>TBM_ANALOG_LEVELS</EXTENSION_TABLE_NAME>" << std::endl;
1493  *tbmstream << " <NAME>TBM Analog Levels</NAME>" << std::endl;
1494  *tbmstream << " </TYPE>" << std::endl;
1495  *tbmstream << " <RUN>" << std::endl;
1496  *tbmstream << " <RUN_TYPE>TBM Analog Levels</RUN_TYPE>" << std::endl;
1497  *tbmstream << " <RUN_NUMBER>1</RUN_NUMBER>" << std::endl;
1498  *tbmstream << " <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl;
1499  *tbmstream << " <CREATED_BY_USER>Umesh Joshi</CREATED_BY_USER> " << std::endl;
1500  *tbmstream << " <LOCATION>CERN</LOCATION> " << std::endl;
1501  *tbmstream << " <COMMENT_DESCRIPTION>TBM Analog Levels</COMMENT_DESCRIPTION>" << std::endl;
1502  *tbmstream << " </RUN>" << std::endl;
1503  *tbmstream << " </HEADER>" << std::endl;
1504  *tbmstream << "" << std::endl;
1505  *tbmstream << " <DATA_SET>" << std::endl;
1506  *tbmstream << " <VERSION>" << version << "</VERSION>" << std::endl;
1507  *tbmstream << " " << std::endl;
1508  *tbmstream << " <PART>" << std::endl;
1509  *tbmstream << " <SERIAL_NUMBER>CMS-PIXEL-ROOT</SERIAL_NUMBER>" << std::endl;
1510  *tbmstream << " <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl;
1511  *tbmstream << " </PART>" << std::endl;
1512 }
1513 
1514 //=============================================================================================
1515 void PixelFEDCard::writeXMLHeader(pos::PixelConfigKey key, int version, std::string path, std::ofstream *out) const {
1516  std::string mthn = "[PixelFEDCard::writeXMLHeader()]\t\t\t ";
1517  std::stringstream fullPath;
1518 
1519  fullPath << path << "/fedcard_" << PixelTimeFormatter::getmSecTime() << ".xml";
1520  std::cout << __LINE__ << "]\t" << mthn << "Writing to: " << fullPath.str() << "" << std::endl;
1521 
1522  out->open(fullPath.str().c_str());
1523 
1524  *out << "<?xml version='1.0' encoding='UTF-8' standalone='yes'?>" << std::endl;
1525  *out << "<ROOT>" << std::endl;
1526  *out << "" << std::endl;
1527  *out << " <HEADER>" << std::endl;
1528  *out << " <TYPE>" << std::endl;
1529  *out << " <EXTENSION_TABLE_NAME>FED_CONFIGURATION</EXTENSION_TABLE_NAME>" << std::endl;
1530  *out << " <NAME>Pixel FED Configuration</NAME>" << std::endl;
1531  *out << " </TYPE>" << std::endl;
1532  *out << " <RUN>" << std::endl;
1533  *out << " <RUN_TYPE>Pixel FED Configuration</RUN_TYPE>" << std::endl;
1534  *out << " <RUN_NUMBER>1</RUN_NUMBER>" << std::endl;
1535  *out << " <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl;
1536  *out << " <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl;
1537  *out << " <LOCATION>CERN TAC</LOCATION>" << std::endl;
1538  *out << " <CREATED_BY_USER>Dario Menasce</CREATED_BY_USER>" << std::endl;
1539  *out << " </RUN>" << std::endl;
1540  *out << " </HEADER>" << std::endl;
1541  *out << "" << std::endl;
1542  *out << " <DATA_SET>" << std::endl;
1543  *out << "" << std::endl;
1544  *out << " <VERSION>" << version << "</VERSION>" << std::endl;
1545  *out << " <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl;
1546  *out << "" << std::endl;
1547  *out << " <PART>" << std::endl;
1548  *out << " <NAME_LABEL>CMS-PIXEL-ROOT</NAME_LABEL>" << std::endl;
1549  *out << " <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl;
1550  *out << " </PART>" << std::endl;
1551 }
1552 //=============================================================================================
1553 void PixelFEDCard::writeXML(std::ofstream *out) const {
1554  std::string mthn = "[PixelFEDCard::writeXML()]\t\t\t ";
1555 
1556  *out << " <DATA>" << std::endl;
1557  *out << " " << std::endl;
1558  *out << " <PXLFED_NAME>PxlFED_" << fedNumber << "</PXLFED_NAME>" << std::endl;
1559  *out << " <VME_ADDRESS>268435456</VME_ADDRESS>" << std::endl;
1560  // *out << " <CRATE_NUMBER>1</CRATE_NUMBER>" << std::endl ;
1561  // *out << " <SLOT_NUMBER>5</SLOT_NUMBER> " << std::endl ;
1562  // *out << " <VME_ADDRESS>268435456</VME_ADDRESS>" << std::endl ;
1563  // *out << " <CRATE_LABEL>S1G03e</CRATE_LABEL>" << std::endl ;
1564  *out << "" << std::endl;
1565  *out << " <CHANNEL_ID>1</CHANNEL_ID>" << std::endl;
1566  *out << " <NUMBER_OF_ROCS>21</NUMBER_OF_ROCS>" << std::endl;
1567  *out << " <CHANNEL_OFFSET_DAC_SETTINGS>0</CHANNEL_OFFSET_DAC_SETTINGS>" << std::endl;
1568  *out << " <CHANNEL_DELAY_SETTINGS>3</CHANNEL_DELAY_SETTINGS>" << std::endl;
1569  *out << " <CHANNEL_BLACK_HIGH>400</CHANNEL_BLACK_HIGH>" << std::endl;
1570  *out << " <CHANNEL_BLACK_LOW>150</CHANNEL_BLACK_LOW>" << std::endl;
1571  *out << " <CHANNEL_ULTRA_BLACK>120</CHANNEL_ULTRA_BLACK>" << std::endl;
1572  *out << "" << std::endl;
1573  *out << " <OPT1_CAP>0</OPT1_CAP>" << std::endl;
1574  *out << " <OPT2_CAP>0</OPT2_CAP>" << std::endl;
1575  *out << " <OPT3_CAP>0</OPT3_CAP>" << std::endl;
1576  *out << " <OPT1_INP>0</OPT1_INP>" << std::endl;
1577  *out << " <OPT2_INP>0</OPT2_INP>" << std::endl;
1578  *out << " <OPT3_INP>0</OPT3_INP>" << std::endl;
1579  *out << " <OPT1_OUT>0</OPT1_OUT>" << std::endl;
1580  *out << " <OPT2_OUT>0</OPT2_OUT>" << std::endl;
1581  *out << " <OPT3_OUT>0</OPT3_OUT>" << std::endl;
1582  *out << " <NORTH_CLKPHB>511</NORTH_CLKPHB>" << std::endl;
1583  *out << " <NORTHCENTER_CLKPHB>511</NORTHCENTER_CLKPHB>" << std::endl;
1584  *out << " <SOUTHCENTER_CLKPHB>511</SOUTHCENTER_CLKPHB>" << std::endl;
1585  *out << " <SOUTH_CLKPHB>511</SOUTH_CLKPHB>" << std::endl;
1586  *out << " <NORTH_CTRL>0</NORTH_CTRL> " << std::endl;
1587  *out << " <NORTHCENTER_CTRL>0</NORTHCENTER_CTRL>" << std::endl;
1588  *out << " <SOUTHCENTER_CTRL>0</SOUTHCENTER_CTRL>" << std::endl;
1589  *out << " <SOUTH_CTRL>0</SOUTH_CTRL>" << std::endl;
1590  *out << " <REG1_TTCRX_FDLA>5</REG1_TTCRX_FDLA>" << std::endl;
1591  *out << " <REG2_TTCRX_CDLA>0</REG2_TTCRX_CDLA>" << std::endl;
1592  *out << " <REG3_TTCRX_CLKD2>155</REG3_TTCRX_CLKD2>" << std::endl;
1593  *out << " <CENTER_CTRL>0</CENTER_CTRL>" << std::endl;
1594  *out << " <CENTER_MODE>0</CENTER_MODE>" << std::endl;
1595  *out << " <B1_ADCGN>0</B1_ADCGN>" << std::endl;
1596  *out << " <B2_ADCGN>0</B2_ADCGN>" << std::endl;
1597  *out << " <B3_ADCGN>0</B3_ADCGN>" << std::endl;
1598  *out << " <B4_ADCGN>0</B4_ADCGN>" << std::endl;
1599  *out << " <NORTH_BADJ>330</NORTH_BADJ>" << std::endl;
1600  *out << " <NORTHCENTER_BADJ>330</NORTHCENTER_BADJ>" << std::endl;
1601  *out << " <SOUTHCENTER_BADJ>330</SOUTHCENTER_BADJ>" << std::endl;
1602  *out << " <SOUTH_BADJ>330</SOUTH_BADJ>" << std::endl;
1603  *out << " <NORTH_TBMMASK>2</NORTH_TBMMASK>" << std::endl;
1604  *out << " <NORTHCENTER_TBMMASK>2</NORTHCENTER_TBMMASK>" << std::endl;
1605  *out << " <SOUTHCENTER_TBMMASK>2</SOUTHCENTER_TBMMASK>" << std::endl;
1606  *out << " <SOUTH_TBMMASK>2</SOUTH_TBMMASK>" << std::endl;
1607  *out << " <NORTH_PWORD>177</NORTH_PWORD>" << std::endl;
1608  *out << " <NORTHCENTER_PWORD>178</NORTHCENTER_PWORD>" << std::endl;
1609  *out << " <SOUTHCENTER_PWORD>179</SOUTHCENTER_PWORD>" << std::endl;
1610  *out << " <SOUTH_PWORD>180</SOUTH_PWORD>" << std::endl;
1611  *out << " <SPECDAC>0</SPECDAC>" << std::endl;
1612  *out << " <OOS_LVL>0</OOS_LVL>" << std::endl;
1613  *out << " <ERR_LVL>0</ERR_LVL>" << std::endl;
1614  *out << " <NORTH_FIFO1_BZ_LVL>900</NORTH_FIFO1_BZ_LVL>" << std::endl;
1615  *out << " <NORTHCENTER_FIFO1_BZ_LVL>900</NORTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1616  *out << " <SOUTHCENTER_FIFO1_BZ_LVL>900</SOUTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1617  *out << " <SOUTH_FIFO1_BZ_LVL>900</SOUTH_FIFO1_BZ_LVL>" << std::endl;
1618  *out << " <FIFO3_WRN_LVL>7680</FIFO3_WRN_LVL> " << std::endl;
1619  *out << " <FED_MASTER_DELAY>0</FED_MASTER_DELAY>" << std::endl;
1620  *out << " <NO_HITLIMIT>0</NO_HITLIMIT>" << std::endl;
1621  *out << " <NC_HITLIMIT>0</NC_HITLIMIT>" << std::endl;
1622  *out << " <SC_HITLIMIT>0</SC_HITLIMIT>" << std::endl;
1623  *out << " <SO_HITLIMIT>0</SO_HITLIMIT>" << std::endl;
1624  *out << " <NO_TESTREG>0</NO_TESTREG>" << std::endl;
1625  *out << " <NC_TESTREG>0</NC_TESTREG>" << std::endl;
1626  *out << " <SC_TESTREG>0</SC_TESTREG>" << std::endl;
1627  *out << " <SO_TESTREG>0</SO_TESTREG>" << std::endl;
1628  *out << " <BUSYWHENBEHIND>4</BUSYWHENBEHIND>" << std::endl;
1629  *out << " <FEATUREREGISTER>0X1234</FEATUREREGISTER>" << std::endl;
1630  *out << " <FIFO2LIMIT>0X1C00</FIFO2LIMIT>" << std::endl;
1631  *out << " <TIMEOUTOROOSLIMIT>0</TIMEOUTOROOSLIMIT>" << std::endl;
1632  *out << " <LASTDACOFF>0</LASTDACOFF>" << std::endl;
1633  *out << " <SIMHITSPERROC>0</SIMHITSPERROC>" << std::endl;
1634  *out << " <BUSYHOLDMIN>0</BUSYHOLDMIN>" << std::endl;
1635  *out << " <SPARE1>0</SPARE1>" << std::endl;
1636  *out << " <SPARE2>0</SPARE2>" << std::endl;
1637  *out << " <SPARE3>0</SPARE3>" << std::endl;
1638  *out << " <SPARE4>0</SPARE4>" << std::endl;
1639  *out << " <SPARE5>0</SPARE5>" << std::endl;
1640  *out << " <SPARE6>0</SPARE6>" << std::endl;
1641  *out << " <SPARE7>0</SPARE7>" << std::endl;
1642  *out << " <SPARE8>0</SPARE8>" << std::endl;
1643  *out << " <SPARE9>0</SPARE9>" << std::endl;
1644  *out << " <SPARE10>0</SPARE10>" << std::endl;
1645  *out << " " << std::endl;
1646  *out << " </DATA>" << std::endl;
1647  *out << " " << std::endl;
1648 }
1649 
1650 //=============================================================================================
1651 void PixelFEDCard::writeXML(std::ofstream *fedstream, std::ofstream *rocstream, std::ofstream *tbmstream) const {
1652  std::string mthn = "[PixelFEDCard::writeXML()]\t\t\t ";
1653 
1654  for (int i = 0; i < 36; i++) {
1655  *fedstream << " <DATA>" << std::endl;
1656  *fedstream << " " << std::endl;
1657  *fedstream << " <PIXEL_FED>" << fedNumber << "</PIXEL_FED>" << std::endl;
1658  *fedstream << " <VME_ADDRS_HEX>0x" << hex << FEDBASE_0 << dec << "</VME_ADDRS_HEX>" << std::endl;
1659  *fedstream << "" << std::endl;
1660  *fedstream << " <CHANNEL_ID>" << i + 1 << "</CHANNEL_ID>" << std::endl;
1661  *fedstream << " <NUM_ROCS>" << NRocs[i] << "</NUM_ROCS>" << std::endl;
1662  *fedstream << " <CHAN_OFFST_DAC>" << offs_dac[i] << "</CHAN_OFFST_DAC>" << std::endl;
1663  *fedstream << " <CHAN_DELAY>" << DelayCh[i] << "</CHAN_DELAY>" << std::endl;
1664  *fedstream << " <CHAN_BHIGH>" << BlackHi[i] << "</CHAN_BHIGH>" << std::endl;
1665  *fedstream << " <CHAN_BLOW>" << BlackLo[i] << "</CHAN_BLOW>" << std::endl;
1666  *fedstream << " <CHAN_UB>" << Ublack[i] << "</CHAN_UB>" << std::endl;
1667  *fedstream << "" << std::endl;
1668  *fedstream << " <OPT1_CAP>" << opt_cap[0] << "</OPT1_CAP>" << std::endl;
1669  *fedstream << " <OPT2_CAP>" << opt_cap[1] << "</OPT2_CAP>" << std::endl;
1670  *fedstream << " <OPT3_CAP>" << opt_cap[2] << "</OPT3_CAP>" << std::endl;
1671  *fedstream << " <OPT1_INP>" << opt_inadj[0] << "</OPT1_INP>" << std::endl;
1672  *fedstream << " <OPT2_INP>" << opt_inadj[1] << "</OPT2_INP>" << std::endl;
1673  *fedstream << " <OPT3_INP>" << opt_inadj[2] << "</OPT3_INP>" << std::endl;
1674  *fedstream << " <OPT1_OUT>" << opt_ouadj[0] << "</OPT1_OUT>" << std::endl;
1675  *fedstream << " <OPT2_OUT>" << opt_ouadj[1] << "</OPT2_OUT>" << std::endl;
1676  *fedstream << " <OPT3_OUT>" << opt_ouadj[2] << "</OPT3_OUT>" << std::endl;
1677  *fedstream << " <NORTH_CLKPHB>" << clkphs1_9 << "</NORTH_CLKPHB>" << std::endl;
1678  *fedstream << " <NORTHCENTER_CLKPHB>" << clkphs10_18 << "</NORTHCENTER_CLKPHB>" << std::endl;
1679  *fedstream << " <SOUTHCENTER_CLKPHB>" << clkphs19_27 << "</SOUTHCENTER_CLKPHB>" << std::endl;
1680  *fedstream << " <SOUTH_CLKPHB>" << clkphs28_36 << "</SOUTH_CLKPHB>" << std::endl;
1681  *fedstream << " <NORTH_CTRL>" << Ncntrl << "</NORTH_CTRL> " << std::endl;
1682  *fedstream << " <NORTHCENTER_CTRL>" << NCcntrl << "</NORTHCENTER_CTRL>" << std::endl;
1683  *fedstream << " <SOUTHCENTER_CTRL>" << SCcntrl << "</SOUTHCENTER_CTRL>" << std::endl;
1684  *fedstream << " <SOUTH_CTRL>" << Scntrl << "</SOUTH_CTRL>" << std::endl;
1685  *fedstream << " <REG0_TTCRX_FDLA>" << FineDes1Del << "</REG0_TTCRX_FDLA>" << std::endl;
1686  *fedstream << " <REG1_TTCRX_FDLA>" << FineDes2Del << "</REG1_TTCRX_FDLA>" << std::endl;
1687  *fedstream << " <REG2_TTCRX_CDLA>" << CoarseDel << "</REG2_TTCRX_CDLA>" << std::endl;
1688  *fedstream << " <REG3_TTCRX_CLKD2>" << ClkDes2 << "</REG3_TTCRX_CLKD2>" << std::endl;
1689  *fedstream << " <CENTER_CTRL>" << Ccntrl << "</CENTER_CTRL>" << std::endl;
1690  *fedstream << " <CENTER_MODE>" << modeRegister << "</CENTER_MODE>" << std::endl;
1691  *fedstream << " <B1_ADCGN>" << Nadcg << "</B1_ADCGN>" << std::endl;
1692  *fedstream << " <B2_ADCGN>" << NCadcg << "</B2_ADCGN>" << std::endl;
1693  *fedstream << " <B3_ADCGN>" << SCadcg << "</B3_ADCGN>" << std::endl;
1694  *fedstream << " <B4_ADCGN>" << Sadcg << "</B4_ADCGN>" << std::endl;
1695  // std::cout << "PixelFEDCard::WriteXML()\tNbaseln:" << Nbaseln << std::endl ;
1696  // std::cout << "PixelFEDCard::WriteXML()\tNbaseln:" << std::hex << Nbaseln << std::dec << std::endl ;
1697  *fedstream << " <NORTH_BADJ>" << Nbaseln << "</NORTH_BADJ>" << std::endl;
1698  *fedstream << " <NORTHCENTER_BADJ>" << NCbaseln << "</NORTHCENTER_BADJ>" << std::endl;
1699  *fedstream << " <SOUTHCENTER_BADJ>" << SCbaseln << "</SOUTHCENTER_BADJ>" << std::endl;
1700  *fedstream << " <SOUTH_BADJ>" << Sbaseln << "</SOUTH_BADJ>" << std::endl;
1701  *fedstream << " <NORTH_TBMMASK>" << N_TBMmask << "</NORTH_TBMMASK>" << std::endl;
1702  *fedstream << " <NORTHCENTER_TBMMASK>" << NC_TBMmask << "</NORTHCENTER_TBMMASK>" << std::endl;
1703  *fedstream << " <SOUTHCENTER_TBMMASK>" << SC_TBMmask << "</SOUTHCENTER_TBMMASK>" << std::endl;
1704  *fedstream << " <SOUTH_TBMMASK>" << S_TBMmask << "</SOUTH_TBMMASK>" << std::endl;
1705  *fedstream << " <NORTH_PWORD>" << N_Pword << "</NORTH_PWORD>" << std::endl;
1706  *fedstream << " <NORTHCENTER_PWORD>" << NC_Pword << "</NORTHCENTER_PWORD>" << std::endl;
1707  *fedstream << " <SOUTHCENTER_PWORD>" << SC_Pword << "</SOUTHCENTER_PWORD>" << std::endl;
1708  *fedstream << " <SOUTH_PWORD>" << S_Pword << "</SOUTH_PWORD>" << std::endl;
1709  *fedstream << " <SPECDAC>" << SpecialDac << "</SPECDAC>" << std::endl;
1710  *fedstream << " <OOS_LVL>" << Ooslvl << "</OOS_LVL>" << std::endl;
1711  *fedstream << " <ERR_LVL>" << Errlvl << "</ERR_LVL>" << std::endl;
1712  *fedstream << " <NORTH_FIFO1_BZ_LVL>" << Nfifo1Bzlvl << "</NORTH_FIFO1_BZ_LVL>" << std::endl;
1713  *fedstream << " <NORTHCENTER_FIFO1_BZ_LVL>" << NCfifo1Bzlvl << "</NORTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1714  *fedstream << " <SOUTHCENTER_FIFO1_BZ_LVL>" << SCfifo1Bzlvl << "</SOUTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1715  *fedstream << " <SOUTH_FIFO1_BZ_LVL>" << Sfifo1Bzlvl << "</SOUTH_FIFO1_BZ_LVL>" << std::endl;
1716  *fedstream << " <FIFO3_WRN_LVL>" << fifo3Wrnlvl << "</FIFO3_WRN_LVL>" << std::endl;
1717  *fedstream << " <FED_MASTER_DELAY>" << FedTTCDelay << "</FED_MASTER_DELAY>" << std::endl;
1718  *fedstream << " <NO_HITLIMIT>" << N_hitlimit << "</NO_HITLIMIT>" << std::endl;
1719  *fedstream << " <NC_HITLIMIT>" << NC_hitlimit << "</NC_HITLIMIT>" << std::endl;
1720  *fedstream << " <SC_HITLIMIT>" << SC_hitlimit << "</SC_HITLIMIT>" << std::endl;
1721  *fedstream << " <SO_HITLIMIT>" << S_hitlimit << "</SO_HITLIMIT>" << std::endl;
1722  *fedstream << " <NO_TESTREG>" << N_testreg << "</NO_TESTREG>" << std::endl;
1723  *fedstream << " <NC_TESTREG>" << NC_testreg << "</NC_TESTREG>" << std::endl;
1724  *fedstream << " <SC_TESTREG>" << SC_testreg << "</SC_TESTREG>" << std::endl;
1725  *fedstream << " <SO_TESTREG>" << S_testreg << "</SO_TESTREG>" << std::endl;
1726  *fedstream << " <BUSYWHENBEHIND>" << BusyWhenBehind << "</BUSYWHENBEHIND>" << std::endl;
1727  *fedstream << " <BUSYHOLDMIN>" << BusyHoldMin << "</BUSYHOLDMIN>" << std::endl;
1728  *fedstream << " <FEATUREREGISTER>" << FeatureRegister << "</FEATUREREGISTER>" << std::endl;
1729  *fedstream << " <FIFO2LIMIT>" << FIFO2Limit << "</FIFO2LIMIT>" << std::endl;
1730  *fedstream << " <LASTDACOFF>" << LastDacOff << "</LASTDACOFF>" << std::endl;
1731  *fedstream << " <SIMHITSPERROC>" << SimHitsPerRoc << "</SIMHITSPERROC>" << std::endl;
1732  *fedstream << " <TIMEOUTOROOSLIMIT>" << TimeoutOROOSLimit << "</TIMEOUTOROOSLIMIT>" << std::endl;
1733  *fedstream << " <TRIGGERHOLDOFF>" << TriggerHoldoff << "</TRIGGERHOLDOFF>" << std::endl;
1734  *fedstream << " <SPARE1>" << SPARE1 << "</SPARE1>" << std::endl;
1735  *fedstream << " <SPARE2>" << SPARE2 << "</SPARE2>" << std::endl;
1736  *fedstream << " <SPARE3>" << SPARE3 << "</SPARE3>" << std::endl;
1737  *fedstream << " <SPARE4>" << SPARE4 << "</SPARE4>" << std::endl;
1738  *fedstream << " <SPARE5>" << SPARE5 << "</SPARE5>" << std::endl;
1739  *fedstream << " <SPARE6>" << SPARE6 << "</SPARE6>" << std::endl;
1740  *fedstream << " <SPARE7>" << SPARE7 << "</SPARE7>" << std::endl;
1741  *fedstream << " <SPARE8>" << SPARE8 << "</SPARE8>" << std::endl;
1742  *fedstream << " <SPARE9>" << SPARE9 << "</SPARE9>" << std::endl;
1743  *fedstream << " <SPARE10>" << SPARE10 << "</SPARE10>" << std::endl;
1744  *fedstream << " " << std::endl;
1745  *fedstream << " </DATA>" << std::endl;
1746  *fedstream << " " << std::endl;
1747  }
1748 
1749  //ROC & TBM LEVELS
1750  for (int i = 0; i < 36; i++) {
1751  for (int j = 0; j < NRocs[i]; j++) {
1752  *rocstream << "" << std::endl;
1753  *rocstream << " <DATA>" << std::endl;
1754  *rocstream << " <PIXEL_FED>" << fedNumber << "</PIXEL_FED>" << std::endl;
1755  *rocstream << " <FED_CHAN>" << i + 1 << "</FED_CHAN>" << std::endl;
1756  *rocstream << " <FED_ROC_NUM>" << j << "</FED_ROC_NUM>" << std::endl;
1757  *rocstream << " <ROC_L0>" << ROC_L0[i][j] << "</ROC_L0>" << std::endl;
1758  *rocstream << " <ROC_L1>" << ROC_L1[i][j] << "</ROC_L1>" << std::endl;
1759  *rocstream << " <ROC_L2>" << ROC_L2[i][j] << "</ROC_L2>" << std::endl;
1760  *rocstream << " <ROC_L3>" << ROC_L3[i][j] << "</ROC_L3>" << std::endl;
1761  *rocstream << " <ROC_L4>" << ROC_L4[i][j] << "</ROC_L4>" << std::endl;
1762  *rocstream << " </DATA>" << std::endl << std::endl;
1763  *rocstream << " " << std::endl;
1764  }
1765 
1766  *tbmstream << "" << std::endl;
1767  *tbmstream << " <DATA>" << std::endl;
1768  *tbmstream << " <PIXEL_FED>" << fedNumber << "</PIXEL_FED>" << std::endl;
1769  *tbmstream << " <FED_CHAN>" << i + 1 << "</FED_CHAN>" << std::endl;
1770  *tbmstream << " <TBMA_HEAD_L0>" << TBM_L0[i] << "</TBMA_HEAD_L0>" << std::endl;
1771  *tbmstream << " <TBMA_HEAD_L1>" << TBM_L1[i] << "</TBMA_HEAD_L1>" << std::endl;
1772  *tbmstream << " <TBMA_HEAD_L2>" << TBM_L2[i] << "</TBMA_HEAD_L2>" << std::endl;
1773  *tbmstream << " <TBMA_HEAD_L3>" << TBM_L3[i] << "</TBMA_HEAD_L3>" << std::endl;
1774  *tbmstream << " <TBMA_HEAD_L4>" << TBM_L4[i] << "</TBMA_HEAD_L4>" << std::endl;
1775  *tbmstream << " <TBMA_TRAIL_L0>" << TRL_L0[i] << "</TBMA_TRAIL_L0>" << std::endl;
1776  *tbmstream << " <TBMA_TRAIL_L1>" << TRL_L1[i] << "</TBMA_TRAIL_L1>" << std::endl;
1777  *tbmstream << " <TBMA_TRAIL_L2>" << TRL_L2[i] << "</TBMA_TRAIL_L2>" << std::endl;
1778  *tbmstream << " <TBMA_TRAIL_L3>" << TRL_L3[i] << "</TBMA_TRAIL_L3>" << std::endl;
1779  *tbmstream << " <TBMA_TRAIL_L4>" << TRL_L4[i] << "</TBMA_TRAIL_L4>" << std::endl;
1780  *tbmstream << " </DATA>" << std::endl << std::endl;
1781  *tbmstream << "" << std::endl;
1782  }
1783 }
1784 
1785 //=============================================================================================
1786 void PixelFEDCard::writeXMLTrailer(std::ofstream *fedstream, std::ofstream *rocstream, std::ofstream *tbmstream) const {
1787  std::string mthn = "[PixelFEDCard::writeXMLTrailer()]\t\t\t ";
1788 
1789  // Main FED
1790  *fedstream << " </DATA_SET>" << std::endl;
1791  *fedstream << "</ROOT>" << std::endl;
1792 
1793  fedstream->close();
1794  std::cout << __LINE__ << "]\t" << mthn << "Data written for main fed" << std::endl;
1795 
1796  // ROC LVLS
1797  *rocstream << " </DATA_SET>" << std::endl;
1798  *rocstream << "</ROOT>" << std::endl;
1799 
1800  rocstream->close();
1801  std::cout << __LINE__ << "]\t" << mthn << "Data written for roc analog levels" << std::endl;
1802 
1803  // TBM LVLS
1804  *tbmstream << " </DATA_SET>" << std::endl;
1805  *tbmstream << "</ROOT>" << std::endl;
1806 
1807  tbmstream->close();
1808  std::cout << __LINE__ << "]\t" << mthn << "Data written for tbm analog levels" << std::endl;
1809 }
1810 
1811 //=============================================================================================
1812 void PixelFEDCard::writeXMLTrailer(std::ofstream *out) const {
1813  std::string mthn = "[PixelFEDCard::writeXMLTrailer()]\t\t\t ";
1814 
1815  *out << " </DATA_SET>" << std::endl;
1816  *out << "</ROOT>" << std::endl;
1817 
1818  out->close();
1819  std::cout << __LINE__ << "]\t" << mthn << "Data written" << std::endl;
1820 }
1821 
1822 //=============================================================================================
1823 void PixelFEDCard::writeXML(pos::PixelConfigKey key, int version, std::string path) const {
1824  std::string mthn = "[PixelFEDCard::writeXML()]\t\t\t ";
1825  std::stringstream fullPath;
1826 
1827  fullPath << path << "/fedcard.xml";
1828  std::cout << __LINE__ << "]\t" << mthn << "Writing to: |" << fullPath.str() << "|" << std::endl;
1829 
1830  std::ofstream out(fullPath.str().c_str());
1831 
1832  out << "<ROOT>" << std::endl;
1833  out << "" << std::endl;
1834  out << " <HEADER>" << std::endl;
1835  out << " <TYPE>" << std::endl;
1836  out << " <EXTENSION_TABLE_NAME>FED_CONFIGURATION</EXTENSION_TABLE_NAME>" << std::endl;
1837  out << " <NAME>Pixel FED Configuration</NAME>" << std::endl;
1838  out << " </TYPE>" << std::endl;
1839  out << " <RUN>" << std::endl;
1840  out << " <RUN_TYPE>Pixel FED Configuration</RUN_TYPE>" << std::endl;
1841  out << " <RUN_NUMBER>1</RUN_NUMBER>" << std::endl;
1842  out << " <RUN_BEGIN_TIMESTAMP>" << PixelTimeFormatter::getTime() << "</RUN_BEGIN_TIMESTAMP>" << std::endl;
1843  out << " <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl;
1844  out << " <LOCATION>CERN TAC</LOCATION>" << std::endl;
1845  out << " <CREATED_BY_USER>Dario Menasce</CREATED_BY_USER>" << std::endl;
1846  out << " </RUN>" << std::endl;
1847  out << " </HEADER>" << std::endl;
1848  out << "" << std::endl;
1849  out << " <DATA_SET>" << std::endl;
1850  out << "" << std::endl;
1851  out << " <VERSION>T_E_S_T</VERSION>" << std::endl;
1852  out << " <COMMENT_DESCRIPTION>Pixel FED Configuration</COMMENT_DESCRIPTION>" << std::endl;
1853  out << "" << std::endl;
1854  out << " <PART>" << std::endl;
1855  out << " <NAME_LABEL>CMS-PIXEL-ROOT</NAME_LABEL>" << std::endl;
1856  out << " <KIND_OF_PART>Detector ROOT</KIND_OF_PART>" << std::endl;
1857  out << " </PART>" << std::endl;
1858  out << "" << std::endl;
1859  out << " <DATA>" << std::endl;
1860  out << " <PXLFED_NAME>PxlFED_32</PXLFED_NAME>" << std::endl;
1861  out << " <CRATE_NUMBER>1</CRATE_NUMBER>" << std::endl;
1862  out << " <SLOT_NUMBER>5</SLOT_NUMBER> " << std::endl;
1863  out << " <VME_ADDRESS>268435456</VME_ADDRESS>" << std::endl;
1864  out << " <CRATE_LABEL>S1G03e</CRATE_LABEL>" << std::endl;
1865  out << "" << std::endl;
1866  out << " <CHANNEL_ID>1</CHANNEL_ID>" << std::endl;
1867  out << " <NUMBER_OF_ROCS>21</NUMBER_OF_ROCS>" << std::endl;
1868  out << " <CHANNEL_OFFSET_DAC_SETTINGS>0</CHANNEL_OFFSET_DAC_SETTINGS>" << std::endl;
1869  out << " <CHANNEL_DELAY_SETTINGS>3</CHANNEL_DELAY_SETTINGS>" << std::endl;
1870  out << " <CHANNEL_BLACK_HIGH>400</CHANNEL_BLACK_HIGH>" << std::endl;
1871  out << " <CHANNEL_BLACK_LOW>150</CHANNEL_BLACK_LOW>" << std::endl;
1872  out << " <CHANNEL_ULTRA_BLACK>120</CHANNEL_ULTRA_BLACK>" << std::endl;
1873  out << "" << std::endl;
1874  out << " <OPT1_CAP>0</OPT1_CAP>" << std::endl;
1875  out << " <OPT2_CAP>0</OPT2_CAP>" << std::endl;
1876  out << " <OPT3_CAP>0</OPT3_CAP>" << std::endl;
1877  out << " <OPT1_INP>0</OPT1_INP>" << std::endl;
1878  out << " <OPT2_INP>0</OPT2_INP>" << std::endl;
1879  out << " <OPT3_INP>0</OPT3_INP>" << std::endl;
1880  out << " <OPT1_OUT>0</OPT1_OUT>" << std::endl;
1881  out << " <OPT2_OUT>0</OPT2_OUT>" << std::endl;
1882  out << " <OPT3_OUT>0</OPT3_OUT>" << std::endl;
1883  out << " <NORTH_CLKPHB>511</NORTH_CLKPHB>" << std::endl;
1884  out << " <NORTHCENTER_CLKPHB>511</NORTHCENTER_CLKPHB>" << std::endl;
1885  out << " <SOUTHCENTER_CLKPHB>511</SOUTHCENTER_CLKPHB>" << std::endl;
1886  out << " <SOUTH_CLKPHB>511</SOUTH_CLKPHB>" << std::endl;
1887  out << " <NORTH_CTRL>0</NORTH_CTRL> " << std::endl;
1888  out << " <NORTHCENTER_CTRL>0</NORTHCENTER_CTRL>" << std::endl;
1889  out << " <SOUTHCENTER_CTRL>0</SOUTHCENTER_CTRL>" << std::endl;
1890  out << " <SOUTH_CTRL>0</SOUTH_CTRL>" << std::endl;
1891  out << " <REG1_TTCRX_FDLA>5</REG1_TTCRX_FDLA>" << std::endl;
1892  out << " <REG2_TTCRX_CDLA>0</REG2_TTCRX_CDLA>" << std::endl;
1893  out << " <REG3_TTCRX_CLKD2>155</REG3_TTCRX_CLKD2>" << std::endl;
1894  out << " <CENTER_CTRL>0</CENTER_CTRL>" << std::endl;
1895  out << " <CENTER_MODE>0</CENTER_MODE>" << std::endl;
1896  out << " <B1_ADCGN>0</B1_ADCGN>" << std::endl;
1897  out << " <B2_ADCGN>0</B2_ADCGN>" << std::endl;
1898  out << " <B3_ADCGN>0</B3_ADCGN>" << std::endl;
1899  out << " <B4_ADCGN>0</B4_ADCGN>" << std::endl;
1900  out << " <NORTH_BADJ>330</NORTH_BADJ>" << std::endl;
1901  out << " <NORTHCENTER_BADJ>330</NORTHCENTER_BADJ>" << std::endl;
1902  out << " <SOUTHCENTER_BADJ>330</SOUTHCENTER_BADJ>" << std::endl;
1903  out << " <SOUTH_BADJ>330</SOUTH_BADJ>" << std::endl;
1904  out << " <NORTH_TBMMASK>2</NORTH_TBMMASK>" << std::endl;
1905  out << " <NORTHCENTER_TBMMASK>2</NORTHCENTER_TBMMASK>" << std::endl;
1906  out << " <SOUTHCENTER_TBMMASK>2</SOUTHCENTER_TBMMASK>" << std::endl;
1907  out << " <SOUTH_TBMMASK>2</SOUTH_TBMMASK>" << std::endl;
1908  out << " <NORTH_PWORD>177</NORTH_PWORD>" << std::endl;
1909  out << " <NORTHCENTER_PWORD>178</NORTHCENTER_PWORD>" << std::endl;
1910  out << " <SOUTHCENTER_PWORD>179</SOUTHCENTER_PWORD>" << std::endl;
1911  out << " <SOUTH_PWORD>180</SOUTH_PWORD>" << std::endl;
1912  out << " <SPECDAC>0</SPECDAC>" << std::endl;
1913  out << " <OOS_LVL>0</OOS_LVL>" << std::endl;
1914  out << " <ERR_LVL>0</ERR_LVL>" << std::endl;
1915  out << " <NORTH_FIFO1_BZ_LVL>900</NORTH_FIFO1_BZ_LVL>" << std::endl;
1916  out << " <NORTHCENTER_FIFO1_BZ_LVL>900</NORTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1917  out << " <SOUTHCENTER_FIFO1_BZ_LVL>900</SOUTHCENTER_FIFO1_BZ_LVL>" << std::endl;
1918  out << " <SOUTH_FIFO1_BZ_LVL>900</SOUTH_FIFO1_BZ_LVL>" << std::endl;
1919  out << " <FIFO3_WRN_LVL>7680</FIFO3_WRN_LVL> " << std::endl;
1920  out << " <FED_MASTER_DELAY>0</FED_MASTER_DELAY>" << std::endl;
1921  out << " <NO_HITLIMIT>0</NO_HITLIMIT>" << std::endl;
1922  out << " <NC_HITLIMIT>0</NC_HITLIMIT>" << std::endl;
1923  out << " <SC_HITLIMIT>0</SC_HITLIMIT>" << std::endl;
1924  out << " <SO_HITLIMIT>0</SO_HITLIMIT>" << std::endl;
1925  out << " <NO_TESTREG>0</NO_TESTREG>" << std::endl;
1926  out << " <NC_TESTREG>0</NC_TESTREG>" << std::endl;
1927  out << " <SC_TESTREG>0</SC_TESTREG>" << std::endl;
1928  out << " <SO_TESTREG>0</SO_TESTREG>" << std::endl;
1929  out << " <BUSYWHENBEHIND>4</BUSYWHENBEHIND>" << std::endl;
1930  out << " <FEATUREREGISTER>0X1234</FEATUREREGISTER>" << std::endl;
1931  out << " <FIFO2LIMIT>0X1C00</FIFO2LIMIT>" << std::endl;
1932  out << " <TIMEOUTOROOSLIMIT>0</TIMEOUTOROOSLIMIT>" << std::endl;
1933  out << " <LASTDACOFF>0</LASTDACOFF>" << std::endl;
1934  out << " <SIMHITSPERROC>0</SIMHITSPERROC>" << std::endl;
1935  out << " <BUSYHOLDMIN>0</BUSYHOLDMIN>" << std::endl;
1936  out << " <SPARE1>0</SPARE1>" << std::endl;
1937  out << " <SPARE2>0</SPARE2>" << std::endl;
1938  out << " <SPARE3>0</SPARE3>" << std::endl;
1939  out << " <SPARE4>0</SPARE4>" << std::endl;
1940  out << " <SPARE5>0</SPARE5>" << std::endl;
1941  out << " <SPARE6>0</SPARE6>" << std::endl;
1942  out << " <SPARE7>0</SPARE7>" << std::endl;
1943  out << " <SPARE8>0</SPARE8>" << std::endl;
1944  out << " <SPARE9>0</SPARE9>" << std::endl;
1945  out << " <SPARE10>0</SPARE10>" << std::endl;
1946  out << " </DATA>" << std::endl;
1947  /*
1948  out<< " <DATA>
1949  <OPT1_CAP>0</OPT1_CAP>
1950  <OPT2_CAP>0</OPT2_CAP>
1951  <OPT3_CAP>0</OPT3_CAP>
1952  <OPT1_INP>0</OPT1_INP>
1953  <OPT2_INP>0</OPT2_INP>
1954  <OPT3_INP>0</OPT3_INP>
1955  <OPT1_OUT>0</OPT1_OUT>
1956  <OPT2_OUT>0</OPT2_OUT>
1957  <OPT3_OUT>0</OPT3_OUT>
1958  <NORTH_CLKPHB>511</NORTH_CLKPHB>
1959  <NORTHCENTER_CLKPHB>511</NORTHCENTER_CLKPHB>
1960  <SOUTHCENTER_CLKPHB>511</SOUTHCENTER_CLKPHB>
1961  <SOUTH_CLKPHB>511</SOUTH_CLKPHB>
1962  <NORTH_CTRL>0</NORTH_CTRL>
1963  <NORTHCENTER_CTRL>0</NORTHCENTER_CTRL>
1964  <SOUTHCENTER_CTRL>0</SOUTHCENTER_CTRL>
1965  <SOUTH_CTRL>0</SOUTH_CTRL>
1966  <REG1_TTCRX_FDLA>5</REG1_TTCRX_FDLA>
1967  <REG2_TTCRX_CDLA>0</REG2_TTCRX_CDLA>
1968  <REG3_TTCRX_CLKD2>155</REG3_TTCRX_CLKD2>
1969  <CENTER_CTRL>0</CENTER_CTRL>
1970  <CENTER_MODE>0</CENTER_MODE>
1971  <B1_ADCGN>0</B1_ADCGN>
1972  <B2_ADCGN>0</B2_ADCGN>
1973  <B3_ADCGN>0</B3_ADCGN>
1974  <B4_ADCGN>0</B4_ADCGN>
1975  <NORTH_BADJ>330</NORTH_BADJ>
1976  <NORTHCENTER_BADJ>330</NORTHCENTER_BADJ>
1977  <SOUTHCENTER_BADJ>330</SOUTHCENTER_BADJ>
1978  <SOUTH_BADJ>330</SOUTH_BADJ>
1979  <NORTH_TBMMASK>2</NORTH_TBMMASK>
1980  <NORTHCENTER_TBMMASK>2</NORTHCENTER_TBMMASK>
1981  <SOUTHCENTER_TBMMASK>2</SOUTHCENTER_TBMMASK>
1982  <SOUTH_TBMMASK>2</SOUTH_TBMMASK>
1983  <NORTH_PWORD>177</NORTH_PWORD>
1984  <NORTHCENTER_PWORD>178</NORTHCENTER_PWORD>
1985  <SOUTHCENTER_PWORD>179</SOUTHCENTER_PWORD>
1986  <SOUTH_PWORD>180</SOUTH_PWORD>
1987  <SPECDAC>0</SPECDAC>
1988  <OOS_LVL>0</OOS_LVL>
1989  <ERR_LVL>0</ERR_LVL>
1990  <NORTH_FIFO1_BZ_LVL>900</NORTH_FIFO1_BZ_LVL>
1991  <NORTHCENTER_FIFO1_BZ_LVL>900</NORTHCENTER_FIFO1_BZ_LVL>
1992  <SOUTHCENTER_FIFO1_BZ_LVL>900</SOUTHCENTER_FIFO1_BZ_LVL>
1993  <SOUTH_FIFO1_BZ_LVL>900</SOUTH_FIFO1_BZ_LVL>
1994  <FIFO3_WRN_LVL>7680</FIFO3_WRN_LVL>
1995  </DATA>
1996 
1997  </DATA_SET>
1998  out << " </DATA_SET>" << std::endl ;
1999  out << "</ROOT>" << std::endl ;
2000 
2001  out.close() ;
2002 */
2003  std::cout << __LINE__ << "]\t" << mthn << "Data written" << std::endl;
2004 }
2005 
2006 //=============================================================================================
2007 uint64_t PixelFEDCard::enabledChannels() {
2008  uint64_t channels = 0;
2009  // return a 64-bit word with low 36 bits set if a channel is enabled
2010  // if bits are set in the control registers, transfer of data from
2011  // fifo1 to fifo 2 is not done, meaning the channel is disabled.
2012  channels = (Ncntrl & 0x1ffLL); // Add LL for SLC4, d.k. 12/07
2013  channels += (NCcntrl & 0x1ffLL) << 9;
2014  channels += (SCcntrl & 0x1ffLL) << 18;
2015  channels += (Scntrl & 0x1ffLL) << 27;
2016  return ~channels; //bitwise complement to get enabled channels
2017 }
2018 
2019 bool PixelFEDCard::useChannel(unsigned int iChannel) {
2020  assert(iChannel > 0 && iChannel < 37);
2021  return (enabledChannels() >> (iChannel - 1)) & 0x1LL;
2022 }
2023 
2024 void PixelFEDCard::setChannel(unsigned int iChannel, bool mode) {
2025  assert(iChannel > 0 && iChannel < 37);
2026  long long mask = enabledChannels();
2027  long long bit = 0x1LL << (iChannel - 1);
2028  if (mode) {
2029  mask = mask | bit;
2030  } else {
2031  bit = ~bit;
2032  mask = mask & bit;
2033  }
2034  mask = ~mask;
2035  Ncntrl = (Ncntrl & 0xffff0000LL) | (mask & 0x1ffLL);
2036  mask = mask >> 9;
2037  NCcntrl = (NCcntrl & 0xffff0000LL) | (mask & 0x1ffLL);
2038  mask = mask >> 9;
2039  SCcntrl = (SCcntrl & 0xffff0000LL) | (mask & 0x1ffLL);
2040  mask = mask >> 9;
2041  Scntrl = (Scntrl & 0xffff0000LL) | (mask & 0x1ffLL);
2042 }
2043 
2044 void PixelFEDCard::restoreBaselinAndChannelMasks() {
2045  Ncntrl = Ncntrl_original;
2046  NCcntrl = NCcntrl_original;
2047  SCcntrl = SCcntrl_original;
2048  Scntrl = Scntrl_original;
2049 
2050  Nbaseln = Nbaseln_original;
2051  NCbaseln = NCbaseln_original;
2052  SCbaseln = SCbaseln_original;
2053  Sbaseln = Sbaseln_original;
2054 }
2055 
2056 void PixelFEDCard::restoreControlAndModeRegister() {
2057  Ccntrl = Ccntrl_original;
2058  modeRegister = modeRegister_original;
2059 }
2060 
2061 /* Emacs specific customization
2062  ;;; Local Variables: ***
2063  ;;; indent-tabs-mode:nil ***
2064  ;;; c-set-style:gnu ***
2065  ;;; End: ***
2066 */
pos::PixelFEDCard::FEDBASE_0
unsigned long FEDBASE_0
Definition: PixelFEDCard.h:146
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This file contains the base class for &quot;pixel configuration data&quot; management.
Definition: PixelConfigBase.h:32
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const edm::EventSetup & c
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int ROC_L3[36][26]
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Definition: PixelFEDCard.h:99
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Definition: PixelFEDCard.cc:2044
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Definition: PixelFEDCard.h:121
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Definition: PixelFEDCard.cc:2056
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Definition: PixelFEDCard.h:89
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Definition: relval_steps.py:3502
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Definition: PixelFEDCard.h:99
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Definition: PixelFEDCard.h:121
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Definition: PixelFEDCard.h:86
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Definition: Matrix.h:45
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Definition: PixelFEDCard.h:118
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Definition: PixelTimeFormatter.h:94
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Definition: PixelFEDCard.cc:2019
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Definition: PixelFEDCard.h:121
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Definition: PixelTimeFormatter.h:61
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Definition: PixelFEDCard.cc:395
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Definition: DeadROC_duringRun.py:23
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prepare the HTCondor submission files and eventually submit them
Definition: submitPVResolutionJobs.py:398
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This class provides utility methods to manipulate ASCII formatted timestamps.
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Definition: PixelFEDCard.h:96
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Definition: PixelFEDCard.cc:1823
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Definition: PixelConfigKey.h:20
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Definition: PixelFEDCard.h:93
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Definition: PixelFEDCard.h:72
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Definition: fed_dqm_sourceclient-live_cfg.py:47
PixelFEDCard.h
This class implements..
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Definition: PixelFEDCard.cc:1812
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Definition: PixelFEDCard.h:99
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Definition: PixelFEDCard.cc:2007
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void setChannel(unsigned int iChannel, bool mode)
Definition: PixelFEDCard.cc:2024
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