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SiStripSpyDigiConverter.h
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1 #ifndef DQM_SiStripMonitorHardware_SiStripSpyDigiConverter_H
2 #define DQM_SiStripMonitorHardware_SiStripSpyDigiConverter_H
3 
4 #include <memory>
5 #include <vector>
6 
9 
11 #include <cstdint>
12 
13 // Forward define other classes
14 class SiStripFedCabling;
15 
16 namespace sistrip {
17 
26  public:
28 
29  //all methods are static so no instances are needed but allow anyway
32 
38  static std::unique_ptr<DSVRawDigis> extractPayloadDigis(const DSVRawDigis* inputScopeDigis,
39  std::vector<uint32_t>* pAPVAddresses,
40  const bool discardDigisWithAPVAddrErr,
42  const uint16_t expectedPos);
43 
44  /* \brief Reorder from readout order to physical order */
45  static std::unique_ptr<DSVRawDigis> reorderDigis(const DSVRawDigis* inputPayloadDigis);
46 
47  /* \brief Merge channel digis into modules. */
48  static std::unique_ptr<DSVRawDigis> mergeModuleChannels(const DSVRawDigis* inputPhysicalOrderChannelDigis,
49  const SiStripFedCabling& cabling);
50 
51  private:
53 
54  static void processFED(const uint16_t aPreviousFedId,
55  const bool discardDigisWithAPVAddrErr,
56  std::vector<uint32_t>* pAPVAddresses,
57  std::vector<DetSetRawDigis>& outputData,
58  std::vector<uint16_t>& aAddrVec,
59  std::vector<uint16_t>& aHeaderBitVec,
60  std::vector<uint16_t>& aTrailBitVec,
61  std::vector<DSVRawDigis::const_iterator>& aFedScopeDigis);
62 
63  }; // end of SpyDigiConverter class.
64 
65 } // namespace sistrip
66 
67 #endif // DQM_SiStripMonitorHardware_SiStripSpyDigiConverter_H
static std::unique_ptr< DSVRawDigis > reorderDigis(const DSVRawDigis *inputPayloadDigis)
Converts scope mode like digis into virgin raw like digis by: -extracting the frame payload...
DSVRawDigis::detset DetSetRawDigis
static std::unique_ptr< DSVRawDigis > extractPayloadDigis(const DSVRawDigis *inputScopeDigis, std::vector< uint32_t > *pAPVAddresses, const bool discardDigisWithAPVAddrErr, const sistrip::SpyUtilities::FrameQuality &aQuality, const uint16_t expectedPos)
Extract frames from the scope digis.
static std::unique_ptr< DSVRawDigis > mergeModuleChannels(const DSVRawDigis *inputPhysicalOrderChannelDigis, const SiStripFedCabling &cabling)
edm::DetSetVector< SiStripRawDigi > DSVRawDigis
Contains cabling info at the device level, including DetId, APV pair numbers, hardware addresses...
static void processFED(const uint16_t aPreviousFedId, const bool discardDigisWithAPVAddrErr, std::vector< uint32_t > *pAPVAddresses, std::vector< DetSetRawDigis > &outputData, std::vector< uint16_t > &aAddrVec, std::vector< uint16_t > &aHeaderBitVec, std::vector< uint16_t > &aTrailBitVec, std::vector< DSVRawDigis::const_iterator > &aFedScopeDigis)