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int | addr_to_ival (int addr) |
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int | gen_inv (int i) |
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void | initLUT (double offset) |
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double | Ioffset () |
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int | ival_to_addr (int ival) |
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void | local_calculate () override |
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double | offset () |
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void | print (std::ofstream &fs, HLS, int l1=0, int l2=0, int l3=0) override |
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void | print (std::ofstream &fs, Verilog, int l1=0, int l2=0, int l3=0) override |
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void | set_mode (mode m) |
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| VarInv (imathGlobals *globals, std::string name, VarBase *p1, double offset, int nbits, int n, unsigned int shift, mode m, int nbaddr=-1) |
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void | writeLUT (std::ofstream &fs) const |
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void | writeLUT (std::ofstream &fs, HLS) const |
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void | writeLUT (std::ofstream &fs, Verilog) const |
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| ~VarInv () override |
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void | add_cut (VarCut *cut, const bool call_set_cut_var=true) |
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void | add_delay (int i) |
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void | add_latency (unsigned int l) |
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void | analyze () |
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bool | calculate () |
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bool | calculate (int debug_level) |
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VarBase * | cut_var () |
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std::string | dump () |
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void | dump_msg () |
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double | fval () const |
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bool | has_delay (int i) |
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void | inputs (std::vector< VarBase * > *vd) |
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long int | ival () const |
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double | K () const |
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std::map< std::string, int > | Kmap () const |
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std::string | kstring () const |
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int | latency () const |
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bool | local_passes () const |
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void | makeready () |
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double | maxval () const |
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double | minval () const |
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std::string | name () const |
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int | nbits () const |
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std::string | op () const |
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VarBase * | p1 () const |
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VarBase * | p2 () const |
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VarBase * | p3 () const |
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void | passes (std::map< const VarBase *, std::vector< bool > > &passes, const std::map< const VarBase *, std::vector< bool > > *const previous_passes=nullptr) const |
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int | pipe_counter () |
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std::string | pipe_delays (const int step) |
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void | pipe_increment () |
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void | print_all (std::ofstream &fs, HLS) |
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void | print_all (std::ofstream &fs, Verilog) |
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void | print_cuts (std::map< const VarBase *, std::set< std::string > > &cut_strings, const int step, HLS, const std::map< const VarBase *, std::set< std::string > > *const previous_cut_strings=nullptr) const |
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void | print_cuts (std::map< const VarBase *, std::set< std::string > > &cut_strings, const int step, Verilog, const std::map< const VarBase *, std::set< std::string > > *const previous_cut_strings=nullptr) const |
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void | print_step (int step, std::ofstream &fs, HLS) |
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void | print_step (int step, std::ofstream &fs, Verilog) |
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void | print_truncation (std::string &t, const std::string &o1, const int ps, HLS) const |
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void | print_truncation (std::string &t, const std::string &o1, const int ps, Verilog) const |
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double | range () const |
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void | reset () |
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int | shift () const |
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int | step () const |
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| VarBase (imathGlobals *globals, std::string name, VarBase *p1, VarBase *p2, VarBase *p3, int l) |
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virtual | ~VarBase () |
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static void | design_print (const std::vector< VarBase * > &v, std::ofstream &fs, HLS) |
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static void | design_print (const std::vector< VarBase * > &v, std::ofstream &fs, Verilog) |
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static void | hls_print (const std::vector< VarBase * > &v, std::ofstream &fs) |
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static std::string | itos (int i) |
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static std::string | pipe_delay (VarBase *v, int nbits, int delay) |
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static std::string | pipe_delay_wire (VarBase *v, std::string name_delayed, int nbits, int delay) |
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static void | verilog_print (const std::vector< VarBase * > &v, std::ofstream &fs) |
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static struct trklet::VarBase::HLS | hls |
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static struct trklet::VarBase::Verilog | verilog |
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Definition at line 955 of file imath.h.
trklet::VarInv::VarInv |
( |
imathGlobals * |
globals, |
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std::string |
name, |
|
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VarBase * |
p1, |
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double |
offset, |
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int |
nbits, |
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int |
n, |
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unsigned int |
shift, |
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mode |
m, |
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int |
nbaddr = -1 |
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) |
| |
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inline |
Definition at line 959 of file imath.h.
984 const std::map<std::string, int> map1 =
p1->
Kmap();
985 for (
const auto &it : map1)
986 Kmap_[it.first] = -it.second;
References addr_to_ival(), ashift_, reco::HaloData::both, gen_inv(), mps_fire::i, testProducerWithPsetDescEmpty_cfi::i1, createfilelist::int, trklet::VarBase::K(), trklet::VarBase::K_, trklet::VarBase::Kmap(), trklet::VarBase::Kmap_, visualization-live-secondInstance_cfg::m, m_, mask_, dqmiodumpmetadata::n, n_, nbaddr_, trklet::VarBase::nbits(), trklet::VarBase::nbits_, Nelements_, offset(), offset_, trklet::VarBase::op_, trklet::VarBase::p1(), trklet::VarBase::p1_, funct::pow(), trklet::VarBase::shift(), and shift_.
void VarInv::print |
( |
std::ofstream & |
fs, |
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Verilog |
, |
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int |
l1 = 0 , |
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int |
l2 = 0 , |
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int |
l3 = 0 |
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) |
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overridevirtual |
Reimplemented from trklet::VarBase.
Definition at line 287 of file imath_Verilog.cc.
293 n1 = n1 +
"_delay" +
itos(l1);
297 t =
t +
"assign " +
t1 +
" = ";
302 fs <<
t <<
"; // address for the LUT\n";
309 fs <<
"Memory #( \n";
310 fs <<
" .RAM_WIDTH(" <<
nbits_ <<
"), // Specify RAM data width \n";
311 fs <<
" .RAM_DEPTH(" <<
Nelements_ <<
"), // Specify RAM depth (number of entries) \n";
312 fs <<
" .RAM_PERFORMANCE(\"HIGH_PERFORMANCE\"), // \"HIGH_PERFORMANCE\" = 2 clks latency \n";
313 fs <<
" .INIT_FILE() \n";
314 fs <<
" ) " <<
t2 <<
" ( \n";
315 fs <<
" .addra(" <<
itos(
nbaddr_) <<
"\'b0), // Write address bus, width determined from RAM_DEPTH \n";
316 fs <<
" .addrb(" <<
t1 <<
" ), // Read address bus, width determined from RAM_DEPTH \n";
317 fs <<
" .dina(" <<
itos(
nbits_) <<
"\'b0), // RAM input data, width determined from RAM_WIDTH \n";
318 fs <<
" .clka(clk), // Write clock \n";
319 fs <<
" .clkb(clk), // Read clock \n";
320 fs <<
" .wea(1\'b0), // Write enable \n";
321 fs <<
" .enb(1\'b1), // Read Enable, for additional power savings, disable when not in use \n";
322 fs <<
" .rstb(reset), // Output reset (does not affect memory contents) \n";
323 fs <<
" .regceb(1\'b1), // Output register enable \n";
324 fs <<
" .doutb(" <<
name_ <<
") // RAM output data, \n";
References cms::cuda::assert(), trklet::VarBase::itos(), mask_, trklet::VarBase::name(), trklet::VarBase::name_, nbaddr_, trklet::VarBase::nbits_, Nelements_, trklet::VarBase::p1_, shift_, AlCaHLTBitMon_QueryRunRegistry::string, submitPVValidationJobs::t, RandomServiceHelper::t1, and RandomServiceHelper::t2.