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L1GtHwValidation.cc
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1 
16 // this class header
17 #include "DQM/L1TMonitor/interface/L1GtHwValidation.h"
18 
19 // system include files
20 #include <memory>
21 #include <iostream>
22 #include <iomanip>
23 
24 // user include files
25 #include "DataFormats/L1GlobalTrigger/interface/L1GlobalTriggerReadoutSetup.h"
26 #include "DataFormats/L1GlobalTrigger/interface/L1GlobalTriggerReadoutRecord.h"
27 #include "DataFormats/L1GlobalTrigger/interface/L1GlobalTriggerEvmReadoutRecord.h"
28 
29 #include "FWCore/MessageLogger/interface/MessageLogger.h"
30 #include "FWCore/ServiceRegistry/interface/Service.h"
31 
32 #include "FWCore/Framework/interface/EventSetup.h"
33 #include "FWCore/Framework/interface/ESHandle.h"
34 #include "FWCore/Framework/interface/Run.h"
35 
36 #include "CondFormats/L1TObjects/interface/L1GtTriggerMenu.h"
37 #include "CondFormats/DataRecord/interface/L1GtTriggerMenuRcd.h"
38 
39 #include "CondFormats/L1TObjects/interface/L1GtPrescaleFactors.h"
40 #include "CondFormats/DataRecord/interface/L1GtPrescaleFactorsAlgoTrigRcd.h"
41 #include "CondFormats/DataRecord/interface/L1GtPrescaleFactorsTechTrigRcd.h"
42 
43 #include "CondFormats/L1TObjects/interface/L1GtTriggerMask.h"
44 #include "CondFormats/DataRecord/interface/L1GtTriggerMaskAlgoTrigRcd.h"
45 #include "CondFormats/DataRecord/interface/L1GtTriggerMaskTechTrigRcd.h"
46 
47 #include "TH1.h"
48 #include "TH2.h"
49 #include "TTree.h"
50 
51 // constructor(s)
52 L1GtHwValidation::L1GtHwValidation(const edm::ParameterSet& paramSet)
53  : //
54  // input tag for the L1 GT hardware DAQ record
55  m_l1GtDataDaqInputTag(paramSet.getParameter<edm::InputTag>("L1GtDataDaqInputTag")),
56  // input tag for the L1 GT hardware EVM record
57  m_l1GtDataEvmInputTag(paramSet.getParameter<edm::InputTag>("L1GtDataEvmInputTag")),
58  // input tag for the L1 GT emulator DAQ record
59  m_l1GtEmulDaqInputTag(paramSet.getParameter<edm::InputTag>("L1GtEmulDaqInputTag")),
60  // input tag for the L1 GT emulator EVM record
61  m_l1GtEmulEvmInputTag(paramSet.getParameter<edm::InputTag>("L1GtEmulEvmInputTag")),
62  // input tag for the L1 GCT hardware record
63  m_l1GctDataInputTag(paramSet.getParameter<edm::InputTag>("L1GctDataInputTag")),
64  //
65  m_dirName(paramSet.getUntrackedParameter("DirName", std::string("L1TEMU/GTexpert"))),
66  //
67  m_excludeCondCategTypeObject(
68  paramSet.getParameter<std::vector<edm::ParameterSet> >("ExcludeCondCategTypeObject")),
69  //
70  m_excludeAlgoTrigByName(paramSet.getParameter<std::vector<std::string> >("ExcludeAlgoTrigByName")),
71  //
72  m_excludeAlgoTrigByBit(paramSet.getParameter<std::vector<int> >("ExcludeAlgoTrigByBit")),
73  //
74  // initialize counters
75  m_nrDataEventError(0),
76  m_nrEmulEventError(0),
77  // cache
78  m_l1GtMenuCacheID(0ULL),
79  m_l1GtPfAlgoCacheID(0ULL),
80  m_l1GtPfTechCacheID(0ULL),
81  m_l1GtTmAlgoCacheID(0ULL),
82  m_l1GtTmTechCacheID(0ULL),
83  //
84  m_agree(true),
85  m_dataOnly(false),
86  m_emulOnly(false),
87  m_dataOnlyMask(false),
88  m_emulOnlyMask(false),
89  //
90  m_nrEvJob(0),
91  m_nrEvRun(0) {
92  for (std::vector<edm::ParameterSet>::const_iterator itExclud = m_excludeCondCategTypeObject.begin();
93  itExclud != m_excludeCondCategTypeObject.end();
94  ++itExclud) {
95  if (!(itExclud->getParameter<std::string>("ExcludedCondCategory")).empty()) {
96  m_excludedCondCategory.push_back(
97  l1GtConditionCategoryStringToEnum(itExclud->getParameter<std::string>("ExcludedCondCategory")));
98 
99  } else {
100  m_excludedCondCategory.push_back(CondNull);
101  }
102 
103  if (!(itExclud->getParameter<std::string>("ExcludedCondType")).empty()) {
104  m_excludedCondType.push_back(
105  l1GtConditionTypeStringToEnum(itExclud->getParameter<std::string>("ExcludedCondType")));
106 
107  } else {
108  m_excludedCondType.push_back(TypeNull);
109  }
110 
111  if (!(itExclud->getParameter<std::string>("ExcludedL1GtObject")).empty()) {
112  m_excludedL1GtObject.push_back(l1GtObjectStringToEnum(itExclud->getParameter<std::string>("ExcludedL1GtObject")));
113 
114  } else {
115  m_excludedL1GtObject.push_back(ObjNull);
116  }
117  }
118 
119  LogDebug("L1GtHwValidation") << "\nInput tag for the L1 GT DAQ hardware record: " << m_l1GtDataDaqInputTag
120  << "\nInput tag for the L1 GT EVM hardware record: " << m_l1GtDataEvmInputTag
121  << "\nInput tag for the L1 GT DAQ emulator records: " << m_l1GtEmulDaqInputTag
122  << "\nInput tag for the L1 GT EVM emulator records: " << m_l1GtEmulEvmInputTag
123  << "\nInput tag for the L1 GCT hardware record: " << m_l1GctDataInputTag
124  << std::endl;
125 
126  // FIXME print in debug mode ExcludeCondCategTypeObject, ExcludeAlgoTrigByName, etc
127 
128  //set Token(-s)
129  m_l1GtDataDaqInputToken_ =
130  consumes<L1GlobalTriggerReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtDataDaqInputTag"));
131  m_l1GtEmulDaqInputToken_ =
132  consumes<L1GlobalTriggerReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtEmulDaqInputTag"));
133  m_l1GtDataEvmInputToken_ =
134  consumes<L1GlobalTriggerEvmReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtDataEvmInputTag"));
135  m_l1GtEmulEvmInputToken_ =
136  consumes<L1GlobalTriggerEvmReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtEmulEvmInputTag"));
137  l1gtPrescaleTechToken_ = esConsumes<edm::Transition::BeginRun>();
138  l1gtPrescaleAlgoToken_ = esConsumes<edm::Transition::BeginRun>();
139  l1gtTrigmenuToken_ = esConsumes<edm::Transition::BeginRun>();
140  l1gtTrigmaskTechToken_ = esConsumes<edm::Transition::BeginRun>();
141  l1gtTrigmaskAlgoToken_ = esConsumes<edm::Transition::BeginRun>();
142 }
143 
144 // destructor
145 L1GtHwValidation::~L1GtHwValidation() {
146  // empty
147 }
148 
149 // member functions
150 
151 void L1GtHwValidation::bookHistograms(DQMStore::IBooker& ibooker,
152  const edm::Run& iRun,
153  const edm::EventSetup& evSetup) {
154  ibooker.setCurrentFolder(m_dirName);
155 
156  // histograms
157 
158  const unsigned int numberTechTriggers = L1GlobalTriggerReadoutSetup::NumberTechnicalTriggers;
159 
160  const unsigned int numberAlgoTriggers = L1GlobalTriggerReadoutSetup::NumberPhysTriggers;
161 
162  for (int iRec = 0; iRec < NumberOfGtRecords; ++iRec) {
163  std::string recString;
164  if (iRec == 0) {
165  recString = "Daq_";
166  ibooker.setCurrentFolder(m_dirName + "/DAQ/");
167 
168  } else {
169  recString = "Evm_";
170  ibooker.setCurrentFolder(m_dirName + "/EVM/");
171  }
172 
173  std::string hName;
174  const char* histName;
175 
176  hName = recString + "gtfeDataEmul";
177  histName = hName.c_str();
178 
179  // GTFE histograms
180  m_gtfeDataEmul[iRec] = ibooker.book1D(histName, "GTFE data vs emul mismatch", 8, 0., 7.);
181  m_gtfeDataEmul[iRec]->setBinLabel(1, "BoardId", 1);
182  m_gtfeDataEmul[iRec]->setBinLabel(2, "RecordLength1", 1);
183  m_gtfeDataEmul[iRec]->setBinLabel(3, "RecordLength0", 1);
184  m_gtfeDataEmul[iRec]->setBinLabel(4, "BxNr", 1);
185  m_gtfeDataEmul[iRec]->setBinLabel(5, "SetupVersion", 1);
186  m_gtfeDataEmul[iRec]->setBinLabel(6, "DaqActiveBoards", 1);
187  m_gtfeDataEmul[iRec]->setBinLabel(7, "AltNrBxBoard", 1);
188  m_gtfeDataEmul[iRec]->setBinLabel(8, "TotalTriggerNr", 1);
189 
190  // FDL histograms
191 
192  for (int iHist = 0; iHist < TotalBxInEvent; ++iHist) {
193  // convert [0, TotalBxInEvent] to [-X, +X] and add to histogram name
194  int iIndex = iHist - ((TotalBxInEvent + 1) / 2 - 1);
195  int hIndex = (iIndex + 16) % 16;
196 
197  std::stringstream ss;
198  std::string str;
199  ss << std::uppercase << std::hex << hIndex;
200  ss >> str;
201 
202  if (iRec == 0) {
203  ibooker.setCurrentFolder(m_dirName + "/DAQ/BxInEvent_" + str);
204 
205  } else {
206  ibooker.setCurrentFolder(m_dirName + "/EVM/BxInEvent_" + str);
207  }
208 
209  hName = recString + "FdlDataEmul_" + str;
210  histName = hName.c_str();
211 
212  std::string hTitle = "FDL data vs emul mismatch for BxInEvent = " + str;
213  const char* histTitle = hTitle.c_str();
214 
215  //
216 
217  m_fdlDataEmul[iHist][iRec] = ibooker.book1D(histName, histTitle, 13, 0., 13.);
218  m_fdlDataEmul[iHist][iRec]->setBinLabel(1, "BoardId", 1);
219  m_fdlDataEmul[iHist][iRec]->setBinLabel(2, "BxInEvent", 1);
220  m_fdlDataEmul[iHist][iRec]->setBinLabel(3, "BxNr", 1);
221  m_fdlDataEmul[iHist][iRec]->setBinLabel(4, "EventNr", 1);
222  m_fdlDataEmul[iHist][iRec]->setBinLabel(5, "TechTrigger", 1);
223  m_fdlDataEmul[iHist][iRec]->setBinLabel(6, "TechTriggerMask", 1);
224  m_fdlDataEmul[iHist][iRec]->setBinLabel(7, "AlgoTrigger", 1);
225  m_fdlDataEmul[iHist][iRec]->setBinLabel(8, "AlgoTriggerMask", 1);
226  m_fdlDataEmul[iHist][iRec]->setBinLabel(9, "AlgoExtend", 1);
227  m_fdlDataEmul[iHist][iRec]->setBinLabel(10, "NoAlgo", 1);
228  m_fdlDataEmul[iHist][iRec]->setBinLabel(11, "FinalORAllParts", 1);
229  m_fdlDataEmul[iHist][iRec]->setBinLabel(12, "FinalORPhysPart", 1);
230  m_fdlDataEmul[iHist][iRec]->setBinLabel(13, "LocalBxNr", 1);
231 
232  // algorithm decision
233  // data
234  hName = recString + "Data_AlgoDecision_" + str;
235  histName = hName.c_str();
236 
237  hTitle = "Data: algorithm decision word for BxInEvent = " + str;
238  histTitle = hTitle.c_str();
239 
240  m_fdlDataAlgoDecision[iHist][iRec] =
241  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
242 
243  // emul
244  hName = recString + "Emul_AlgoDecision_" + str;
245  histName = hName.c_str();
246 
247  hTitle = "Emul: algorithm decision word for BxInEvent = " + str;
248  histTitle = hTitle.c_str();
249 
250  m_fdlEmulAlgoDecision[iHist][iRec] =
251  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
252 
253  // algorithm decision for prescaled algorithms
254  // data
255  hName = recString + "Data_AlgoDecision_Prescaled_" + str;
256  histName = hName.c_str();
257 
258  hTitle = "Data: prescaled algorithms: algorithm decision for BxInEvent = " + str;
259  histTitle = hTitle.c_str();
260 
261  m_fdlDataAlgoDecisionPrescaled[iHist][iRec] =
262  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
263 
264  // emul
265  hName = recString + "Emul_AlgoDecision_Prescaled_" + str;
266  histName = hName.c_str();
267 
268  hTitle = "Emul: prescaled algorithms: algorithm decision for BxInEvent = " + str;
269  histTitle = hTitle.c_str();
270 
271  m_fdlEmulAlgoDecisionPrescaled[iHist][iRec] =
272  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
273 
274  // algorithm decision for unprescaled algorithms
275  // data
276  hName = recString + "Data_AlgoDecision_Unprescaled_" + str;
277  histName = hName.c_str();
278 
279  hTitle = "Data: unprescaled algorithms: algorithm decision for BxInEvent = " + str;
280  histTitle = hTitle.c_str();
281 
282  m_fdlDataAlgoDecisionUnprescaled[iHist][iRec] =
283  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
284 
285  // emul
286  hName = recString + "Emul_AlgoDecision_Unprescaled_" + str;
287  histName = hName.c_str();
288 
289  hTitle = "Emul: unprescaled algorithms: algorithm decision for BxInEvent = " + str;
290  histTitle = hTitle.c_str();
291 
292  m_fdlEmulAlgoDecisionUnprescaled[iHist][iRec] =
293  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
294 
295  // algorithm decision after masking (partition physics)
296  // data
297  hName = recString + "Data_AlgoDecisionAfterMask_" + str;
298  histName = hName.c_str();
299 
300  hTitle = "Data, physics partition: algorithm decision word after mask for BxInEvent = " + str;
301  histTitle = hTitle.c_str();
302 
303  m_fdlDataAlgoDecisionMask[iHist][iRec] =
304  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
305 
306  // emul
307  hName = recString + "Emul_AlgoDecisionAfterMask_" + str;
308  histName = hName.c_str();
309 
310  hTitle = "Emul, physics partition: algorithm decision word after mask for BxInEvent = " + str;
311  histTitle = hTitle.c_str();
312 
313  m_fdlEmulAlgoDecisionMask[iHist][iRec] =
314  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
315 
316  //
317  hName = recString + "DataEmul_AlgoDecision_" + str;
318  histName = hName.c_str();
319 
320  hTitle = "Data vs emul: non-matching algorithm decision word for BxInEvent = " + str;
321  histTitle = hTitle.c_str();
322 
323  m_fdlDataEmulAlgoDecision[iHist][iRec] =
324  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
325 
326  //
327  hName = recString + "DataEmul_AlgoDecision_Prescaled_" + str;
328  histName = hName.c_str();
329 
330  hTitle = "Data vs emul: prescaled algorithms with non-matching decision for BxInEvent = " + str;
331  histTitle = hTitle.c_str();
332 
333  m_fdlDataEmulAlgoDecisionPrescaled[iHist][iRec] =
334  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
335 
336  //
337  hName = recString + "DataEmul_AlgoDecision_Unprescaled_" + str;
338  histName = hName.c_str();
339 
340  hTitle = "Data vs emul: unprescaled algorithms with non-matching decision for BxInEvent = " + str;
341  histTitle = hTitle.c_str();
342 
343  m_fdlDataEmulAlgoDecisionUnprescaled[iHist][iRec] =
344  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
345 
346  //
347  hName = recString + "DataEmul_AlgoDecision_Unprescaled_Allowed_" + str;
348  histName = hName.c_str();
349 
350  hTitle = "Data vs emul: unprescaled algorithms not excluded with non-matching decision for BxInEvent = " + str;
351  histTitle = hTitle.c_str();
352 
353  m_fdlDataEmulAlgoDecisionUnprescaledAllowed[iHist][iRec] =
354  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
355 
356  //
357  hName = recString + "Data_AlgoDecision_NoMatch_" + str;
358  histName = hName.c_str();
359 
360  hTitle = "Data: algorithm decision for non-matching cases for BxInEvent = " + str;
361  histTitle = hTitle.c_str();
362 
363  m_fdlDataAlgoDecision_NoMatch[iHist][iRec] =
364  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
365 
366  //
367  hName = recString + "Emul_AlgoDecision_NoMatch_" + str;
368  histName = hName.c_str();
369 
370  hTitle = "Emul: algorithm decision for non-matching cases for BxInEvent = " + str;
371  histTitle = hTitle.c_str();
372 
373  m_fdlEmulAlgoDecision_NoMatch[iHist][iRec] =
374  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
375 
376  // prescaled algorithms
377  hName = recString + "Data_AlgoDecision_Prescaled_NoMatch_" + str;
378  histName = hName.c_str();
379 
380  hTitle = "Data: prescaled algorithms: non-matching algorithm decision for BxInEvent = " + str;
381  histTitle = hTitle.c_str();
382 
383  m_fdlDataAlgoDecisionPrescaled_NoMatch[iHist][iRec] =
384  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
385 
386  //
387  hName = recString + "Emul_AlgoDecision_Prescaled_NoMatch_" + str;
388  histName = hName.c_str();
389 
390  hTitle = "Emul: prescaled algorithms: non-matching algorithm decision for BxInEvent = " + str;
391  histTitle = hTitle.c_str();
392 
393  m_fdlEmulAlgoDecisionPrescaled_NoMatch[iHist][iRec] =
394  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
395 
396  // unprescaled algorithms - non-matching
397  hName = recString + "Data_AlgoDecision_Unprescaled_NoMatch_" + str;
398  histName = hName.c_str();
399 
400  hTitle = "Data: unprescaled algorithms: non-matching algorithm decision for BxInEvent = " + str;
401  histTitle = hTitle.c_str();
402 
403  m_fdlDataAlgoDecisionUnprescaled_NoMatch[iHist][iRec] =
404  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
405 
406  //
407  hName = recString + "Emul_AlgoDecision_Unprescaled_NoMatch_" + str;
408  histName = hName.c_str();
409 
410  hTitle = "Emul: unprescaled algorithms: non-matching algorithm decision for BxInEvent = " + str;
411  histTitle = hTitle.c_str();
412 
413  m_fdlEmulAlgoDecisionUnprescaled_NoMatch[iHist][iRec] =
414  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
415 
416  //
417  hName = recString + "Data_AlgoDecisionMask_NoMatch_" + str;
418  histName = hName.c_str();
419 
420  hTitle = "Data: algorithm decision for non-matching cases after mask for BxInEvent = " + str;
421  histTitle = hTitle.c_str();
422 
423  m_fdlDataAlgoDecisionMask_NoMatch[iHist][iRec] =
424  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
425 
426  //
427  hName = recString + "Emul_AlgoDecisionMask_NoMatch_" + str;
428  histName = hName.c_str();
429 
430  hTitle = "Emul: algorithm decision for non-matching cases after mask for BxInEvent = " + str;
431  histTitle = hTitle.c_str();
432 
433  m_fdlEmulAlgoDecisionMask_NoMatch[iHist][iRec] =
434  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
435 
436  // prescaled algorithms
437  hName = recString + "Data_AlgoDecisionMask_Prescaled_NoMatch_" + str;
438  histName = hName.c_str();
439 
440  hTitle = "Data: prescaled algorithms: non-matching algorithm decision after mask for BxInEvent = " + str;
441  histTitle = hTitle.c_str();
442 
443  m_fdlDataAlgoDecisionPrescaledMask_NoMatch[iHist][iRec] =
444  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
445 
446  //
447  hName = recString + "Emul_AlgoDecision_PrescaledMask_NoMatch_" + str;
448  histName = hName.c_str();
449 
450  hTitle = "Emul: prescaled algorithms: non-matching algorithm decision after mask for BxInEvent = " + str;
451  histTitle = hTitle.c_str();
452 
453  m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[iHist][iRec] =
454  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
455 
456  // unprescaled algorithms - non-matching
457  hName = recString + "Data_AlgoDecision_UnprescaledMask_NoMatch_" + str;
458  histName = hName.c_str();
459 
460  hTitle = "Data: unprescaled algorithms: non-matching algorithm decision after mask for BxInEvent = " + str;
461  histTitle = hTitle.c_str();
462 
463  m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[iHist][iRec] =
464  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
465 
466  //
467  hName = recString + "Emul_AlgoDecision_UnprescaledMask_NoMatch_" + str;
468  histName = hName.c_str();
469 
470  hTitle = "Emul: unprescaled algorithms: non-matching algorithm decision after mask for BxInEvent = " + str;
471  histTitle = hTitle.c_str();
472 
473  m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[iHist][iRec] =
474  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
475 
476  //
477  hName = recString + "DataEmul_AlgoDecisionAfterMask_" + str;
478  histName = hName.c_str();
479 
480  hTitle =
481  "Data vs emul, physics partition: non-matching algorithm decision word after mask for BxInEvent = " + str;
482  histTitle = hTitle.c_str();
483 
484  m_fdlDataEmulAlgoDecisionMask[iHist][iRec] =
485  ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
486 
487  // technical trigger decision
488  // data
489  hName = recString + "Data_TechDecision_" + str;
490  histName = hName.c_str();
491 
492  hTitle = "Data technical trigger decision word for BxInEvent = " + str;
493  histTitle = hTitle.c_str();
494 
495  m_fdlDataTechDecision[iHist][iRec] =
496  ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
497 
498  // emul
499  hName = recString + "Emul_TechDecision_" + str;
500  histName = hName.c_str();
501 
502  hTitle = "Emul: technical trigger decision word for BxInEvent = " + str;
503  histTitle = hTitle.c_str();
504 
505  m_fdlEmulTechDecision[iHist][iRec] =
506  ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
507 
508  // technical trigger decision after masking (partition physics)
509  hName = recString + "Data_TechDecisionAfterMask_" + str;
510  histName = hName.c_str();
511 
512  hTitle = "Data technical trigger decision word after mask for BxInEvent = " + str;
513  histTitle = hTitle.c_str();
514 
515  m_fdlDataTechDecisionMask[iHist][iRec] =
516  ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
517 
518  //
519  hName = recString + "Emul_TechDecisionAfterMask_" + str;
520  histName = hName.c_str();
521 
522  hTitle = "Emul: technical trigger decision word after mask for BxInEvent = " + str;
523  histTitle = hTitle.c_str();
524 
525  m_fdlEmulTechDecisionMask[iHist][iRec] =
526  ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
527 
528  //
529  hName = recString + "DataEmul_TechDecision_" + str;
530  histName = hName.c_str();
531 
532  hTitle = "Data vs emul: non-matching technical trigger decision word for BxInEvent = " + str;
533  histTitle = hTitle.c_str();
534 
535  m_fdlDataEmulTechDecision[iHist][iRec] =
536  ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
537 
538  hName = recString + "DataEmul_TechDecisionAfterMask_" + str;
539  histName = hName.c_str();
540 
541  hTitle = "Data vs emul: non-matching technical trigger decision word after mask for BxInEvent = " + str;
542  histTitle = hTitle.c_str();
543 
544  m_fdlDataEmulTechDecisionMask[iHist][iRec] =
545  ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
546  }
547 
548  if (iRec == 0) {
549  ibooker.setCurrentFolder(m_dirName + "/DAQ/");
550 
551  } else {
552  ibooker.setCurrentFolder(m_dirName + "/EVM/");
553  }
554 
555  hName = recString + "FdlDataEmul_Err";
556  histName = hName.c_str();
557 
558  m_fdlDataEmul_Err[iRec] =
559  ibooker.book1D(histName, "FDL data vs emul mismatch for non-matching BxInEvent in FDL payload", 13, 0., 13.);
560  m_fdlDataEmul_Err[iRec]->setBinLabel(1, "BoardId", 1);
561  m_fdlDataEmul_Err[iRec]->setBinLabel(2, "BxInEvent", 1);
562  m_fdlDataEmul_Err[iRec]->setBinLabel(3, "BxNr", 1);
563  m_fdlDataEmul_Err[iRec]->setBinLabel(4, "EventNr", 1);
564  m_fdlDataEmul_Err[iRec]->setBinLabel(5, "TechTrigger", 1);
565  m_fdlDataEmul_Err[iRec]->setBinLabel(6, "TechTriggerMask", 1);
566  m_fdlDataEmul_Err[iRec]->setBinLabel(7, "AlgoTrigger", 1);
567  m_fdlDataEmul_Err[iRec]->setBinLabel(8, "AlgoTriggerMask", 1);
568  m_fdlDataEmul_Err[iRec]->setBinLabel(9, "AlgoExtend", 1);
569  m_fdlDataEmul_Err[iRec]->setBinLabel(10, "NoAlgo", 1);
570  m_fdlDataEmul_Err[iRec]->setBinLabel(11, "FinalORAllParts", 1);
571  m_fdlDataEmul_Err[iRec]->setBinLabel(12, "FinalORPhysPart", 1);
572  m_fdlDataEmul_Err[iRec]->setBinLabel(13, "LocalBxNr", 1);
573 
574  hName = recString + "FdlDataAlgoDecision_Err";
575  histName = hName.c_str();
576 
577  m_fdlDataAlgoDecision_Err[iRec] = ibooker.book1D(histName,
578  "Data: algorithm trigger decision word, non-matching BxInEvent",
579  numberAlgoTriggers,
580  0.,
581  numberAlgoTriggers);
582 
583  //
584  hName = recString + "Emul_AlgoDecision_Err";
585  histName = hName.c_str();
586 
587  m_fdlEmulAlgoDecision_Err[iRec] = ibooker.book1D(histName,
588  "Emul: algorithm trigger decision word, non-matching BxInEvent",
589  numberAlgoTriggers,
590  0.,
591  numberAlgoTriggers);
592 
593  hName = recString + "DataEmul_AlgoDecision_Err";
594  histName = hName.c_str();
595 
596  m_fdlDataEmulAlgoDecision_Err[iRec] =
597  ibooker.book1D(histName,
598  "Data vs emul: algorithm trigger decision word, non-matching BxInEvent",
599  numberAlgoTriggers,
600  0.,
601  numberAlgoTriggers);
602 
603  //
604  hName = recString + "Data_TechDecision_Err";
605  histName = hName.c_str();
606 
607  m_fdlDataTechDecision_Err[iRec] = ibooker.book1D(histName,
608  "Data: technical trigger decision word, non-matching BxInEvent",
609  numberTechTriggers,
610  0.,
611  numberTechTriggers);
612 
613  hName = recString + "Emul_TechDecision_Err";
614  histName = hName.c_str();
615 
616  m_fdlEmulTechDecision_Err[iRec] = ibooker.book1D(histName,
617  "Emul: technical trigger decision word, non-matching BxInEvent",
618  numberTechTriggers,
619  0.,
620  numberTechTriggers);
621 
622  hName = recString + "DataEmul_TechDecision_Err";
623  histName = hName.c_str();
624 
625  m_fdlDataEmulTechDecision_Err[iRec] =
626  ibooker.book1D(histName,
627  "Data vs emul: technical trigger decision word, non-matching BxInEvent",
628  numberTechTriggers,
629  0.,
630  numberTechTriggers);
631  }
632 
633  ibooker.setCurrentFolder(m_dirName);
634 
635  //
636  m_excludedAlgorithmsAgreement = ibooker.book1D("ExcludedAlgorithmsFromAgreement",
637  "Algorithms excluded from data versus emulator agreement flag",
638  numberAlgoTriggers,
639  0.,
640  numberAlgoTriggers);
641 
642  //
643 
644  m_gtErrorFlag = ibooker.book1D("GTErrorFlag", "L1 GT error flag for data versus emulator comparison", 5, 0., 5);
645 
646  m_gtErrorFlag->setBinLabel(1, "Agree", 1);
647  m_gtErrorFlag->setBinLabel(2, "", 1);
648  m_gtErrorFlag->setBinLabel(3, "", 1);
649  m_gtErrorFlag->setBinLabel(4, "Data only", 1);
650  m_gtErrorFlag->setBinLabel(5, "Emul only", 1);
651 
652  m_nrEvRun = 0;
653 
654  // get / update the trigger menu from the EventSetup
655  // local cache & check on cacheIdentifier
656 
657  unsigned long long l1GtMenuCacheID = evSetup.get<L1GtTriggerMenuRcd>().cacheIdentifier();
658 
659  if (m_l1GtMenuCacheID != l1GtMenuCacheID) {
660  m_l1GtMenu = &evSetup.getData(l1gtTrigmenuToken_);
661 
662  // compute the list of algorithms excluded from the computing of the agreement flag
663  m_excludedAlgoList.clear();
664  excludedAlgoList();
665 
666  m_l1GtMenuCacheID = l1GtMenuCacheID;
667  }
668 
669  // FIXME when the menu changes, make a copy of histograms, and clear the old one
670  // otherwise the labels are wrong
671 
672  LogDebug("L1GtHwValidation") << "\nUsing L1 menu: \n " << m_l1GtMenu->gtTriggerMenuImplementation() << "\n"
673  << std::endl;
674 
675  const AlgorithmMap& algorithmMap = m_l1GtMenu->gtAlgorithmMap();
676 
677  for (CItAlgo itAlgo = algorithmMap.begin(); itAlgo != algorithmMap.end(); itAlgo++) {
678  const int algBitNumber = (itAlgo->second).algoBitNumber();
679 
680  std::stringstream ss;
681  std::string algBitString;
682  ss << std::uppercase << algBitNumber;
683  ss >> algBitString;
684 
685  const std::string& aName = algBitString + " " + itAlgo->first;
686  const char* algName = aName.c_str();
687 
688  for (int iRec = 0; iRec < NumberOfGtRecords; ++iRec) {
689  for (int iBxInEvent = 0; iBxInEvent < TotalBxInEvent; ++iBxInEvent) {
690  // convert [0, TotalBxInEvent] to [-X, +X]
691  int iIndex = iBxInEvent - ((TotalBxInEvent + 1) / 2 - 1);
692  int hIndex = (iIndex + 16) % 16;
693 
694  std::stringstream ss;
695  std::string str;
696  ss << std::uppercase << std::hex << hIndex;
697  ss >> str;
698 
699  if (iRec == 0) {
700  //if (m_dbe) {
701  ibooker.setCurrentFolder(m_dirName + "/DAQ/BxInEvent_" + str);
702  //}
703 
704  } else {
705  //if (m_dbe) {
706  ibooker.setCurrentFolder(m_dirName + "/EVM/BxInEvent_" + str);
707  //}
708  }
709 
710  m_fdlDataAlgoDecision[iBxInEvent][iRec]->setBinLabel(algBitNumber + 1, algName, 1);
711  m_fdlDataAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(algBitNumber + 1, algName, 1);
712  m_fdlDataAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(algBitNumber + 1, algName, 1);
713  m_fdlDataAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(algBitNumber + 1, algName, 1);
714  m_fdlDataAlgoDecision_NoMatch[iBxInEvent][iRec]->setBinLabel(algBitNumber + 1, algName, 1);
715 
716  m_fdlEmulAlgoDecision[iBxInEvent][iRec]->setBinLabel(algBitNumber + 1, algName, 1);
717  m_fdlEmulAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(algBitNumber + 1, algName, 1);
718  m_fdlEmulAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(algBitNumber + 1, algName, 1);
719  m_fdlEmulAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(algBitNumber + 1, algName, 1);
720  m_fdlEmulAlgoDecision_NoMatch[iBxInEvent][iRec]->setBinLabel(algBitNumber + 1, algName, 1);
721 
722  m_fdlDataEmulAlgoDecision[iBxInEvent][iRec]->setBinLabel(algBitNumber + 1, algName, 1);
723  m_fdlDataEmulAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(algBitNumber + 1, algName, 1);
724  m_fdlDataEmulAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(algBitNumber + 1, algName, 1);
725  m_fdlDataEmulAlgoDecisionUnprescaledAllowed[iBxInEvent][iRec]->setBinLabel(algBitNumber + 1, algName, 1);
726  m_fdlDataEmulAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(algBitNumber + 1, algName, 1);
727  }
728 
729  if (iRec == 0) {
730  ibooker.setCurrentFolder(m_dirName + "/DAQ/");
731 
732  } else {
733  ibooker.setCurrentFolder(m_dirName + "/EVM/");
734  }
735 
736  m_fdlDataAlgoDecision_Err[iRec]->setBinLabel(algBitNumber + 1, algName, 1);
737 
738  m_fdlEmulAlgoDecision_Err[iRec]->setBinLabel(algBitNumber + 1, algName, 1);
739 
740  m_fdlDataEmulAlgoDecision_Err[iRec]->setBinLabel(algBitNumber + 1, algName, 1);
741  }
742 
743  //
744  for (std::vector<int>::const_iterator itAlgo = m_excludedAlgoList.begin(); itAlgo != m_excludedAlgoList.end();
745  ++itAlgo) {
746  if (algBitNumber == *itAlgo) {
747  m_excludedAlgorithmsAgreement->setBinLabel(algBitNumber + 1, algName, 1);
748  }
749  }
750  }
751 
752  // get / update the prescale factors from the EventSetup
753  // local cache & check on cacheIdentifier
754 
755  unsigned long long l1GtPfAlgoCacheID = evSetup.get<L1GtPrescaleFactorsAlgoTrigRcd>().cacheIdentifier();
756 
757  if (m_l1GtPfAlgoCacheID != l1GtPfAlgoCacheID) {
758  m_l1GtPfAlgo = &evSetup.getData(l1gtPrescaleAlgoToken_);
759 
760  m_prescaleFactorsAlgoTrig = &(m_l1GtPfAlgo->gtPrescaleFactors());
761 
762  m_l1GtPfAlgoCacheID = l1GtPfAlgoCacheID;
763  }
764 
765  unsigned long long l1GtPfTechCacheID = evSetup.get<L1GtPrescaleFactorsTechTrigRcd>().cacheIdentifier();
766 
767  if (m_l1GtPfTechCacheID != l1GtPfTechCacheID) {
768  m_l1GtPfTech = &evSetup.getData(l1gtPrescaleTechToken_);
769 
770  m_prescaleFactorsTechTrig = &(m_l1GtPfTech->gtPrescaleFactors());
771 
772  m_l1GtPfTechCacheID = l1GtPfTechCacheID;
773  }
774 
775  // get / update the trigger mask from the EventSetup
776  // local cache & check on cacheIdentifier
777 
778  unsigned long long l1GtTmAlgoCacheID = evSetup.get<L1GtTriggerMaskAlgoTrigRcd>().cacheIdentifier();
779 
780  if (m_l1GtTmAlgoCacheID != l1GtTmAlgoCacheID) {
781  m_l1GtTmAlgo = &evSetup.getData(l1gtTrigmaskAlgoToken_);
782 
783  m_triggerMaskAlgoTrig = m_l1GtTmAlgo->gtTriggerMask();
784 
785  m_l1GtTmAlgoCacheID = l1GtTmAlgoCacheID;
786  }
787 
788  unsigned long long l1GtTmTechCacheID = evSetup.get<L1GtTriggerMaskTechTrigRcd>().cacheIdentifier();
789 
790  if (m_l1GtTmTechCacheID != l1GtTmTechCacheID) {
791  m_l1GtTmTech = &evSetup.getData(l1gtTrigmaskTechToken_);
792 
793  m_triggerMaskTechTrig = m_l1GtTmTech->gtTriggerMask();
794 
795  m_l1GtTmTechCacheID = l1GtTmTechCacheID;
796  }
797 }
798 
799 //compare the GTFE board
800 void L1GtHwValidation::compareGTFE(const edm::Event& iEvent,
801  const edm::EventSetup& evSetup,
802  const L1GtfeWord& gtfeBlockData,
803  const L1GtfeWord& gtfeBlockEmul,
804  const int iRec) {
805  std::string recString;
806  if (gtfeBlockData == gtfeBlockEmul) {
807  m_myCoutStream << "\n" << recString << " Data and emulated GTFE blocks: identical.\n";
808  gtfeBlockData.print(m_myCoutStream);
809  } else {
810  m_myCoutStream << "\n" << recString << " Data and emulated GTFE blocks: different.\n";
811 
812  m_myCoutStream << "\nData: GTFE block\n";
813  gtfeBlockData.print(m_myCoutStream);
814 
815  m_myCoutStream << "\nEmul: GTFE block\n";
816  gtfeBlockEmul.print(m_myCoutStream);
817  }
818 
819  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
820 
821  m_myCoutStream.str("");
822  m_myCoutStream.clear();
823 
824  // get BoardId value
825  const uint16_t boardIdData = gtfeBlockData.boardId();
826  const uint16_t boardIdEmul = gtfeBlockEmul.boardId();
827 
828  if (boardIdData == boardIdEmul) {
829  m_myCoutStream << "\n" << recString << " Data and emulated GTFE boardId identical.";
830  m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4) << std::setfill('0') << boardIdData
831  << std::setfill(' ') << std::dec;
832  m_myCoutStream << "\n";
833 
834  } else {
835  m_myCoutStream << "\n" << recString << " Data and emulated GTFE boardId different.";
836  m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x" << std::setw(4) << std::setfill('0') << boardIdData
837  << std::setfill(' ') << std::dec;
838  m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x" << std::setw(4) << std::setfill('0') << boardIdEmul
839  << std::setfill(' ') << std::dec;
840  m_myCoutStream << "\n";
841  m_gtfeDataEmul[iRec]->Fill(0);
842  }
843 
845  const uint16_t recordLength1Data = gtfeBlockData.recordLength1();
846  const uint16_t recordLength1Emul = gtfeBlockEmul.recordLength1();
847 
848  if (recordLength1Data == recordLength1Emul) {
849  m_myCoutStream << "\n" << recString << " Data and emulated GTFE recordLength for alternative 1 identical.";
850  m_myCoutStream << "\n recordLength1() = " << recordLength1Data;
851  m_myCoutStream << "\n";
852 
853  } else {
854  m_myCoutStream << "\n" << recString << " Data and emulated GTFE recordLength for alternative 1 different.";
855  m_myCoutStream << "\n Data: recordLength1() = " << recordLength1Data;
856  m_myCoutStream << "\n Emul: recordLength1() = " << recordLength1Emul;
857  m_myCoutStream << "\n";
858  m_gtfeDataEmul[iRec]->Fill(1);
859  }
860 
862  const uint16_t recordLengthData = gtfeBlockData.recordLength();
863  const uint16_t recordLengthEmul = gtfeBlockEmul.recordLength();
864 
865  if (recordLengthData == recordLengthEmul) {
866  m_myCoutStream << "\n" << recString << " Data and emulated GTFE recordLength for alternative 0 identical.";
867  m_myCoutStream << "\n recordLength() = " << recordLengthData;
868  m_myCoutStream << "\n";
869 
870  } else {
871  m_myCoutStream << "\n" << recString << " Data and emulated GTFE recordLength for alternative 1 different.";
872  m_myCoutStream << "\n Data: recordLength() = " << recordLengthData;
873  m_myCoutStream << "\n Emul: recordLength() = " << recordLengthEmul;
874  m_myCoutStream << "\n";
875  m_gtfeDataEmul[iRec]->Fill(2);
876  }
877 
879  const uint16_t bxNrData = gtfeBlockData.bxNr();
880  const uint16_t bxNrEmul = gtfeBlockEmul.bxNr();
881 
882  if (bxNrData == bxNrEmul) {
883  m_myCoutStream << "\n" << recString << " Data and emulated GTFE bxNr identical.";
884  m_myCoutStream << "\n bxNr() = " << bxNrData;
885  m_myCoutStream << "\n";
886 
887  } else {
888  m_myCoutStream << "\n" << recString << " Data and emulated GTFE bxNr different.";
889  m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
890  m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
891  m_myCoutStream << "\n";
892  m_gtfeDataEmul[iRec]->Fill(3);
893  }
894 
896  const uint32_t setupVersionData = gtfeBlockData.setupVersion();
897  const uint32_t setupVersionEmul = gtfeBlockEmul.setupVersion();
898 
899  if (setupVersionData == setupVersionEmul) {
900  m_myCoutStream << "\n" << recString << " Data and emulated GTFE setupVersion identical.";
901  m_myCoutStream << "\n setupVersion() = " << setupVersionData;
902  m_myCoutStream << "\n";
903 
904  } else {
905  m_myCoutStream << "\n" << recString << " Data and emulated GTFE setupVersion different.";
906  m_myCoutStream << "\n Data: setupVersion() = " << setupVersionData;
907  m_myCoutStream << "\n Emul: setupVersion() = " << setupVersionEmul;
908  m_myCoutStream << "\n";
909  m_gtfeDataEmul[iRec]->Fill(4);
910  }
911 
913  const uint16_t activeBoardsData = gtfeBlockData.activeBoards();
914  const uint16_t activeBoardsEmul = gtfeBlockEmul.activeBoards();
915 
916  if (activeBoardsData == activeBoardsEmul) {
917  m_myCoutStream << "\n" << recString << " Data and emulated GTFE activeBoards identical.";
918  m_myCoutStream << "\n activeBoards() = " << std::hex << "0x" << std::setw(4) << std::setfill('0')
919  << activeBoardsData << std::setfill(' ') << std::dec;
920  m_myCoutStream << "\n";
921 
922  } else {
923  m_myCoutStream << "\n" << recString << " Data and emulated GTFE activeBoards different.";
924  m_myCoutStream << "\n Data: activeBoards() = " << std::hex << "0x" << std::setw(4) << std::setfill('0')
925  << activeBoardsData << std::setfill(' ') << std::dec;
926  m_myCoutStream << "\n Emul: activeBoards() = " << std::hex << "0x" << std::setw(4) << std::setfill('0')
927  << activeBoardsEmul << std::setfill(' ') << std::dec;
928  m_myCoutStream << "\n";
929  m_gtfeDataEmul[iRec]->Fill(5);
930  }
935  const uint16_t altNrBxBoardData = gtfeBlockData.altNrBxBoard();
936  const uint16_t altNrBxBoardEmul = gtfeBlockEmul.altNrBxBoard();
937 
938  if (altNrBxBoardData == altNrBxBoardEmul) {
939  m_myCoutStream << "\n" << recString << " Data and emulated GTFE altNrBxBoard identical.";
940  m_myCoutStream << "\n altNrBxBoard() = " << altNrBxBoardData;
941  m_myCoutStream << "\n";
942 
943  } else {
944  m_myCoutStream << "\n" << recString << " Data and emulated GTFE altNrBxBoard different.";
945  m_myCoutStream << "\n Data: altNrBxBoard() = " << altNrBxBoardData;
946  m_myCoutStream << "\n Emul: altNrBxBoard() = " << altNrBxBoardEmul;
947  m_myCoutStream << "\n";
948  m_gtfeDataEmul[iRec]->Fill(6);
949  }
950 
952  const uint32_t totalTriggerNrData = gtfeBlockData.totalTriggerNr();
953  const uint32_t totalTriggerNrEmul = gtfeBlockEmul.totalTriggerNr();
954 
955  if (totalTriggerNrData == totalTriggerNrEmul) {
956  m_myCoutStream << "\n" << recString << " Data and emulated GTFE totalTriggerNr identical.";
957  m_myCoutStream << "\n totalTriggerNr() = " << totalTriggerNrData;
958  m_myCoutStream << "\n";
959 
960  } else {
961  m_myCoutStream << "\n" << recString << " Data and emulated GTFE totalTriggerNr different.";
962  m_myCoutStream << "\n Data: totalTriggerNr() = " << totalTriggerNrData;
963  m_myCoutStream << "\n Emul: totalTriggerNr() = " << totalTriggerNrEmul;
964  m_myCoutStream << "\n";
965  m_gtfeDataEmul[iRec]->Fill(7);
966  }
967 
968  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
969  m_myCoutStream.str("");
970  m_myCoutStream.clear();
971 }
972 
973 //compare the FDL board
974 void L1GtHwValidation::compareFDL(const edm::Event& iEvent,
975  const edm::EventSetup& evSetup,
976  const L1GtFdlWord& fdlBlockData,
977  const L1GtFdlWord& fdlBlockEmul,
978  const int iRec) {
979  // index of physics partition
980  int PhysicsPartition = 0;
981 
982  //
983  std::string recString;
984 
985  if (fdlBlockData == fdlBlockEmul) {
986  m_myCoutStream << "\n" << recString << " Data and emulated FDL blocks: identical.\n";
987  fdlBlockData.print(m_myCoutStream);
988 
989  } else {
990  m_myCoutStream << "\n" << recString << " Data and emulated FDL blocks: different.\n";
991 
992  m_myCoutStream << "\nData: FDL block\n";
993  fdlBlockData.print(m_myCoutStream);
994 
995  m_myCoutStream << "\nEmul: FDL block\n";
996  fdlBlockEmul.print(m_myCoutStream);
997  }
998 
999  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1000 
1001  m_myCoutStream.str("");
1002  m_myCoutStream.clear();
1003 
1004  // get bunch cross in the GT event record -
1005  // move it first as histograms are BxInEvent dependent
1006  const int bxInEventData = fdlBlockData.bxInEvent();
1007  const int bxInEventEmul = fdlBlockEmul.bxInEvent();
1008 
1009  bool matchBxInEvent = false;
1010 
1011  if (bxInEventData == bxInEventEmul) {
1012  m_myCoutStream << "\n" << recString << " Data and emulated FDL bxInEvent identical.";
1013  m_myCoutStream << "\n bxInEvent() = " << bxInEventData;
1014  m_myCoutStream << "\n";
1015  matchBxInEvent = true;
1016 
1017  } else {
1018  m_myCoutStream << "\n" << recString << " Data and emulated FDL bxInEvent different.";
1019  m_myCoutStream << "\n Data: bxInEvent() = " << bxInEventData;
1020  m_myCoutStream << "\n Emul: bxInEvent() = " << bxInEventEmul;
1021  m_myCoutStream << "\n";
1022 
1023  m_fdlDataEmul_Err[iRec]->Fill(1);
1024 
1025  if (iRec == 0) {
1026  m_agree = false;
1027 
1028  m_myCoutStream << "\nDisagreement data versus emulator: "
1029  << "\n Data and emulated FDL bxInEvent different \n";
1030  }
1031  }
1032 
1033  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1034  m_myCoutStream.str("");
1035  m_myCoutStream.clear();
1036 
1037  // symmetrize
1038  bool validBxInEvent = false;
1039  int histIndex = bxInEventData + (TotalBxInEvent + 1) / 2 - 1;
1040  LogDebug("L1GtHwValidation") << "\n Convert bxInEvent = " << bxInEventData << " to histIndex = " << histIndex
1041  << std::endl;
1042  if ((histIndex <= TotalBxInEvent) && (histIndex >= 0)) {
1043  validBxInEvent = true;
1044  }
1045 
1046  // loop over algorithms and increase the corresponding counters
1047 
1048  // get BoardId value
1049  const uint16_t boardIdData = fdlBlockData.boardId();
1050  const uint16_t boardIdEmul = fdlBlockEmul.boardId();
1051 
1052  if (boardIdData == boardIdEmul) {
1053  m_myCoutStream << "\n" << recString << " Data and emulated FDL boardId identical.";
1054  m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4) << std::setfill('0') << boardIdData
1055  << std::setfill(' ') << std::dec;
1056  m_myCoutStream << "\n";
1057 
1058  } else {
1059  m_myCoutStream << "\n" << recString << " Data and emulated FDL boardId different.";
1060  m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x" << std::setw(4) << std::setfill('0') << boardIdData
1061  << std::setfill(' ') << std::dec;
1062  m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x" << std::setw(4) << std::setfill('0') << boardIdEmul
1063  << std::setfill(' ') << std::dec;
1064  m_myCoutStream << "\n";
1065 
1066  if (matchBxInEvent && validBxInEvent) {
1067  m_fdlDataEmul[histIndex][iRec]->Fill(0);
1068  } else {
1069  m_fdlDataEmul_Err[iRec]->Fill(0);
1070  }
1071  }
1072 
1073  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1074  m_myCoutStream.str("");
1075  m_myCoutStream.clear();
1076 
1077  // get BxNr - bunch cross number of the actual bx
1078  const uint16_t bxNrData = fdlBlockData.bxNr();
1079  const uint16_t bxNrEmul = fdlBlockEmul.bxNr();
1080 
1081  if (bxNrData == bxNrEmul) {
1082  m_myCoutStream << "\n" << recString << " Data and emulated FDL bxNr identical.";
1083  m_myCoutStream << "\n bxNr() = " << bxNrData;
1084  m_myCoutStream << "\n";
1085 
1086  } else {
1087  m_myCoutStream << "\n" << recString << " Data and emulated FDL bxNr different.";
1088  m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
1089  m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
1090  m_myCoutStream << "\n";
1091 
1092  if (matchBxInEvent && validBxInEvent) {
1093  m_fdlDataEmul[histIndex][iRec]->Fill(2);
1094  } else {
1095  m_fdlDataEmul_Err[iRec]->Fill(2);
1096  }
1097  }
1098 
1099  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1100  m_myCoutStream.str("");
1101  m_myCoutStream.clear();
1102 
1103  // get event number since last L1 reset generated in FDL
1104  const uint32_t eventNrData = fdlBlockData.eventNr();
1105  const uint32_t eventNrEmul = fdlBlockEmul.eventNr();
1106 
1107  if (eventNrData == eventNrEmul) {
1108  m_myCoutStream << "\n" << recString << " Data and emulated FDL eventNr identical.";
1109  m_myCoutStream << "\n eventNr() = " << eventNrData;
1110  m_myCoutStream << "\n";
1111 
1112  } else {
1113  m_myCoutStream << "\n" << recString << " Data and emulated FDL eventNr different.";
1114  m_myCoutStream << "\n Data: eventNr() = " << eventNrData;
1115  m_myCoutStream << "\n Emul: eventNr() = " << eventNrEmul;
1116  m_myCoutStream << "\n";
1117 
1118  if (matchBxInEvent && validBxInEvent) {
1119  m_fdlDataEmul[histIndex][iRec]->Fill(3);
1120  } else {
1121  m_fdlDataEmul_Err[iRec]->Fill(3);
1122  }
1123  }
1124 
1125  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1126  m_myCoutStream.str("");
1127  m_myCoutStream.clear();
1128 
1129  // get technical trigger bits
1130  const TechnicalTriggerWord& gtTechnicalTriggerWordData = fdlBlockData.gtTechnicalTriggerWord();
1131  const TechnicalTriggerWord& gtTechnicalTriggerWordEmul = fdlBlockEmul.gtTechnicalTriggerWord();
1132 
1133  int nTechBits = gtTechnicalTriggerWordData.size();
1134 
1135  TechnicalTriggerWord gtTechnicalTriggerWordDataMask(nTechBits);
1136  TechnicalTriggerWord gtTechnicalTriggerWordEmulMask(nTechBits);
1137 
1138  unsigned int bitValue = 0;
1139 
1140  if (matchBxInEvent && validBxInEvent) {
1141  for (int iBit = 0; iBit < nTechBits; ++iBit) {
1142  unsigned int triggerMask = (m_triggerMaskTechTrig.at(iBit)) & (1 << PhysicsPartition);
1143 
1144  if (gtTechnicalTriggerWordData[iBit]) {
1145  m_fdlDataTechDecision[histIndex][iRec]->Fill(iBit);
1146 
1147  bitValue = (triggerMask) ? 0 : 1;
1148  gtTechnicalTriggerWordDataMask[iBit] = bitValue;
1149  if (bitValue) {
1150  m_fdlDataTechDecisionMask[histIndex][iRec]->Fill(iBit);
1151  }
1152  }
1153 
1154  if (gtTechnicalTriggerWordEmul.at(iBit)) {
1155  m_fdlEmulTechDecision[histIndex][iRec]->Fill(iBit);
1156 
1157  bitValue = (triggerMask) ? 0 : 1;
1158  gtTechnicalTriggerWordEmulMask[iBit] = bitValue;
1159  if (bitValue) {
1160  m_fdlEmulTechDecisionMask[histIndex][iRec]->Fill(iBit);
1161  }
1162  }
1163  }
1164  } else {
1165  for (int iBit = 0; iBit < nTechBits; ++iBit) {
1166  if (gtTechnicalTriggerWordData[iBit]) {
1167  m_fdlDataTechDecision_Err[iRec]->Fill(iBit);
1168  }
1169 
1170  if (gtTechnicalTriggerWordEmul.at(iBit)) {
1171  m_fdlEmulTechDecision_Err[iRec]->Fill(iBit);
1172  }
1173  }
1174  }
1175 
1176  if (gtTechnicalTriggerWordData == gtTechnicalTriggerWordEmul) {
1177  m_myCoutStream << "\n" << recString << " Data and emulated FDL gtTechnicalTriggerWord identical.\n";
1178  fdlBlockData.printGtTechnicalTriggerWord(m_myCoutStream);
1179  m_myCoutStream << "\n";
1180 
1181  } else {
1182  m_myCoutStream << "\n" << recString << " Data and emulated FDL gtTechnicalTriggerWord different.";
1183  m_myCoutStream << "\n Data: ";
1184  fdlBlockData.printGtTechnicalTriggerWord(m_myCoutStream);
1185  m_myCoutStream << "\n Emul: ";
1186  fdlBlockEmul.printGtTechnicalTriggerWord(m_myCoutStream);
1187  m_myCoutStream << "\n";
1188 
1189  if (matchBxInEvent && validBxInEvent) {
1190  m_fdlDataEmul[histIndex][iRec]->Fill(4);
1191  } else {
1192  m_fdlDataEmul_Err[iRec]->Fill(4);
1193  }
1194 
1195  if (matchBxInEvent && validBxInEvent) {
1196  for (int iBit = 0; iBit < nTechBits; ++iBit) {
1197  if (gtTechnicalTriggerWordData[iBit] != gtTechnicalTriggerWordEmul.at(iBit)) {
1198  m_fdlDataEmulTechDecision[histIndex][iRec]->Fill(iBit);
1199  }
1200  }
1201  } else {
1202  for (int iBit = 0; iBit < nTechBits; ++iBit) {
1203  if (gtTechnicalTriggerWordData[iBit] != gtTechnicalTriggerWordEmul.at(iBit)) {
1204  m_fdlDataEmulTechDecision_Err[iRec]->Fill(iBit);
1205  }
1206  }
1207  }
1208  }
1209 
1210  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1211  m_myCoutStream.str("");
1212  m_myCoutStream.clear();
1213 
1214  if (gtTechnicalTriggerWordDataMask == gtTechnicalTriggerWordEmulMask) {
1215  m_myCoutStream << "\n" << recString << " Data and emulated FDL gtTechnicalTriggerWord after mask identical.\n";
1216  m_myCoutStream << "\n";
1217 
1218  } else {
1219  m_myCoutStream << "\n" << recString << " Data and emulated FDL gtTechnicalTriggerWord after mask different.";
1220  m_myCoutStream << "\n Data: ";
1221  m_myCoutStream << "\n Emul: ";
1222  m_myCoutStream << "\n";
1223 
1224  if (matchBxInEvent && validBxInEvent) {
1225  m_fdlDataEmul[histIndex][iRec]->Fill(5);
1226  } else {
1227  m_fdlDataEmul_Err[iRec]->Fill(5);
1228  }
1229 
1230  if (matchBxInEvent && validBxInEvent) {
1231  for (int iBit = 0; iBit < nTechBits; ++iBit) {
1232  if (gtTechnicalTriggerWordData[iBit] != gtTechnicalTriggerWordEmul.at(iBit)) {
1233  m_fdlDataEmulTechDecisionMask[histIndex][iRec]->Fill(iBit);
1234  }
1235  }
1236  }
1237  }
1238 
1239  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1240  m_myCoutStream.str("");
1241  m_myCoutStream.clear();
1242 
1243  // get algorithms bits (decision word)
1244  const DecisionWord& gtDecisionWordData = fdlBlockData.gtDecisionWord();
1245  const DecisionWord& gtDecisionWordEmul = fdlBlockEmul.gtDecisionWord();
1246 
1247  int nAlgoBits = gtDecisionWordData.size();
1248 
1249  DecisionWord gtDecisionWordDataMask(nAlgoBits);
1250  DecisionWord gtDecisionWordEmulMask(nAlgoBits);
1251 
1252  // get the index of the prescale factor set from data
1253  int iPfSet = fdlBlockData.gtPrescaleFactorIndexAlgo();
1254 
1255  // check that the prescale factor is not out of range for the prescale factor
1256  // record retrieved from event setup
1257  size_t pfSetsSize = (*m_prescaleFactorsAlgoTrig).size();
1258 
1259  if (iPfSet < 0) {
1260  LogDebug("L1GtHwValidation") << "\nError: index of prescale factor set retrieved from the data \n"
1261  << "less than zero."
1262  << "\n Value of index retrieved from data = " << iPfSet << std::endl;
1263 
1264  // FIXME add a histogram to be used for a quality test
1265 
1266  return;
1267 
1268  } else if (iPfSet >= (static_cast<int>(pfSetsSize))) {
1269  LogDebug("L1GtHwValidation") << "\nError: index of prescale factor set retrieved from the data \n"
1270  << "greater than the size of the vector of prescale factor sets."
1271  << "\n Value of index retrieved from data = " << iPfSet
1272  << "\n Vector size = " << pfSetsSize << std::endl;
1273 
1274  // FIXME add a histogram to be used for a quality test
1275 
1276  return;
1277  }
1278 
1279  const std::vector<int>& prescaleFactorsAlgoTrig = (*m_prescaleFactorsAlgoTrig).at(iPfSet);
1280 
1281  if (matchBxInEvent && validBxInEvent) {
1282  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1283  unsigned int triggerMask = (m_triggerMaskAlgoTrig.at(iBit)) & (1 << PhysicsPartition);
1284 
1285  int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
1286 
1287  LogTrace("L1GtHwValidation") << "Bit " << iBit << ": prescale factor = " << prescaleFactor
1288  << " trigger mask = " << triggerMask << std::endl;
1289 
1290  if (gtDecisionWordData[iBit]) {
1291  m_fdlDataAlgoDecision[histIndex][iRec]->Fill(iBit);
1292 
1293  if (prescaleFactor == 1) {
1294  m_fdlDataAlgoDecisionUnprescaled[histIndex][iRec]->Fill(iBit);
1295  } else {
1296  m_fdlDataAlgoDecisionPrescaled[histIndex][iRec]->Fill(iBit);
1297  }
1298 
1299  bitValue = (triggerMask) ? 0 : 1;
1300  gtDecisionWordDataMask[iBit] = bitValue;
1301  if (bitValue) {
1302  m_fdlDataAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
1303  }
1304  }
1305 
1306  if (gtDecisionWordEmul.at(iBit)) {
1307  m_fdlEmulAlgoDecision[histIndex][iRec]->Fill(iBit);
1308 
1309  bitValue = (triggerMask) ? 0 : 1;
1310  gtDecisionWordEmulMask[iBit] = bitValue;
1311  if (bitValue) {
1312  m_fdlEmulAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
1313  }
1314  }
1315  }
1316  } else {
1317  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1318  if (gtDecisionWordData[iBit]) {
1319  m_fdlDataAlgoDecision_Err[iRec]->Fill(iBit);
1320  }
1321  }
1322 
1323  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1324  if (gtDecisionWordEmul.at(iBit)) {
1325  m_fdlEmulAlgoDecision_Err[iRec]->Fill(iBit);
1326  }
1327  }
1328 
1329  if (iRec == 0) {
1330  m_agree = false;
1331 
1332  m_myCoutStream << "\nDisagreement data versus emulator: "
1333  << "\n matchBxInEvent && validBxInEvent false \n";
1334  }
1335  }
1336 
1337  if (gtDecisionWordData == gtDecisionWordEmul) {
1338  m_myCoutStream << "\n" << recString << " Data and emulated FDL gtDecisionWord identical.";
1339  fdlBlockData.printGtDecisionWord(m_myCoutStream);
1340  m_myCoutStream << "\n";
1341 
1342  } else {
1343  m_myCoutStream << "\n" << recString << " Data and emulated FDL gtDecisionWord different.";
1344  m_myCoutStream << "\n Data: ";
1345  fdlBlockData.printGtDecisionWord(m_myCoutStream);
1346  m_myCoutStream << "\n Emul: ";
1347  fdlBlockEmul.printGtDecisionWord(m_myCoutStream);
1348  m_myCoutStream << "\n";
1349 
1350  if (matchBxInEvent && validBxInEvent) {
1351  m_fdlDataEmul[histIndex][iRec]->Fill(6);
1352  } else {
1353  m_fdlDataEmul_Err[iRec]->Fill(6);
1354  }
1355 
1356  if (matchBxInEvent && validBxInEvent) {
1357  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1358  int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
1359 
1360  if (gtDecisionWordData[iBit] != gtDecisionWordEmul.at(iBit)) {
1361  m_fdlDataEmulAlgoDecision[histIndex][iRec]->Fill(iBit);
1362 
1363  // for excluded algorithms, fill mismatch for BxInEvent = 0 and DAQ record only
1364  if (excludedAlgo(iBit) && (bxInEventData == 0) && (iRec == 0)) {
1365  m_excludedAlgorithmsAgreement->Fill(iBit);
1366  }
1367 
1368  if (prescaleFactor == 1) {
1369  m_fdlDataEmulAlgoDecisionUnprescaled[histIndex][iRec]->Fill(iBit);
1370 
1371  // fill a histogram for allowed algorithm triggers only
1372  if (!excludedAlgo(iBit)) {
1373  m_fdlDataEmulAlgoDecisionUnprescaledAllowed[histIndex][iRec]->Fill(iBit);
1374  }
1375 
1376  } else {
1377  m_fdlDataEmulAlgoDecisionPrescaled[histIndex][iRec]->Fill(iBit);
1378  }
1379 
1380  if (gtDecisionWordData[iBit]) {
1381  m_fdlDataAlgoDecision_NoMatch[histIndex][iRec]->Fill(iBit);
1382 
1383  if (prescaleFactor == 1) {
1384  m_fdlDataAlgoDecisionUnprescaled_NoMatch[histIndex][iRec]->Fill(iBit);
1385 
1386  // compare for agreement only unprescaled algorithms and algorithms which
1387  // are not excluded from comparison
1388  if ((!excludedAlgo(iBit)) && (bxInEventData == 0) && (iRec == 0)) {
1389  m_agree = false;
1390  m_dataOnly = true;
1391 
1392  m_myCoutStream << "\nDisagreement data versus emulator: "
1393  << "result before mask for algorithm with bit number " << iBit
1394  << "\n Data: true, emulator: false \n";
1395  }
1396 
1397  } else {
1398  m_fdlDataAlgoDecisionPrescaled_NoMatch[histIndex][iRec]->Fill(iBit);
1399  }
1400 
1401  } else {
1402  m_fdlEmulAlgoDecision_NoMatch[histIndex][iRec]->Fill(iBit);
1403 
1404  if (prescaleFactor == 1) {
1405  m_fdlEmulAlgoDecisionUnprescaled_NoMatch[histIndex][iRec]->Fill(iBit);
1406 
1407  // compare for agreement only unprescaled algorithms and algorithms which
1408  // are not excluded from comparison
1409  if ((!excludedAlgo(iBit)) && (bxInEventData == 0) && (iRec == 0)) {
1410  m_agree = false;
1411  m_emulOnly = true;
1412 
1413  m_myCoutStream << "\nDisagreement data versus emulator: "
1414  << "result before mask for algorithm with bit number " << iBit
1415  << "\n Data: false, emulator: true \n";
1416  }
1417 
1418  } else {
1419  m_fdlEmulAlgoDecisionPrescaled_NoMatch[histIndex][iRec]->Fill(iBit);
1420  }
1421  }
1422  }
1423  }
1424  } else {
1425  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1426  if (gtDecisionWordData[iBit] != gtDecisionWordEmul.at(iBit)) {
1427  m_fdlDataEmulAlgoDecision_Err[iRec]->Fill(iBit);
1428  }
1429  }
1430 
1431  if (iRec == 0) {
1432  m_agree = false;
1433 
1434  m_myCoutStream << "\nDisagreement data versus emulator: "
1435  << "\n matchBxInEvent && validBxInEvent false \n";
1436  }
1437  }
1438  }
1439 
1440  if (gtDecisionWordDataMask == gtDecisionWordEmulMask) {
1441  m_myCoutStream << "\n" << recString << " Data and emulated FDL gtDecisionWord after mask identical.";
1442  m_myCoutStream << "\n";
1443 
1444  } else {
1445  m_myCoutStream << "\n" << recString << " Data and emulated FDL gtDecisionWord after mask different.";
1446  m_myCoutStream << "\n Data: ";
1447  m_myCoutStream << "\n Emul: ";
1448  m_myCoutStream << "\n";
1449 
1450  if (matchBxInEvent && validBxInEvent) {
1451  m_fdlDataEmul[histIndex][iRec]->Fill(7);
1452  } else {
1453  m_fdlDataEmul_Err[iRec]->Fill(7);
1454  }
1455 
1456  if (matchBxInEvent && validBxInEvent) {
1457  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1458  if (gtDecisionWordDataMask[iBit] != gtDecisionWordEmulMask.at(iBit)) {
1459  m_fdlDataEmulAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
1460 
1461  int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
1462 
1463  if (gtDecisionWordDataMask[iBit]) {
1464  m_fdlDataAlgoDecisionMask_NoMatch[histIndex][iRec]->Fill(iBit);
1465 
1466  if (prescaleFactor == 1) {
1467  m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[histIndex][iRec]->Fill(iBit);
1468 
1469  // compare for agreement only unprescaled algorithms and algorithms which
1470  // are not excluded from comparison
1471  if ((!excludedAlgo(iBit)) && (bxInEventData == 0) && (iRec == 0)) {
1472  m_agree = false;
1473  m_dataOnlyMask = true;
1474 
1475  m_myCoutStream << "\nDisagreement data versus emulator: "
1476  << "result after mask for algorithm with bit number " << iBit
1477  << " different in data versus emulator "
1478  << "\n Data: true, emulator: false \n";
1479  }
1480 
1481  } else {
1482  m_fdlDataAlgoDecisionPrescaledMask_NoMatch[histIndex][iRec]->Fill(iBit);
1483  }
1484 
1485  } else {
1486  m_fdlEmulAlgoDecisionMask_NoMatch[histIndex][iRec]->Fill(iBit);
1487 
1488  if (prescaleFactor == 1) {
1489  m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[histIndex][iRec]->Fill(iBit);
1490 
1491  // compare for agreement only unprescaled algorithms and algorithms which
1492  // are not excluded from comparison
1493  if ((!excludedAlgo(iBit)) && (bxInEventData == 0) && (iRec == 0)) {
1494  m_agree = false;
1495  m_emulOnlyMask = true;
1496 
1497  m_myCoutStream << "\nDisagreement data versus emulator: "
1498  << "result after mask for algorithm with bit number " << iBit
1499  << " different in data versus emulator "
1500  << "\n Data: false, emulator: true \n";
1501  }
1502 
1503  } else {
1504  m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[histIndex][iRec]->Fill(iBit);
1505  }
1506  }
1507  }
1508  }
1509  }
1510  }
1511 
1512  // get extended algorithms bits (extended decision word)
1513  const DecisionWordExtended& gtDecisionWordExtendedData = fdlBlockData.gtDecisionWordExtended();
1514  const DecisionWordExtended& gtDecisionWordExtendedEmul = fdlBlockEmul.gtDecisionWordExtended();
1515 
1516  if (gtDecisionWordExtendedData == gtDecisionWordExtendedEmul) {
1517  m_myCoutStream << "\n" << recString << " Data and emulated FDL gtDecisionWordExtended identical.\n";
1518  fdlBlockData.printGtDecisionWordExtended(m_myCoutStream);
1519  m_myCoutStream << "\n";
1520 
1521  } else {
1522  m_myCoutStream << "\n" << recString << " Data and emulated FDL gtDecisionWordExtended different.\n";
1523  m_myCoutStream << "\n Data: ";
1524  fdlBlockData.printGtDecisionWordExtended(m_myCoutStream);
1525  m_myCoutStream << "\n Emul: ";
1526  fdlBlockEmul.printGtDecisionWordExtended(m_myCoutStream);
1527  m_myCoutStream << "\n";
1528 
1529  if (matchBxInEvent && validBxInEvent) {
1530  m_fdlDataEmul[histIndex][iRec]->Fill(8);
1531  } else {
1532  m_fdlDataEmul_Err[iRec]->Fill(8);
1533  }
1534  }
1535 
1536  // get NoAlgo
1537  const uint16_t noAlgoData = fdlBlockData.noAlgo();
1538  const uint16_t noAlgoEmul = fdlBlockEmul.noAlgo();
1539 
1540  if (noAlgoData == noAlgoEmul) {
1541  m_myCoutStream << "\n" << recString << " Data and emulated FDL noAlgo identical.";
1542  m_myCoutStream << "\n noAlgo() = " << noAlgoData;
1543  m_myCoutStream << "\n";
1544 
1545  } else {
1546  m_myCoutStream << "\n" << recString << " Data and emulated FDL noAlgo different.";
1547  m_myCoutStream << "\n Data: noAlgo() = " << noAlgoData;
1548  m_myCoutStream << "\n Emul: noAlgo() = " << noAlgoEmul;
1549  m_myCoutStream << "\n";
1550 
1551  if (matchBxInEvent && validBxInEvent) {
1552  m_fdlDataEmul[histIndex][iRec]->Fill(9);
1553  } else {
1554  m_fdlDataEmul_Err[iRec]->Fill(9);
1555  }
1556  }
1557 
1558  // get "Final OR" bits
1559  const uint16_t finalORData = fdlBlockData.finalOR();
1560  const uint16_t finalOREmul = fdlBlockEmul.finalOR();
1561 
1562  if (finalORData == finalOREmul) {
1563  m_myCoutStream << "\n" << recString << " Data and emulated FDL finalOR identical.";
1564  m_myCoutStream << "\n finalOR() = " << std::hex << "0x" << std::setw(2) << std::setfill('0') << finalORData
1565  << std::setfill(' ') << std::dec;
1566  m_myCoutStream << "\n";
1567 
1568  } else {
1569  m_myCoutStream << "\n" << recString << " Data and emulated FDL finalOR different.";
1570  m_myCoutStream << "\n Data: finalOR() = " << std::hex << "0x" << std::setw(2) << std::setfill('0') << finalORData
1571  << std::setfill(' ') << std::dec;
1572  m_myCoutStream << "\n Emul: finalOR() = " << std::hex << "0x" << std::setw(2) << std::setfill('0') << finalOREmul
1573  << std::setfill(' ') << std::dec;
1574  m_myCoutStream << "\n";
1575 
1576  if (matchBxInEvent && validBxInEvent) {
1577  m_fdlDataEmul[histIndex][iRec]->Fill(10);
1578  } else {
1579  m_fdlDataEmul_Err[iRec]->Fill(10);
1580  }
1581  }
1582 
1583  // get "Final OR" for physics partition
1584  const int finalORPhysData = finalORData & (1 << PhysicsPartition);
1585  const int finalORPhysEmul = finalOREmul & (1 << PhysicsPartition);
1586 
1587  if (finalORPhysData == finalORPhysEmul) {
1588  m_myCoutStream << "\n" << recString << " Data and emulated FDL finalOR for the physics partition identical.";
1589  m_myCoutStream << "\n finalOR() = " << finalORPhysData;
1590  m_myCoutStream << "\n";
1591 
1592  } else {
1593  m_myCoutStream << "\n" << recString << " Data and emulated FDL finalOR for the physics partition different.";
1594  m_myCoutStream << "\n Data: finalOR() = " << finalORPhysData;
1595  m_myCoutStream << "\n Emul: finalOR() = " << finalORPhysEmul;
1596  m_myCoutStream << "\n";
1597 
1598  if (matchBxInEvent && validBxInEvent) {
1599  m_fdlDataEmul[histIndex][iRec]->Fill(11);
1600  } else {
1601  m_fdlDataEmul_Err[iRec]->Fill(11);
1602  }
1603  }
1604 
1605  // get local bunch cross number of the actual bx
1606  const uint16_t localBxNrData = fdlBlockData.localBxNr();
1607  const uint16_t localBxNrEmul = fdlBlockEmul.localBxNr();
1608 
1609  if (localBxNrData == localBxNrEmul) {
1610  m_myCoutStream << "\n" << recString << " Data and emulated FDL localBxNr identical.";
1611  m_myCoutStream << "\n localBxNr() = " << localBxNrData;
1612  m_myCoutStream << "\n";
1613 
1614  } else {
1615  m_myCoutStream << "\n" << recString << " Data and emulated FDL localBxNr different.";
1616  m_myCoutStream << "\n Data: localBxNr() = " << localBxNrData;
1617  m_myCoutStream << "\n Emul: localBxNr() = " << localBxNrEmul;
1618  m_myCoutStream << "\n";
1619 
1620  if (matchBxInEvent && validBxInEvent) {
1621  m_fdlDataEmul[histIndex][iRec]->Fill(12);
1622  } else {
1623  m_fdlDataEmul_Err[iRec]->Fill(12);
1624  }
1625  }
1626 
1627  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1628  m_myCoutStream.str("");
1629  m_myCoutStream.clear();
1630 }
1631 
1632 //compare the PSB board
1633 void L1GtHwValidation::comparePSB(const edm::Event& iEvent,
1634  const edm::EventSetup& evSetup,
1635  const L1GtPsbWord& psbBlockData,
1636  const L1GtPsbWord& psbBlockEmul) {
1637  if (psbBlockData == psbBlockEmul) {
1638  m_myCoutStream << "\nData and emulated PSB blocks: identical.\n";
1639  psbBlockData.print(m_myCoutStream);
1640 
1641  } else {
1642  m_myCoutStream << "\nData and emulated PSB blocks: different.\n";
1643 
1644  m_myCoutStream << "\nData: PSB block\n";
1645  psbBlockData.print(m_myCoutStream);
1646 
1647  m_myCoutStream << "\nEmul: PSB block\n";
1648  psbBlockEmul.print(m_myCoutStream);
1649  }
1650 
1651  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1652 
1653  m_myCoutStream.str("");
1654  m_myCoutStream.clear();
1655 
1656  // get BoardId value
1657  const uint16_t boardIdData = psbBlockData.boardId();
1658  const uint16_t boardIdEmul = psbBlockEmul.boardId();
1659 
1660  if (boardIdData == boardIdEmul) {
1661  m_myCoutStream << "\nData and emulated PSB boardId identical.";
1662  m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4) << std::setfill('0') << boardIdData
1663  << std::setfill(' ') << std::dec;
1664  m_myCoutStream << "\n";
1665 
1666  } else {
1667  m_myCoutStream << "\nData and emulated PSB boardId different.";
1668  m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x" << std::setw(4) << std::setfill('0') << boardIdData
1669  << std::setfill(' ') << std::dec;
1670  m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x" << std::setw(4) << std::setfill('0') << boardIdEmul
1671  << std::setfill(' ') << std::dec;
1672  m_myCoutStream << "\n";
1673  }
1674 
1675  // get bunch cross in the GT event record
1676  const int bxInEventData = psbBlockData.bxInEvent();
1677  const int bxInEventEmul = psbBlockEmul.bxInEvent();
1678 
1679  if (bxInEventData == bxInEventEmul) {
1680  m_myCoutStream << "\nData and emulated PSB bxInEvent identical.";
1681  m_myCoutStream << "\n bxInEvent() = " << bxInEventData;
1682  m_myCoutStream << "\n";
1683 
1684  } else {
1685  m_myCoutStream << "\nData and emulated PSB bxInEvent different.";
1686  m_myCoutStream << "\n Data: bxInEvent() = " << bxInEventData;
1687  m_myCoutStream << "\n Emul: bxInEvent() = " << bxInEventEmul;
1688  m_myCoutStream << "\n";
1689  }
1690 
1691  // get BxNr - bunch cross number of the actual bx
1692  const uint16_t bxNrData = psbBlockData.bxNr();
1693  const uint16_t bxNrEmul = psbBlockEmul.bxNr();
1694 
1695  if (bxNrData == bxNrEmul) {
1696  m_myCoutStream << "\nData and emulated PSB bxNr identical.";
1697  m_myCoutStream << "\n bxNr() = " << bxNrData;
1698  m_myCoutStream << "\n";
1699 
1700  } else {
1701  m_myCoutStream << "\nData and emulated PSB bxNr different.";
1702  m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
1703  m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
1704  m_myCoutStream << "\n";
1705  }
1706 
1707  // get event number since last L1 reset generated in FDL
1708  const uint32_t eventNrData = psbBlockData.eventNr();
1709  const uint32_t eventNrEmul = psbBlockEmul.eventNr();
1710 
1711  if (eventNrData == eventNrEmul) {
1712  m_myCoutStream << "\nData and emulated PSB eventNr identical.";
1713  m_myCoutStream << "\n eventNr() = " << eventNrData;
1714  m_myCoutStream << "\n";
1715 
1716  } else {
1717  m_myCoutStream << "\nData and emulated PSB eventNr different.";
1718  m_myCoutStream << "\n Data: eventNr() = " << eventNrData;
1719  m_myCoutStream << "\n Emul: eventNr() = " << eventNrEmul;
1720  m_myCoutStream << "\n";
1721  }
1722 
1724  uint16_t valData;
1725  uint16_t valEmul;
1726 
1727  for (int iA = 0; iA < psbBlockData.NumberAData; ++iA) {
1728  valData = psbBlockData.aData(iA);
1729  valEmul = psbBlockEmul.aData(iA);
1730 
1731  if (valData == valEmul) {
1732  m_myCoutStream << "\nData and emulated PSB aData(" << iA << ") identical.";
1733  m_myCoutStream << "\n aData(iA) = " << std::hex << "0x" << std::setw(4) << std::setfill('0') << valData
1734  << std::setfill(' ') << std::dec;
1735  m_myCoutStream << "\n";
1736 
1737  } else {
1738  m_myCoutStream << "\nData and emulated PSB aData(" << iA << ") different.";
1739  m_myCoutStream << "\n Data: aData(iA) = " << std::hex << "0x" << std::setw(4) << std::setfill('0') << valData
1740  << std::setfill(' ') << std::dec;
1741  m_myCoutStream << "\n Emul: aData(iA) = " << std::hex << "0x" << std::setw(4) << std::setfill('0') << valEmul
1742  << std::setfill(' ') << std::dec;
1743  m_myCoutStream << "\n";
1744  }
1745  }
1746 
1748  for (int iB = 0; iB < psbBlockData.NumberBData; ++iB) {
1749  valData = psbBlockData.bData(iB);
1750  valEmul = psbBlockEmul.bData(iB);
1751 
1752  if (valData == valEmul) {
1753  m_myCoutStream << "\nData and emulated PSB bData(" << iB << ") identical.";
1754  m_myCoutStream << "\n bData(iA) = " << std::hex << "0x" << std::setw(4) << std::setfill('0') << valData
1755  << std::setfill(' ') << std::dec;
1756  m_myCoutStream << "\n";
1757 
1758  } else {
1759  m_myCoutStream << "\nData and emulated PSB bData(" << iB << ") different.";
1760  m_myCoutStream << "\n Data: bData(iA) = " << std::hex << "0x" << std::setw(4) << std::setfill('0') << valData
1761  << std::setfill(' ') << std::dec;
1762  m_myCoutStream << "\n Emul: bData(iA) = " << std::hex << "0x" << std::setw(4) << std::setfill('0') << valEmul
1763  << std::setfill(' ') << std::dec;
1764  m_myCoutStream << "\n";
1765  }
1766  }
1767 
1768  // get local bunch cross number of the actual bx
1769  const uint16_t localBxNrData = psbBlockData.localBxNr();
1770  const uint16_t localBxNrEmul = psbBlockEmul.localBxNr();
1771 
1772  if (localBxNrData == localBxNrEmul) {
1773  m_myCoutStream << "\nData and emulated PSB localBxNr identical.";
1774  m_myCoutStream << "\n localBxNr() = " << localBxNrData;
1775  m_myCoutStream << "\n";
1776 
1777  } else {
1778  m_myCoutStream << "\nData and emulated PSB localBxNr different.";
1779  m_myCoutStream << "\n Data: localBxNr() = " << localBxNrData;
1780  m_myCoutStream << "\n Emul: localBxNr() = " << localBxNrEmul;
1781  m_myCoutStream << "\n";
1782  }
1783 
1784  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1785  m_myCoutStream.str("");
1786  m_myCoutStream.clear();
1787 }
1788 
1789 //compare the TCS board
1790 void L1GtHwValidation::compareTCS(const edm::Event& iEvent,
1791  const edm::EventSetup& evSetup,
1792  const L1TcsWord&,
1793  const L1TcsWord&) {
1794  // empty
1795 }
1796 
1797 //L1 GT DAQ record comparison
1798 void L1GtHwValidation::compareDaqRecord(const edm::Event& iEvent, const edm::EventSetup& evSetup) {
1799  // formal index for DAQ record
1800  int iRec = 0;
1801 
1802  // reset the flags - they are used for DAQ recor only
1803  m_agree = true;
1804  m_dataOnly = false;
1805  m_emulOnly = false;
1806  m_dataOnlyMask = false;
1807  m_emulOnlyMask = false;
1808 
1809  // get the L1 GT hardware DAQ record L1GlobalTriggerReadoutRecord
1810  edm::Handle<L1GlobalTriggerReadoutRecord> gtReadoutRecordData;
1811  iEvent.getByToken(m_l1GtDataDaqInputToken_, gtReadoutRecordData);
1812 
1813  bool validData = false;
1814 
1815  if (!gtReadoutRecordData.isValid()) {
1816  m_nrDataEventError++;
1817  } else {
1818  validData = true;
1819  }
1820 
1821  // get the L1 GT emulator DAQ record L1GlobalTriggerReadoutRecord
1822  edm::Handle<L1GlobalTriggerReadoutRecord> gtReadoutRecordEmul;
1823  iEvent.getByToken(m_l1GtEmulDaqInputToken_, gtReadoutRecordEmul);
1824 
1825  bool validEmul = false;
1826 
1827  if (!gtReadoutRecordEmul.isValid()) {
1828  m_nrEmulEventError++;
1829  } else {
1830  validEmul = true;
1831  }
1832 
1833  if ((!validData) || (!validEmul)) {
1834  edm::LogWarning("L1GtHwValidation") << "\n No valid product found: DAQ L1GlobalTriggerReadoutRecord"
1835  << "\n Data validity [1 = true; 0 = false]: " << validData
1836  << "\n Emulator validity: [1 = true; 0 = false]: " << validEmul
1837  << "\n DAQ histograms will not be filled.\n"
1838  << std::endl;
1839 
1840  return;
1841  }
1842 
1843  // compare GTFE
1844  const L1GtfeWord& gtfeBlockData = gtReadoutRecordData->gtfeWord();
1845  const L1GtfeWord& gtfeBlockEmul = gtReadoutRecordEmul->gtfeWord();
1846 
1847  compareGTFE(iEvent, evSetup, gtfeBlockData, gtfeBlockEmul, iRec);
1848 
1849  // FDL comparison
1850  const std::vector<L1GtFdlWord>& gtFdlVectorData = gtReadoutRecordData->gtFdlVector();
1851  const std::vector<L1GtFdlWord>& gtFdlVectorEmul = gtReadoutRecordEmul->gtFdlVector();
1852 
1853  int gtFdlVectorDataSize = gtFdlVectorData.size();
1854  int gtFdlVectorEmulSize = gtFdlVectorEmul.size();
1855 
1856  if (gtFdlVectorDataSize == gtFdlVectorEmulSize) {
1857  m_myCoutStream << "\nData and emulated FDL vector size: identical.\n";
1858  m_myCoutStream << " Size: " << gtFdlVectorDataSize << std::endl;
1859 
1860  for (int iFdl = 0; iFdl < gtFdlVectorDataSize; ++iFdl) {
1861  const L1GtFdlWord& fdlBlockData = gtFdlVectorData[iFdl];
1862  const L1GtFdlWord& fdlBlockEmul = gtFdlVectorEmul[iFdl];
1863 
1864  compareFDL(iEvent, evSetup, fdlBlockData, fdlBlockEmul, iRec);
1865  }
1866  } else {
1867  m_myCoutStream << "\nData and emulated FDL vector size: different.\n";
1868  m_myCoutStream << " Data: size = " << gtFdlVectorDataSize << std::endl;
1869  m_myCoutStream << " Emul: size = " << gtFdlVectorEmulSize << std::endl;
1870  }
1871 
1872  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1873 
1874  m_myCoutStream.str("");
1875  m_myCoutStream.clear();
1876 
1877  // PSB comparison
1878  const std::vector<L1GtPsbWord>& gtPsbVectorData = gtReadoutRecordData->gtPsbVector();
1879  const std::vector<L1GtPsbWord>& gtPsbVectorEmul = gtReadoutRecordEmul->gtPsbVector();
1880 
1881  int gtPsbVectorDataSize = gtPsbVectorData.size();
1882  int gtPsbVectorEmulSize = gtPsbVectorEmul.size();
1883 
1884  if (gtPsbVectorDataSize == gtPsbVectorEmulSize) {
1885  m_myCoutStream << "\nData and emulated PSB vector size: identical.\n";
1886  m_myCoutStream << " Size: " << gtPsbVectorDataSize << std::endl;
1887  } else {
1888  m_myCoutStream << "\nData and emulated PSB vector size: different.\n";
1889  m_myCoutStream << " Data: size = " << gtPsbVectorDataSize << std::endl;
1890  m_myCoutStream << " Emul: size = " << gtPsbVectorEmulSize << std::endl;
1891  }
1892 
1893  // the order of PSB block in the gtPsbVector is different in emulator and in data
1894  // in emulator: all active PSB in one BxInEvent, ordered L1A-1, L1A, L1A+1
1895  // in unpacker: every PSB in all BxInEvent
1896  for (int iPsb = 0; iPsb < gtPsbVectorDataSize; ++iPsb) {
1897  const L1GtPsbWord& psbBlockData = gtPsbVectorData[iPsb];
1898  const uint16_t boardIdData = psbBlockData.boardId();
1899  const int bxInEventData = psbBlockData.bxInEvent();
1900 
1901  // search the corresponding PSB in the emulated record using the
1902  // BoardId and the BxInEvent
1903 
1904  bool foundPSB = false;
1905 
1906  for (int iPsbF = 0; iPsbF < gtPsbVectorEmulSize; ++iPsbF) {
1907  const L1GtPsbWord& psbBlockEmul = gtPsbVectorEmul[iPsbF];
1908  const uint16_t boardIdEmul = psbBlockEmul.boardId();
1909  const int bxInEventEmul = psbBlockEmul.bxInEvent();
1910 
1911  if ((boardIdEmul == boardIdData) && (bxInEventData == bxInEventEmul)) {
1912  foundPSB = true;
1913 
1914  // compare the boards
1915  comparePSB(iEvent, evSetup, psbBlockData, psbBlockEmul);
1916  }
1917  }
1918 
1919  if (!foundPSB) {
1920  m_myCoutStream << "\nNo emulated PSB with boardId() = " << std::hex << "0x" << std::setw(4) << std::setfill('0')
1921  << boardIdData << std::setfill(' ') << std::dec << " and BxInEvent = " << bxInEventData
1922  << " was found";
1923  }
1924  }
1925 
1926  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1927 
1928  m_myCoutStream.str("");
1929  m_myCoutStream.clear();
1930 
1931  // fill the m_gtErrorFlag histogram (only for L1 GT DAQ record)
1932 
1933  if (m_agree) {
1934  m_gtErrorFlag->Fill(0.0001);
1935  }
1936 
1937  if (m_dataOnly || m_dataOnlyMask) {
1938  m_gtErrorFlag->Fill(3.0001);
1939  }
1940 
1941  if (m_emulOnly || m_emulOnlyMask) {
1942  m_gtErrorFlag->Fill(4.0001);
1943  }
1944 }
1945 
1946 // L1 GT EVM record comparison
1947 void L1GtHwValidation::compareEvmRecord(const edm::Event& iEvent, const edm::EventSetup& evSetup) {
1948  // formal index for EVM record
1949  int iRec = 1;
1950 
1951  // get the L1 GT hardware EVM record L1GlobalTriggerEvmReadoutRecord
1952  edm::Handle<L1GlobalTriggerEvmReadoutRecord> gtReadoutRecordData;
1953  iEvent.getByToken(m_l1GtDataEvmInputToken_, gtReadoutRecordData);
1954 
1955  bool validData = false;
1956 
1957  if (!gtReadoutRecordData.isValid()) {
1958  m_nrDataEventError++;
1959  } else {
1960  validData = true;
1961  }
1962 
1963  // get the L1 GT emulator EVM record L1GlobalTriggerEvmReadoutRecord
1964  edm::Handle<L1GlobalTriggerEvmReadoutRecord> gtReadoutRecordEmul;
1965  iEvent.getByToken(m_l1GtEmulEvmInputToken_, gtReadoutRecordEmul);
1966 
1967  bool validEmul = false;
1968 
1969  if (!gtReadoutRecordEmul.isValid()) {
1970  m_nrEmulEventError++;
1971  } else {
1972  validEmul = true;
1973  }
1974 
1975  if ((!validData) || (!validEmul)) {
1976  edm::LogWarning("L1GtHwValidation") << "\n No valid product found: EVM L1GlobalTriggerEvmReadoutRecord"
1977  << "\n Data validity [1 = true; 0 = false]: " << validData
1978  << "\n Emulator validity: [1 = true; 0 = false]: " << validEmul
1979  << "\n EVM histograms will not be filled.\n"
1980  << std::endl;
1981 
1982  return;
1983  }
1984 
1985  // compare GTFE
1986  const L1GtfeWord& gtfeBlockData = gtReadoutRecordData->gtfeWord();
1987  const L1GtfeWord& gtfeBlockEmul = gtReadoutRecordEmul->gtfeWord();
1988 
1989  compareGTFE(iEvent, evSetup, gtfeBlockData, gtfeBlockEmul, iRec);
1990 
1991  // FDL comparison
1992  const std::vector<L1GtFdlWord>& gtFdlVectorData = gtReadoutRecordData->gtFdlVector();
1993  const std::vector<L1GtFdlWord>& gtFdlVectorEmul = gtReadoutRecordEmul->gtFdlVector();
1994 
1995  int gtFdlVectorDataSize = gtFdlVectorData.size();
1996  int gtFdlVectorEmulSize = gtFdlVectorEmul.size();
1997 
1998  if (gtFdlVectorDataSize == gtFdlVectorEmulSize) {
1999  m_myCoutStream << "\nData and emulated FDL vector size: identical.\n";
2000  m_myCoutStream << " Size: " << gtFdlVectorDataSize << std::endl;
2001 
2002  for (int iFdl = 0; iFdl < gtFdlVectorDataSize; ++iFdl) {
2003  const L1GtFdlWord& fdlBlockData = gtFdlVectorData[iFdl];
2004  const L1GtFdlWord& fdlBlockEmul = gtFdlVectorEmul[iFdl];
2005 
2006  compareFDL(iEvent, evSetup, fdlBlockData, fdlBlockEmul, iRec);
2007  }
2008  } else {
2009  m_myCoutStream << "\nData and emulated FDL vector size: different.\n";
2010  m_myCoutStream << " Data: size = " << gtFdlVectorDataSize << std::endl;
2011  m_myCoutStream << " Emul: size = " << gtFdlVectorEmulSize << std::endl;
2012  }
2013 
2014  // FIXME compare TCS
2015 
2016  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
2017 
2018  m_myCoutStream.str("");
2019  m_myCoutStream.clear();
2020 
2021  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
2022 
2023  m_myCoutStream.str("");
2024  m_myCoutStream.clear();
2025 }
2026 
2027 // compare the GCT collections obtained from L1 GT PSB with the input
2028 // GCT collections
2029 void L1GtHwValidation::compareGt_Gct(const edm::Event& iEvent, const edm::EventSetup&) {
2030  // FIXME
2031 }
2032 
2033 // analyze each event: event loop
2034 void L1GtHwValidation::analyze(const edm::Event& iEvent, const edm::EventSetup& evSetup) {
2035  ++m_nrEvJob;
2036  ++m_nrEvRun;
2037 
2038  // L1 GT DAQ record comparison
2039  compareDaqRecord(iEvent, evSetup);
2040 
2041  // L1 GT EVM record comparison
2042  compareEvmRecord(iEvent, evSetup);
2043 
2044  // GCT collections from L1 GT PSB versus unpacked GCT
2045  compareGt_Gct(iEvent, evSetup);
2046 }
2047 
2048 bool L1GtHwValidation::matchCondCategory(const L1GtConditionCategory& conditionCategory,
2049  const L1GtConditionCategory& excludedCategory) {
2050  bool matchValue = false;
2051 
2052  if (excludedCategory == CondNull) {
2053  matchValue = true;
2054  } else {
2055  if (conditionCategory == excludedCategory) {
2056  matchValue = true;
2057  }
2058  }
2059 
2060  return matchValue;
2061 }
2062 
2063 bool L1GtHwValidation::matchCondType(const L1GtConditionType& conditionType, const L1GtConditionType& excludedType) {
2064  bool matchValue = false;
2065 
2066  if (excludedType == TypeNull) {
2067  matchValue = true;
2068  } else {
2069  if (conditionType == excludedType) {
2070  matchValue = true;
2071  }
2072  }
2073 
2074  return matchValue;
2075 }
2076 
2077 bool L1GtHwValidation::matchCondL1GtObject(const std::vector<L1GtObject>& condObjects,
2078  const L1GtObject& excludedObject) {
2079  bool matchValue = false;
2080 
2081  if (excludedObject == ObjNull) {
2082  matchValue = true;
2083 
2084  } else {
2085  for (std::vector<L1GtObject>::const_iterator itCondObj = condObjects.begin(); itCondObj != condObjects.end();
2086  ++itCondObj) {
2087  if ((*itCondObj) == excludedObject) {
2088  matchValue = true;
2089  }
2090  }
2091  }
2092 
2093  return matchValue;
2094 }
2095 
2096 void L1GtHwValidation::excludedAlgoList() {
2097  const AlgorithmMap& algorithmMap = m_l1GtMenu->gtAlgorithmMap();
2098 
2099  for (CItAlgo itAlgo = algorithmMap.begin(); itAlgo != algorithmMap.end(); itAlgo++) {
2100  const std::string& algName = itAlgo->first;
2101  const int algBitNumber = (itAlgo->second).algoBitNumber();
2102  const int chipNr = (itAlgo->second).algoChipNumber();
2103 
2104  const ConditionMap& conditionMap = (m_l1GtMenu->gtConditionMap()).at(chipNr);
2105 
2106  const std::vector<L1GtLogicParser::TokenRPN>& aRpnVector = (itAlgo->second).algoRpnVector();
2107  size_t aRpnVectorSize = aRpnVector.size();
2108 
2109  bool algWithExcludedCondition = false;
2110  bool algWithConditionNotInMap = false;
2111 
2112  // loop over RpnVector and check each conditions against list of excluded conditions
2113  for (size_t opI = 0; opI < aRpnVectorSize; ++opI) {
2114  const std::string& cndName = (aRpnVector[opI]).operand;
2115 
2116  if (!cndName.empty()) {
2117  bool foundCond = false;
2118 
2119  CItCond itCond = conditionMap.find(cndName);
2120  if (itCond != conditionMap.end()) {
2121  const L1GtConditionCategory& cCateg = (itCond->second)->condCategory();
2122  const L1GtConditionType& cType = (itCond->second)->condType();
2123  const std::vector<L1GtObject>& objType = (itCond->second)->objectType();
2124 
2125  // condition index in the m_excludedCondCategory, m_excludedCondType, m_excludedL1GtObject vectors
2126  int iCond = -1;
2127 
2128  for (std::vector<L1GtConditionCategory>::const_iterator itCateg = m_excludedCondCategory.begin();
2129  itCateg != m_excludedCondCategory.end();
2130  ++itCateg) {
2131  iCond++;
2132 
2133  bool matchCondCategoryValue = matchCondCategory(cCateg, (*itCateg));
2134  bool matchCondTypeValue = matchCondType(cType, m_excludedCondType.at(iCond));
2135  bool matchCondL1GtObjectValue = matchCondL1GtObject(objType, m_excludedL1GtObject.at(iCond));
2136 
2137  LogTrace("L1GtHwValidation") << "\n "
2138  << "Algorithm: " << algName << " Condition: " << cndName << "\n "
2139  << "Category: " << l1GtConditionCategoryEnumToString(cCateg)
2140  << "; excluded: " << l1GtConditionCategoryEnumToString((*itCateg)) << "\n "
2141  << "Type: " << l1GtConditionTypeEnumToString(cType) << "; excluded: "
2142  << l1GtConditionTypeEnumToString(m_excludedCondType.at(iCond)) << "\n "
2143  << "Object excluded: "
2144  << l1GtObjectEnumToString(m_excludedL1GtObject.at(iCond)) << std::endl;
2145 
2146  if (matchCondCategoryValue && matchCondTypeValue && matchCondL1GtObjectValue) {
2147  algWithExcludedCondition = true;
2148  }
2149  }
2150 
2151  foundCond = true;
2152  }
2153 
2154  if (!foundCond) {
2155  // it should never be happen, all conditions are in the maps
2156 
2157  algWithConditionNotInMap = true;
2158 
2159  LogTrace("L1GtHwValidation") << "\n Error: condition " << cndName << " not found in condition map!"
2160  << "\n Add algorithm " << algName << " (bit number " << algBitNumber << ") "
2161  << "\n to list of algorithms excluded from comparison"
2162  << "\n data versus emulator." << std::endl;
2163  }
2164  }
2165  }
2166 
2167  if (algWithConditionNotInMap) {
2168  // it should never be happen, all conditions are in the maps
2169 
2170  m_excludedAlgoList.push_back(algBitNumber);
2171 
2172  LogTrace("L1GtHwValidation") << "\n Error: one or more conditions from algorithm " << algName << " (bit number "
2173  << algBitNumber << ") "
2174  << " not found in condition map!"
2175  << "\n Add it to list of algorithms excluded from comparison"
2176  << "\n data versus emulator." << std::endl;
2177  }
2178 
2179  if (algWithExcludedCondition) {
2180  m_excludedAlgoList.push_back(algBitNumber);
2181 
2182  LogTrace("L1GtHwValidation") << "\n Algorithm " << algName << " (bit number " << algBitNumber
2183  << ") contains an excluded condition."
2184  << "\n Add it to list of algorithms excluded from comparison"
2185  << "\n data versus emulator." << std::endl;
2186  }
2187 
2188  // add algorithm triggers from ExcludeAlgoTrigByName
2189  for (std::vector<std::string>::const_iterator itExcl = m_excludeAlgoTrigByName.begin();
2190  itExcl != m_excludeAlgoTrigByName.end();
2191  ++itExcl) {
2192  if ((*itExcl) == algName) {
2193  m_excludedAlgoList.push_back(algBitNumber);
2194 
2195  LogTrace("L1GtHwValidation") << "\n Algorithm " << algName << " (bit number " << algBitNumber
2196  << ")\n added to list of algorithms excluded from comparison"
2197  << " \n data versus emulator by ExcludeAlgoTrigByName." << std::endl;
2198  }
2199  }
2200 
2201  // add algorithm triggers from ExcludeAlgoTrigByBit
2202  for (std::vector<int>::const_iterator itExcl = m_excludeAlgoTrigByBit.begin();
2203  itExcl != m_excludeAlgoTrigByBit.end();
2204  ++itExcl) {
2205  if ((*itExcl) == algBitNumber) {
2206  m_excludedAlgoList.push_back(algBitNumber);
2207 
2208  LogTrace("L1GtHwValidation") << "\n Algorithm " << algName << " (bit number " << algBitNumber
2209  << ")\n added to list of algorithms excluded from comparison"
2210  << " \n data versus emulator by ExcludeAlgoTrigByBit." << std::endl;
2211  }
2212  }
2213  }
2214 }
2215 
2216 bool L1GtHwValidation::excludedAlgo(const int& iBit) const {
2217  for (std::vector<int>::const_iterator itAlgo = m_excludedAlgoList.begin(); itAlgo != m_excludedAlgoList.end();
2218  ++itAlgo) {
2219  if (iBit == *itAlgo) {
2220  return true;
2221  }
2222  }
2223 
2224  return false;
2225 }
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Definition: L1GtHwValidation.h:247
L1GtHwValidation::m_agree
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Definition: L1GtHwValidation.h:190
L1GtHwValidation::m_l1GtTmAlgoCacheID
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Definition: L1GtHwValidation.h:203
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Definition: L1GtHwValidation.h:116
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Definition: L1GtFdlWord.h:63
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Definition: L1GlobalTriggerReadoutSetup.h:36
Run.h
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Definition: L1GtTriggerMenuFwd.h:31
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Definition: L1GtTriggerMaskAlgoTrigRcd.h:39
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L1GtHwValidation::~L1GtHwValidation
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Definition: L1GtPsbWord.h:71
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MonitorElement * m_fdlDataEmulTechDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:251
L1GtPsbWord::print
void print(std::ostream &myCout) const
pretty print
Definition: L1GtPsbWord.cc:348
L1GtHwValidation::m_fdlDataEmulAlgoDecision
MonitorElement * m_fdlDataEmulAlgoDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:233
L1GtHwValidation::m_fdlDataAlgoDecisionPrescaledMask_NoMatch
MonitorElement * m_fdlDataAlgoDecisionPrescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:216
L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaled_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionUnprescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:226
L1GtHwValidation::analyze
void analyze(const edm::Event &, const edm::EventSetup &) override
Definition: L1GtHwValidation.cc:2034
L1GlobalTriggerReadoutRecord::gtPsbVector
const std::vector< L1GtPsbWord > gtPsbVector() const
get the vector of L1GtPsbWord
Definition: L1GlobalTriggerReadoutRecord.h:131
L1GtHwValidation::m_fdlDataTechDecision
MonitorElement * m_fdlDataTechDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:242
L1GtHwValidation::m_gtErrorFlag
MonitorElement * m_gtErrorFlag
PSB.
Definition: L1GtHwValidation.h:261
L1GtConditionType
L1GtConditionType
Definition: L1GtDefinitions.h:4
L1GtHwValidation::m_l1GtPfTechCacheID
unsigned long long m_l1GtPfTechCacheID
Definition: L1GtHwValidation.h:172
funct::true
true
Definition: Factorize.h:173
L1GtHwValidation::m_l1GtDataEvmInputToken_
edm::EDGetTokenT< L1GlobalTriggerEvmReadoutRecord > m_l1GtDataEvmInputToken_
Definition: L1GtHwValidation.h:272
L1GtPsbWord::eventNr
const cms_uint32_t eventNr() const
get/set event number since last L1 reset generated in PSB
Definition: L1GtPsbWord.h:97
L1GtHwValidation::m_fdlEmulAlgoDecision_NoMatch
MonitorElement * m_fdlEmulAlgoDecision_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:224
L1GtHwValidation::m_dirName
std::string m_dirName
directory name for L1Extra plots
Definition: L1GtHwValidation.h:131
L1GtPsbWord::NumberBData
static const int NumberBData
Definition: L1GtPsbWord.h:32
electrons_cff.objType
objType
Definition: electrons_cff.py:519
LogDebug
#define LogDebug(id)
Definition: MessageLogger.h:233
l1GtObjectStringToEnum
L1GtObject l1GtObjectStringToEnum(const std::string &)
Definition: L1GtObject.cc:24
edm::ParameterSet
Definition: ParameterSet.h:47
L1GtHwValidation::m_excludedCondType
std::vector< L1GtConditionType > m_excludedCondType
excluded condition types
Definition: L1GtHwValidation.h:148
L1GtHwValidation::m_fdlDataEmulAlgoDecisionUnprescaled
MonitorElement * m_fdlDataEmulAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:235
L1GtHwValidation::m_fdlDataAlgoDecisionMask
MonitorElement * m_fdlDataAlgoDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:211
L1GtHwValidation::comparePSB
virtual void comparePSB(const edm::Event &, const edm::EventSetup &, const L1GtPsbWord &, const L1GtPsbWord &)
compare the PSB board
Definition: L1GtHwValidation.cc:1633
ParameterSet
Definition: Functions.h:16
L1GlobalTriggerReadoutSetup.h
B2GTnPMonitor_cfi.histTitle
histTitle
Definition: B2GTnPMonitor_cfi.py:112
L1GtfeWord::bxNr
const cms_uint16_t bxNr() const
get/set bunch cross number as counted in the GTFE board
Definition: L1GtfeWord.h:93
L1GtTriggerMask::gtTriggerMask
const std::vector< unsigned int > & gtTriggerMask() const
get the trigger mask
Definition: L1GtTriggerMask.h:47
L1GtHwValidation::m_excludedAlgoList
std::vector< int > m_excludedAlgoList
Definition: L1GtHwValidation.h:267
L1GtHwValidation::m_prescaleFactorsAlgoTrig
const std::vector< std::vector< int > > * m_prescaleFactorsAlgoTrig
Definition: L1GtHwValidation.h:174
L1GtFdlWord::printGtDecisionWordExtended
void printGtDecisionWordExtended(std::ostream &myCout) const
Definition: L1GtFdlWord.cc:413
L1GtFdlWord
Definition: L1GtFdlWord.h:29
L1GlobalTriggerReadoutRecord::gtfeWord
const L1GtfeWord gtfeWord() const
get / set GTFE word (record) in the GT readout record
Definition: L1GlobalTriggerReadoutRecord.cc:367
createfilelist.int
int
Definition: createfilelist.py:10
Skims_PDWG_cff.prescaleFactor
prescaleFactor
Definition: Skims_PDWG_cff.py:25
iEvent
int iEvent
Definition: GenABIO.cc:224
L1GtHwValidation::m_l1GtTmTech
const L1GtTriggerMask * m_l1GtTmTech
Definition: L1GtHwValidation.h:181
dqm::impl::MonitorElement::setBinLabel
virtual void setBinLabel(int bin, const std::string &label, int axis=1)
set bin label for x, y or z axis (axis=1, 2, 3 respectively)
Definition: MonitorElement.cc:771
L1GtPrescaleFactorsAlgoTrigRcd.h
L1GtHwValidation::m_fdlDataAlgoDecision_Err
MonitorElement * m_fdlDataAlgoDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:218
trackerHitRTTI::vector
Definition: trackerHitRTTI.h:21
L1GtHwValidation::m_fdlDataAlgoDecisionUnprescaledMask_NoMatch
MonitorElement * m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:217
L1GtHwValidation::m_nrEmulEventError
int m_nrEmulEventError
Definition: L1GtHwValidation.h:159
L1GtFdlWord::gtDecisionWord
const DecisionWord & gtDecisionWord() const
get/set/print algorithms bits (decision word)
Definition: L1GtFdlWord.h:128
edm::EventSetup
Definition: EventSetup.h:58
L1GtfeWord::boardId
const cms_uint16_t boardId() const
get/set board ID
Definition: L1GtfeWord.h:58
AlCaHLTBitMon_QueryRunRegistry.string
string string
Definition: AlCaHLTBitMon_QueryRunRegistry.py:256
L1GtFdlWord::bxNr
const cms_uint16_t bxNr() const
get/set BxNr - bunch cross number of the actual bx
Definition: L1GtFdlWord.h:88
L1GtHwValidation::m_excludeAlgoTrigByBit
std::vector< int > m_excludeAlgoTrigByBit
exclude algorithm triggers from comparison data - emulator by algorithm bit number
Definition: L1GtHwValidation.h:141
L1GtHwValidation::excludedAlgoList
void excludedAlgoList()
exclude from comparison some bits with known disagreement - bit list
Definition: L1GtHwValidation.cc:2096
edm::EventSetup::getData
bool getData(T &iHolder) const
Definition: EventSetup.h:127
L1GtTriggerMenu::gtConditionMap
const std::vector< ConditionMap > & gtConditionMap() const
get / set / build the condition maps
Definition: L1GtTriggerMenu.h:80
DecisionWord
std::vector< bool > DecisionWord
typedefs
Definition: L1GlobalTriggerReadoutSetupFwd.h:34
L1GtHwValidation::compareGTFE
virtual void compareGTFE(const edm::Event &, const edm::EventSetup &, const L1GtfeWord &, const L1GtfeWord &, const int)
compare the GTFE board
Definition: L1GtHwValidation.cc:800
L1GtHwValidation::m_fdlDataAlgoDecisionUnprescaled
MonitorElement * m_fdlDataAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:210
L1GtHwValidation::matchCondCategory
bool matchCondCategory(const L1GtConditionCategory &, const L1GtConditionCategory &)
book all histograms for the module
Definition: L1GtHwValidation.cc:2048
L1GtHwValidation::m_fdlDataAlgoDecisionUnprescaled_NoMatch
MonitorElement * m_fdlDataAlgoDecisionUnprescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:214
DecisionWordExtended
std::vector< bool > DecisionWordExtended
Definition: L1GlobalTriggerReadoutSetupFwd.h:38
std
Definition: JetResolutionObject.h:76
L1GtFdlWord::gtTechnicalTriggerWord
const TechnicalTriggerWord & gtTechnicalTriggerWord() const
get/set technical trigger bits
Definition: L1GtFdlWord.h:112
L1GtHwValidation::m_triggerMaskTechTrig
std::vector< unsigned int > m_triggerMaskTechTrig
Definition: L1GtHwValidation.h:185
L1GtfeWord::recordLength1
const cms_uint16_t recordLength1() const
get/set record length for alternative 1
Definition: L1GtfeWord.h:71
L1GtHwValidation::compareFDL
virtual void compareFDL(const edm::Event &, const edm::EventSetup &, const L1GtFdlWord &, const L1GtFdlWord &, const int)
compare the FDL board
Definition: L1GtHwValidation.cc:974
L1GtHwValidation::m_dataOnly
bool m_dataOnly
Definition: L1GtHwValidation.h:191
L1GtHwValidation::l1gtPrescaleAlgoToken_
edm::ESGetToken< L1GtPrescaleFactors, L1GtPrescaleFactorsAlgoTrigRcd > l1gtPrescaleAlgoToken_
Definition: L1GtHwValidation.h:275
L1GtHwValidation::m_emulOnlyMask
bool m_emulOnlyMask
Definition: L1GtHwValidation.h:194
L1GtFdlWord::printGtTechnicalTriggerWord
void printGtTechnicalTriggerWord(std::ostream &myCout) const
Definition: L1GtFdlWord.cc:227
L1GtHwValidation::m_fdlDataEmulAlgoDecisionPrescaled
MonitorElement * m_fdlDataEmulAlgoDecisionPrescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:234
L1GtFdlWord::print
void print(std::ostream &myCout) const
pretty print the content of a L1GtFdlWord
Definition: L1GtFdlWord.cc:595
L1GtHwValidation::m_l1GtEmulDaqInputTag
edm::InputTag m_l1GtEmulDaqInputTag
input tag for the L1 GT emulator DAQ record
Definition: L1GtHwValidation.h:122
L1GtPsbWord::localBxNr
const cms_uint16_t localBxNr() const
get/set local bunch cross number of the actual bx
Definition: L1GtPsbWord.h:134
L1GtHwValidation::m_fdlEmulTechDecision
MonitorElement * m_fdlEmulTechDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:246
EventSetup.h
edm::ParameterSet::getParameter
T getParameter(std::string const &) const
Definition: ParameterSet.h:303
L1GtHwValidation::m_l1GtPfTech
const L1GtPrescaleFactors * m_l1GtPfTech
Definition: L1GtHwValidation.h:171
L1GtHwValidation::m_fdlDataEmulTechDecision
MonitorElement * m_fdlDataEmulTechDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:250
L1GtHwValidation::m_l1GtEmulEvmInputTag
edm::InputTag m_l1GtEmulEvmInputTag
input tag for the L1 GT emulator EVM record
Definition: L1GtHwValidation.h:125
dqm::implementation::IBooker
Definition: DQMStore.h:43
L1GtHwValidation::m_fdlEmulAlgoDecisionPrescaledMask_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:228
L1GtHwValidation::excludedAlgo
bool excludedAlgo(const int &) const
exclusion status for algorithm with bit i
Definition: L1GtHwValidation.cc:2216
L1GlobalTriggerReadoutSetup::NumberTechnicalTriggers
static const unsigned int NumberTechnicalTriggers
Definition: L1GlobalTriggerReadoutSetup.h:38
L1GtHwValidation::m_fdlDataAlgoDecision
MonitorElement * m_fdlDataAlgoDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:208
L1GtHwValidation::matchCondL1GtObject
bool matchCondL1GtObject(const std::vector< L1GtObject > &, const L1GtObject &)
Definition: L1GtHwValidation.cc:2077
LogTrace
#define LogTrace(id)
Definition: MessageLogger.h:234
TypeNull
Definition: L1GtDefinitions.h:5
L1GtHwValidation::m_fdlDataAlgoDecisionPrescaled_NoMatch
MonitorElement * m_fdlDataAlgoDecisionPrescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:213
L1GtHwValidation::m_fdlDataEmulAlgoDecisionUnprescaledAllowed
MonitorElement * m_fdlDataEmulAlgoDecisionUnprescaledAllowed[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:236
TechnicalTriggerWord
std::vector< bool > TechnicalTriggerWord
technical trigger bits (64 bits)
Definition: L1GlobalTriggerReadoutSetupFwd.h:41
L1GtPrescaleFactorsAlgoTrigRcd
Definition: L1GtPrescaleFactorsAlgoTrigRcd.h:38
L1GtFdlWord::finalOR
const cms_uint16_t finalOR() const
get/set "Final OR" bits
Definition: L1GtFdlWord.h:221
L1GtHwValidation::l1gtTrigmaskTechToken_
edm::ESGetToken< L1GtTriggerMask, L1GtTriggerMaskTechTrigRcd > l1gtTrigmaskTechToken_
Definition: L1GtHwValidation.h:277
L1GtHwValidation::m_fdlDataAlgoDecisionPrescaled
MonitorElement * m_fdlDataAlgoDecisionPrescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:209
edm::HandleBase::isValid
bool isValid() const
Definition: HandleBase.h:70
L1GtHwValidation::m_l1GtTmAlgo
const L1GtTriggerMask * m_l1GtTmAlgo
trigger masks
Definition: L1GtHwValidation.h:178
L1GtHwValidation::m_fdlEmulAlgoDecisionMask
MonitorElement * m_fdlEmulAlgoDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:223
edm::Event
Definition: Event.h:73
L1GtfeWord::altNrBxBoard
const cms_uint16_t altNrBxBoard() const
get/set alternative for number of BX per board
Definition: L1GtfeWord.h:134
L1GtHwValidation::m_l1GtMenuCacheID
unsigned long long m_l1GtMenuCacheID
Definition: L1GtHwValidation.h:165
L1GtPsbWord::NumberAData
static const int NumberAData
Definition: L1GtPsbWord.h:31
TauDecayModes.dec
dec
Definition: TauDecayModes.py:142
edm::InputTag
Definition: InputTag.h:15
L1GlobalTriggerReadoutRecord.h
L1GtHwValidation::m_fdlDataTechDecision_Err
MonitorElement * m_fdlDataTechDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:244
L1GtHwValidation::m_l1GtEmulEvmInputToken_
edm::EDGetTokenT< L1GlobalTriggerEvmReadoutRecord > m_l1GtEmulEvmInputToken_
Definition: L1GtHwValidation.h:273
L1GtPsbWord::boardId
const cms_uint16_t boardId() const
get/set board ID
Definition: L1GtPsbWord.h:58
L1GtHwValidation::compareEvmRecord
virtual void compareEvmRecord(const edm::Event &, const edm::EventSetup &)
L1 GT EVM record comparison.
Definition: L1GtHwValidation.cc:1947
L1GtPrescaleFactors.h
L1GlobalTriggerReadoutRecord::gtFdlVector
const std::vector< L1GtFdlWord > gtFdlVector() const
get the vector of L1GtFdlWord
Definition: L1GlobalTriggerReadoutRecord.h:119
L1GtTriggerMenu::gtAlgorithmMap
const AlgorithmMap & gtAlgorithmMap() const
get / set the algorithm map (by name)
Definition: L1GtTriggerMenu.h:187
L1GtObject
dqm::implementation::IBooker::book1D
MonitorElement * book1D(TString const &name, TString const &title, int const nchX, double const lowX, double const highX, FUNC onbooking=NOOP())
Definition: DQMStore.h:98
L1GtHwValidation::m_excludedL1GtObject
std::vector< L1GtObject > m_excludedL1GtObject
excluded L1 GT objects
Definition: L1GtHwValidation.h:151
L1GtHwValidation::compareTCS
virtual void compareTCS(const edm::Event &, const edm::EventSetup &, const L1TcsWord &, const L1TcsWord &)
compare the TCS board
Definition: L1GtHwValidation.cc:1790
L1GtFdlWord::printGtDecisionWord
void printGtDecisionWord(std::ostream &myCout) const
Definition: L1GtFdlWord.cc:286
L1GtHwValidation.h
L1GtHwValidation::m_excludeAlgoTrigByName
std::vector< std::string > m_excludeAlgoTrigByName
exclude algorithm triggers from comparison data - emulator by algorithm name
Definition: L1GtHwValidation.h:138
L1GtHwValidation::m_dataOnlyMask
bool m_dataOnlyMask
Definition: L1GtHwValidation.h:193
L1GtPrescaleFactorsTechTrigRcd.h
L1GtHwValidation::m_l1GtPfAlgoCacheID
unsigned long long m_l1GtPfAlgoCacheID
Definition: L1GtHwValidation.h:169
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