23 int pretrig_chan[4] = {0, 0, 0, 0};
24 unsigned int tbin_strt, tbin_stop;
25 unsigned int ibit, jbit, itbin, ich, iram,
iline, iadr;
29 LogTrace(
"CSCTMBScope|CSCRawToDigi") <<
" .....TMBHeader -- unpacking Logic Analyzer......";
32 if ((e05Line - b05Line) == 1537) {
34 LogTrace(
"CSCTMBScope|CSCRawToDigi") <<
"Scope data found";
38 for (iram = 0; iram < 6; iram++) {
39 for (iadr = 0; iadr < 256; iadr++) {
46 for (ich = 0; ich < 51; ich++)
56 tbin_strt = pretrig_chan[0] - 7;
57 tbin_stop = pretrig_chan[0] + 24;
59 for (ich = 0; ich <= 14; ich++) {
62 for (itbin = tbin_strt; itbin <= tbin_stop; itbin++) {
63 ibit = (
scope_ram[itbin][iram] >> (ich % 16)) & 1;
64 data[ich] = (ibit << jbit) |
data[ich];
70 for (ich = 16; ich <= 30; ich++) {
73 for (itbin = tbin_strt; itbin <= tbin_stop; itbin++) {
74 ibit = (
scope_ram[itbin][iram] >> (ich % 16)) & 1;
75 data[ich - 1] = (ibit << jbit) |
data[ich - 1];
81 tbin_strt = pretrig_chan[1] - 7;
82 tbin_stop = pretrig_chan[1] + 24;
84 for (ich = 32; ich <= 36; ich++) {
87 for (itbin = tbin_strt; itbin <= tbin_stop; itbin++) {
88 ibit = (
scope_ram[itbin][iram] >> (ich % 16)) & 1;
89 data[ich - 2] = (ibit << jbit) |
data[ich - 2];
94 tbin_strt = pretrig_chan[1] - 7 + 120;
95 tbin_stop = pretrig_chan[1] + 24 + 120;
97 for (ich = 37; ich <= 40; ich++) {
100 for (itbin = tbin_strt; itbin <= tbin_stop; itbin++) {
101 ibit = (
scope_ram[itbin][iram] >> (ich % 16)) & 1;
102 data[ich - 2] = (ibit << jbit) |
data[ich - 2];
107 tbin_strt = pretrig_chan[1] - 7;
108 tbin_stop = pretrig_chan[1] + 24;
110 for (ich = 41; ich <= 46; ich++) {
113 for (itbin = tbin_strt; itbin <= tbin_stop; itbin++) {
114 ibit = (
scope_ram[itbin][iram] >> (ich % 16)) & 1;
115 data[ich - 2] = (ibit << jbit) |
data[ich - 2];
121 tbin_strt = pretrig_chan[2] - 7;
122 tbin_stop = pretrig_chan[2] + 24;
124 for (ich = 48; ich <= 53; ich++) {
127 for (itbin = tbin_strt; itbin <= tbin_stop; itbin++) {
128 ibit = (
scope_ram[itbin][iram] >> (ich % 16)) & 1;
129 data[ich - 3] = (ibit << jbit) |
data[ich - 3];
138 for (ich = 65; ich <= 76; ich++) {
140 itbin = pretrig_chan[3];
141 ibit = (
scope_ram[itbin][iram] >> (ich % 16)) & 1;
142 lct_bxn = (ibit << jbit) | lct_bxn;
148 LogTrace(
"CSCTMBScope|CSCRawToDigi") <<
"Scope bxn at LCT (seq_pretrig): " << lct_bxn;
152 for (ich = 0; ich <= 50; ich++) {
153 for (itbin = 0; itbin < 32; itbin++) {
154 ibit = (
data[ich] >> itbin) & 1;
156 LogTrace(
"CSCTMBScope|CSCRawToDigi") <<
"_";
158 LogTrace(
"CSCTMBScope|CSCRawToDigi") <<
"-";
167 for (ich = 0; ich < 51; ich++)
173 LogTrace(
"CSCTMBScope|CSCRawToDigi") <<
"No scope data found: wrdcnt: " << (e05Line - b05Line);
177 LogTrace(
"CSCTMBScope|CSCRawToDigi") <<
" .....END -- unpacking Logic Analyzer...........";
180 return (e05Line - b05Line + 1);