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SiStripFecCabling.cc
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1 
2 #include "CalibFormats/SiStripObjects/interface/SiStripFecCabling.h"
3 #include "DataFormats/SiStripCommon/interface/SiStripConstants.h"
4 #include "FWCore/MessageLogger/interface/MessageLogger.h"
5 #include "FWCore/Utilities/interface/typelookup.h"
6 #include <iomanip>
7 #include <iostream>
8 
9 using namespace sistrip;
10 
11 // -----------------------------------------------------------------------------
12 //
13 SiStripFecCabling::SiStripFecCabling(const SiStripFedCabling &fed_cabling) : crates_() {
14  LogTrace(mlCabling_) << "[SiStripFecCabling::" << __func__ << "]"
15  << " Constructing object...";
16  crates_.reserve(4);
17  buildFecCabling(fed_cabling);
18 }
19 
20 // -----------------------------------------------------------------------------
21 //
22 void SiStripFecCabling::buildFecCabling(const SiStripFedCabling &fed_cabling) {
23  LogTrace(mlCabling_) << "[SiStripFecCabling::" << __func__ << "]"
24  << " Building FEC cabling...";
25 
26  // Retrieve and iterate through FED ids
27  auto feds = fed_cabling.fedIds();
28  for (auto ifed = feds.begin(); ifed != feds.end(); ifed++) {
29  // Retrieve and iterate through FED channel connections
30  auto conns = fed_cabling.fedConnections(*ifed);
31  for (auto iconn = conns.begin(); iconn != conns.end(); iconn++) {
32  // Check that FED id is not invalid and add devices
33  if (iconn->fedId() != sistrip::invalid_) {
34  addDevices(*iconn);
35  }
36  }
37  }
38 
39  // Consistency checks
40  for (std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end();
41  ++icrate) {
42  for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
43  for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
44  ++iring) {
45  for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
46  ++iccu) {
47  for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
48  ++imod) {
49  //@@ need consistency checks here!
50  }
51  }
52  }
53  }
54  }
55  LogTrace(mlCabling_) << "[SiStripFecCabling::" << __func__ << "]"
56  << " Finished building FEC cabling";
57 }
58 
59 // -----------------------------------------------------------------------------
60 //
61 void SiStripFecCabling::addDevices(const FedChannelConnection &conn) {
62  auto icrate = crates_.begin();
63  while (icrate != crates_.end() && (*icrate).fecCrate() != conn.fecCrate()) {
64  icrate++;
65  }
66  if (icrate == crates_.end()) {
67  crates_.push_back(SiStripFecCrate(conn));
68  } else {
69  icrate->addDevices(conn);
70  }
71 }
72 
73 // -----------------------------------------------------------------------------
74 //
75 void SiStripFecCabling::connections(std::vector<FedChannelConnection> &conns) const {
76  LogTrace(mlCabling_) << "[SiStripFecCabling::" << __func__ << "]"
77  << " Building vector of FedChannelConnection objects...";
78  conns.clear();
79  for (std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end();
80  ++icrate) {
81  for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
82  for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
83  ++iring) {
84  for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
85  ++iccu) {
86  for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
87  ++imod) {
88  for (uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++) {
89  conns.push_back(FedChannelConnection(icrate->fecCrate(),
90  ifec->fecSlot(),
91  iring->fecRing(),
92  iccu->ccuAddr(),
93  imod->ccuChan(),
94  imod->activeApvPair(imod->lldChannel(ipair)).first,
95  imod->activeApvPair(imod->lldChannel(ipair)).second,
96  imod->dcuId(),
97  imod->detId(),
98  imod->nApvPairs(),
99  imod->fedCh(ipair).fedId_,
100  imod->fedCh(ipair).fedCh_,
101  imod->length(),
102  imod->dcu(),
103  imod->pll(),
104  imod->mux(),
105  imod->lld()));
106  uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
107  uint16_t fed_slot = imod->fedCh(ipair).fedSlot_;
108  conns.back().fedCrate(fed_crate);
109  conns.back().fedSlot(fed_slot);
110  }
111  }
112  }
113  }
114  }
115  }
116 }
117 
118 // -----------------------------------------------------------------------------
119 //
120 namespace {
121  // Using a template allows the const and non-const version to share the same
122  // code
123  template <typename T>
124  auto moduleFrom(T &crates, const FedChannelConnection &conn)
125  -> decltype(&(crates[0].fecs()[0].rings()[0].ccus()[0].modules()[0])) {
126  std::stringstream ss;
127  auto icrate = crates.begin();
128  while (icrate != crates.end() && icrate->fecCrate() != conn.fecCrate()) {
129  icrate++;
130  }
131  if (icrate != crates.end()) {
132  auto ifec = icrate->fecs().begin();
133  while (ifec != icrate->fecs().end() && ifec->fecSlot() != conn.fecSlot()) {
134  ifec++;
135  }
136  if (ifec != icrate->fecs().end()) {
137  auto iring = ifec->rings().begin();
138  while (iring != ifec->rings().end() && iring->fecRing() != conn.fecRing()) {
139  iring++;
140  }
141  if (iring != ifec->rings().end()) {
142  auto iccu = iring->ccus().begin();
143  while (iccu != iring->ccus().end() && iccu->ccuAddr() != conn.ccuAddr()) {
144  iccu++;
145  }
146  if (iccu != iring->ccus().end()) {
147  auto imod = iccu->modules().begin();
148  while (imod != iccu->modules().end() && imod->ccuChan() != conn.ccuChan()) {
149  imod++;
150  }
151  if (imod != iccu->modules().end()) {
152  return &(*imod);
153  } else {
154  ss << "[SiStripFecCabling::" << __func__ << "]"
155  << " CCU channel " << conn.ccuChan() << " not found!";
156  }
157  } else {
158  ss << "[SiStripFecCabling::" << __func__ << "]"
159  << " CCU address " << conn.ccuAddr() << " not found!";
160  }
161  } else {
162  ss << "[SiStripFecCabling::" << __func__ << "]"
163  << " FEC ring " << conn.fecRing() << " not found!";
164  }
165  } else {
166  ss << "[SiStripFecCabling::" << __func__ << "]"
167  << " FEC slot " << conn.fecSlot() << " not found!";
168  }
169  } else {
170  ss << "[SiStripFecCabling::" << __func__ << "]"
171  << " FEC crate " << conn.fecCrate() << " not found!";
172  }
173 
174  if (!ss.str().empty()) {
175  edm::LogWarning(mlCabling_) << ss.str();
176  }
177  return nullptr;
178  }
179 } // namespace
180 
181 const SiStripModule &SiStripFecCabling::module(const FedChannelConnection &conn) const {
182  auto module = moduleFrom(crates(), conn);
183  if (module) {
184  return *module;
185  }
186 
187  static const SiStripModule s_module{FedChannelConnection{}};
188  return s_module;
189 }
190 
191 SiStripModule *SiStripFecCabling::module(const FedChannelConnection &conn) { return moduleFrom(crates(), conn); }
192 
193 // -----------------------------------------------------------------------------
194 //
195 const SiStripModule &SiStripFecCabling::module(const uint32_t &dcu_id) const {
196  for (std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end();
197  ++icrate) {
198  for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
199  for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
200  ++iring) {
201  for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
202  ++iccu) {
203  for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
204  ++imod) {
205  if ((*imod).dcuId() == dcu_id) {
206  return *imod;
207  }
208  }
209  }
210  }
211  }
212  }
213  static const SiStripModule module{FedChannelConnection{}};
214  return module;
215 }
216 
217 // -----------------------------------------------------------------------------
218 //
219 NumberOfDevices SiStripFecCabling::countDevices() const {
220  NumberOfDevices num_of_devices; // simple container class used for counting
221 
222  std::vector<uint16_t> fed_crates;
223  std::vector<uint16_t> fed_slots;
224  std::vector<uint16_t> fed_ids;
225  for (std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end();
226  ++icrate) {
227  for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
228  for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
229  ++iring) {
230  for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
231  ++iccu) {
232  for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
233  ++imod) {
234  // APVs
235  if (imod->activeApv(32)) {
236  num_of_devices.nApvs_++;
237  }
238  if (imod->activeApv(33)) {
239  num_of_devices.nApvs_++;
240  }
241  if (imod->activeApv(34)) {
242  num_of_devices.nApvs_++;
243  }
244  if (imod->activeApv(35)) {
245  num_of_devices.nApvs_++;
246  }
247  if (imod->activeApv(36)) {
248  num_of_devices.nApvs_++;
249  }
250  if (imod->activeApv(37)) {
251  num_of_devices.nApvs_++;
252  }
253  if (imod->dcuId()) {
254  num_of_devices.nDcuIds_++;
255  }
256  if (imod->detId()) {
257  num_of_devices.nDetIds_++;
258  }
259 
260  // APV pairs
261  num_of_devices.nApvPairs_ += imod->nApvPairs();
262  if (imod->nApvPairs() == 0) {
263  num_of_devices.nApvPairs0_++;
264  } else if (imod->nApvPairs() == 1) {
265  num_of_devices.nApvPairs1_++;
266  } else if (imod->nApvPairs() == 2) {
267  num_of_devices.nApvPairs2_++;
268  } else if (imod->nApvPairs() == 3) {
269  num_of_devices.nApvPairs3_++;
270  } else {
271  num_of_devices.nApvPairsX_++;
272  }
273 
274  // FED crates, slots, ids, channels
275  for (uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++) {
276  uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
277  uint16_t fed_slot = imod->fedCh(ipair).fedSlot_;
278  uint16_t fed_id = imod->fedCh(ipair).fedId_;
279 
280  if (fed_id) {
281  num_of_devices.nFedChans_++;
282 
283  std::vector<uint16_t>::iterator icrate = find(fed_crates.begin(), fed_crates.end(), fed_crate);
284  if (icrate == fed_crates.end()) {
285  num_of_devices.nFedCrates_++;
286  fed_crates.push_back(fed_crate);
287  }
288 
289  std::vector<uint16_t>::iterator islot = find(fed_slots.begin(), fed_slots.end(), fed_slot);
290  if (islot == fed_slots.end()) {
291  num_of_devices.nFedSlots_++;
292  fed_slots.push_back(fed_slot);
293  }
294 
295  std::vector<uint16_t>::iterator ifed = find(fed_ids.begin(), fed_ids.end(), fed_id);
296  if (ifed == fed_ids.end()) {
297  num_of_devices.nFedIds_++;
298  fed_ids.push_back(fed_id);
299  }
300  }
301  }
302 
303  // FE devices
304  if (imod->dcu()) {
305  num_of_devices.nDcus_++;
306  }
307  if (imod->mux()) {
308  num_of_devices.nMuxes_++;
309  }
310  if (imod->pll()) {
311  num_of_devices.nPlls_++;
312  }
313  if (imod->lld()) {
314  num_of_devices.nLlds_++;
315  }
316 
317  // FE modules
318  num_of_devices.nCcuChans_++;
319  }
320  num_of_devices.nCcuAddrs_++;
321  }
322  num_of_devices.nFecRings_++;
323  }
324  num_of_devices.nFecSlots_++;
325  }
326  num_of_devices.nFecCrates_++;
327  }
328 
329  return num_of_devices;
330 }
331 
332 // -----------------------------------------------------------------------------
333 //
334 void SiStripFecCabling::print(std::stringstream &ss) const {
335  uint32_t valid = 0;
336  uint32_t total = 0;
337  ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
338  ss << "Printing cabling for " << crates().size() << " crates" << std::endl;
339  for (std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); ++icrate) {
340  ss << "Printing cabling for " << icrate->fecs().size() << " FECs for crate " << icrate->fecCrate() << std::endl;
341  for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
342  ss << "Printing cabling for " << ifec->rings().size() << " rings for FEC " << ifec->fecSlot() << std::endl;
343  for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
344  ++iring) {
345  ss << "Printing cabling for " << iring->ccus().size() << " CCUs for ring " << iring->fecRing() << std::endl;
346  for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
347  ++iccu) {
348  ss << "Printing cabling for " << iccu->modules().size() << " modules for CCU " << iccu->ccuAddr()
349  << std::endl;
350  for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
351  ++imod) {
352  SiStripModule::FedCabling conns = imod->fedChannels();
353  SiStripModule::FedCabling::const_iterator ii = conns.begin();
354  SiStripModule::FedCabling::const_iterator jj = conns.end();
355  for (; ii != jj; ++ii) {
356  if (ii->second.fedId_ != sistrip::invalid_ && ii->second.fedCh_ != sistrip::invalid_) {
357  valid++;
358  }
359  total++;
360  }
361  ss << *imod << std::endl;
362  }
363  }
364  }
365  }
366  }
367  ss << "Number of connected: " << valid << std::endl << "Number of connections: " << total << std::endl;
368 }
369 
370 // -----------------------------------------------------------------------------
371 //
372 void SiStripFecCabling::terse(std::stringstream &ss) const {
373  ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
374  for (std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); ++icrate) {
375  for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ++ifec) {
376  for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
377  ++iring) {
378  for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
379  ++iccu) {
380  for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
381  ++imod) {
382  imod->terse(ss);
383  ss << std::endl;
384  }
385  }
386  }
387  }
388  }
389 }
390 
391 // -----------------------------------------------------------------------------
392 //
393 std::ostream &operator<<(std::ostream &os, const SiStripFecCabling &cabling) {
394  std::stringstream ss;
395  cabling.print(ss);
396  os << ss.str();
397  return os;
398 }
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