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SiStripFedCablingFakeESSource.cc
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10 #include <sstream>
11 #include <vector>
12 #include <map>
13 
14 using namespace sistrip;
15 
16 // -----------------------------------------------------------------------------
17 //
19  : SiStripFedCablingESProducer(pset), fedIds_(pset.getParameter<edm::FileInPath>("FedIdsFile")), pset_(pset) {
20  findingRecord<SiStripFedCablingRcd>();
21  m_detInfoFileReader = SiStripDetInfoFileReader{pset.getParameter<edm::FileInPath>("SiStripDetInfoFile").fullPath()};
22  edm::LogVerbatim("FedCabling") << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
23  << " Constructing object...";
24 }
25 
26 // -----------------------------------------------------------------------------
27 //
29  edm::LogVerbatim("FedCabling") << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
30  << " Destructing object...";
31 }
32 
33 // -----------------------------------------------------------------------------
34 //
36  edm::LogVerbatim("FedCabling") << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
37  << " Building \"fake\" FED cabling map"
38  << " from real DetIds and FedIds (read from ascii file)";
39 
40  // Create FEC cabling object
41  SiStripFecCabling* fec_cabling = new SiStripFecCabling();
42 
43  // Read DetId list from file
44  typedef std::vector<uint32_t> Dets;
45  Dets dets = m_detInfoFileReader.getAllDetIds();
46 
47  // Read FedId list from file
48  typedef std::vector<uint16_t> Feds;
50 
51  bool populateAllFeds = pset_.getParameter<bool>("PopulateAllFeds");
52 
53  // Iterator through DetInfo objects and populate FEC cabling object
54  uint32_t imodule = 0;
55  Dets::const_iterator idet = dets.begin();
56  Dets::const_iterator jdet = dets.end();
57  for (; idet != jdet; ++idet) {
58  uint16_t npairs = m_detInfoFileReader.getNumberOfApvsAndStripLength(*idet).first / 2;
59  for (uint16_t ipair = 0; ipair < npairs; ++ipair) {
60  uint16_t addr = 0;
61  if (npairs == 2 && ipair == 0) {
62  addr = 32;
63  } else if (npairs == 2 && ipair == 1) {
64  addr = 36;
65  } else if (npairs == 3 && ipair == 0) {
66  addr = 32;
67  } else if (npairs == 3 && ipair == 1) {
68  addr = 34;
69  } else if (npairs == 3 && ipair == 2) {
70  addr = 36;
71  } else {
72  edm::LogWarning("FedCabling") << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
73  << " Inconsistent values for nPairs (" << npairs << ") and ipair (" << ipair
74  << ")!";
75  }
76  uint32_t module_key =
77  SiStripFecKey(fecCrate(imodule), fecSlot(imodule), fecRing(imodule), ccuAddr(imodule), ccuChan(imodule)).key();
79  fecSlot(imodule),
80  fecRing(imodule),
81  ccuAddr(imodule),
82  ccuChan(imodule),
83  addr,
84  addr + 1, // apv i2c addresses
85  module_key, // dcu id
86  *idet, // det id
87  npairs); // apv pairs
88  fec_cabling->addDevices(conn);
89  }
90  imodule++;
91  }
92 
93  // Assign "dummy" FED ids/chans
94  bool insufficient = false;
95  Feds::const_iterator ifed = feds.begin();
96  uint16_t fed_ch = 0;
97  for (std::vector<SiStripFecCrate>::const_iterator icrate = fec_cabling->crates().begin();
98  icrate != fec_cabling->crates().end();
99  icrate++) {
100  for (std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++) {
101  for (std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end();
102  iring++) {
103  for (std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end();
104  iccu++) {
105  for (std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end();
106  imod++) {
107  if (populateAllFeds) {
108  for (uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++) {
109  if (ifed == feds.end()) {
110  fed_ch++;
111  ifed = feds.begin();
112  }
113  if (fed_ch == 96) {
114  insufficient = true;
115  break;
116  }
117 
118  std::pair<uint16_t, uint16_t> addr = imod->activeApvPair(imod->lldChannel(ipair));
119  SiStripModule::FedChannel fed_channel((*ifed) / 16 + 1, // 16 FEDs per crate, numbering starts from 1
120  (*ifed) % 16 + 2, // FED slot starts from 2
121  *ifed,
122  fed_ch);
123  const_cast<SiStripModule&>(*imod).fedCh(addr.first, fed_channel);
124  ifed++;
125  }
126  } else {
127  // Patch introduced by D.Giordano 2/12/08
128  //to reproduce the fake cabling used in 2x
129  //that was designed to fill each fed iteratively
130  //filling all channels of a fed before going to the next one
131  if (96 - fed_ch < imod->nApvPairs()) {
132  ifed++;
133  fed_ch = 0;
134  } // move to next FED
135  for (uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++) {
136  std::pair<uint16_t, uint16_t> addr = imod->activeApvPair((*imod).lldChannel(ipair));
137  SiStripModule::FedChannel fed_channel((*ifed) / 16 + 1, // 16 FEDs per crate, numbering starts from 1
138  (*ifed) % 16 + 2, // FED slot starts from 2
139  (*ifed),
140  fed_ch);
141  const_cast<SiStripModule&>(*imod).fedCh(addr.first, fed_channel);
142  fed_ch++;
143  }
144  }
145  }
146  }
147  }
148  }
149  }
150 
151  if (insufficient) {
152  edm::LogWarning(mlCabling_) << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
153  << " Insufficient FED channels to cable entire system!";
154  }
155 
156  // Some debug
157  std::stringstream ss;
158  ss << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
159  << " First count devices of FEC cabling " << std::endl;
160  fec_cabling->countDevices().print(ss);
161  LogTrace(mlCabling_) << ss.str();
162 
163  // Build FED cabling using FedChannelConnections
164  std::vector<FedChannelConnection> conns;
165  fec_cabling->connections(conns);
166  SiStripFedCabling* cabling = new SiStripFedCabling(conns);
167 
168  return cabling;
169 }
170 
171 // -----------------------------------------------------------------------------
172 //
174  const edm::IOVSyncValue& iov_sync,
175  edm::ValidityInterval& iov_validity) {
176  edm::ValidityInterval infinity(iov_sync.beginOfTime(), iov_sync.endOfTime());
177  iov_validity = infinity;
178 }
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Definition: SiStripFedCablingFakeESSource.h:33
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Definition: SiStripFecCabling.cc:61
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Definition: SiStripFedCabling.h:25
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Definition: SiStripFedCablingESProducer.h:48
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Definition: SiStripFecCabling.cc:219
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Definition: SiStripFedCablingESProducer.h:47
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Abstract base class for producer of SiStripFedCabling record.
Definition: SiStripFedCablingESProducer.h:17
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Definition: SiStripFecKey.h:45
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Definition: SiStripFedCablingFakeESSource.h:35
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Definition: FedChannelConnection.h:26
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Definition: SiStripDetInfoFileReader.h:52
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Definition: SiStripFedCablingESProducer.h:46
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