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L1MuCSCTFConfiguration.cc
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1 #include "CondFormats/L1TObjects/interface/L1MuCSCTFConfiguration.h"
2 #include <sstream>
3 #include <iostream>
4 #include <cstdlib>
5 #include "FWCore/MessageLogger/interface/MessageLogger.h"
6 
7 edm::ParameterSet L1MuCSCTFConfiguration::parameters(int sp) const {
8  LogDebug("L1MuCSCTFConfiguration") << "SP:" << int(sp) << std::endl;
9 
10  edm::ParameterSet pset;
11  if (sp >= 12)
12  return pset;
13 
14  // ------------------------------------------------------
15  // core configuration
16  // by default everything is disabled: we need to set them
17  // coincidence and singles
18  bool run_core = false;
19  bool trigger_on_ME1a = false;
20  bool trigger_on_ME1b = false;
21  bool trigger_on_ME2 = false;
22  bool trigger_on_ME3 = false;
23  bool trigger_on_ME4 = false;
24  bool trigger_on_MB1a = false;
25  bool trigger_on_MB1d = false;
26 
27  unsigned int BXAdepth = 0;
28  unsigned int useDT = 0;
29  unsigned int widePhi = 0;
30  unsigned int PreTrigger = 0;
31  // ------------------------------------------------------
32 
33  // ------------------------------------------------------
34  // these are very important parameters.
35  // Double check with Alex
36  unsigned int CoreLatency = 7;
37  bool rescaleSinglesPhi = true;
38 
39  // ask Alex if use or remove them or what
40  bool AllowALCTonly = false;
41  bool AllowCLCTonly = false;
42 
43  // other useful parameters in general not set in the OMDS
44  unsigned int QualityEnableME1a = 0xFFFF;
45  unsigned int QualityEnableME1b = 0xFFFF;
46  unsigned int QualityEnableME1c = 0xFFFF;
47  unsigned int QualityEnableME1d = 0xFFFF;
48  unsigned int QualityEnableME1e = 0xFFFF;
49  unsigned int QualityEnableME1f = 0xFFFF;
50  unsigned int QualityEnableME2a = 0xFFFF;
51  unsigned int QualityEnableME2b = 0xFFFF;
52  unsigned int QualityEnableME2c = 0xFFFF;
53  unsigned int QualityEnableME3a = 0xFFFF;
54  unsigned int QualityEnableME3b = 0xFFFF;
55  unsigned int QualityEnableME3c = 0xFFFF;
56  unsigned int QualityEnableME4a = 0xFFFF;
57  unsigned int QualityEnableME4b = 0xFFFF;
58  unsigned int QualityEnableME4c = 0xFFFF;
59 
60  unsigned int kill_fiber = 0;
61  unsigned int singlesTrackOutput = 1;
62  // ------------------------------------------------------
63 
64  //initialization of the DAT_ETA registers with default values
65  //the DAT_ETA registers meaning are explained at Table 2 of
66  //http://www.phys.ufl.edu/~uvarov/SP05/LU-SP_ReferenceGuide_090915_Update.pdf
67  std::vector<unsigned int> etamin(8), etamax(8), etawin(7);
68 
69  unsigned int mindetap = 8;
70  unsigned int mindetap_halo = 8;
71 
72  etamin[0] = 22;
73  etamin[1] = 22;
74  etamin[2] = 14;
75  etamin[3] = 14;
76  etamin[4] = 14;
77  etamin[5] = 14;
78  etamin[6] = 10;
79  etamin[7] = 22;
80 
81  unsigned int mindeta12_accp = 8;
82  unsigned int mindeta13_accp = 19;
83  unsigned int mindeta112_accp = 19;
84  unsigned int mindeta113_accp = 30;
85 
86  etamax[0] = 127;
87  etamax[1] = 127;
88  etamax[2] = 127;
89  etamax[3] = 127;
90  etamax[4] = 127;
91  etamax[5] = 24;
92  etamax[6] = 24;
93  etamax[7] = 127;
94 
95  unsigned int maxdeta12_accp = 14;
96  unsigned int maxdeta13_accp = 25;
97  unsigned int maxdeta112_accp = 25;
98  unsigned int maxdeta113_accp = 36;
99 
100  etawin[0] = 4;
101  etawin[1] = 4;
102  etawin[2] = 4;
103  etawin[3] = 4;
104  etawin[4] = 4;
105  etawin[5] = 4;
106  etawin[6] = 4;
107 
108  unsigned int maxdphi12_accp = 64;
109  unsigned int maxdphi13_accp = 64;
110  unsigned int maxdphi112_accp = 64;
111  unsigned int maxdphi113_accp = 64;
112 
113  unsigned int mindphip = 128;
114  unsigned int mindphip_halo = 128;
115 
116  unsigned int straightp = 60;
117  unsigned int curvedp = 200;
118 
119  unsigned int mbaPhiOff = 0;
120  // this differ from the default value in the documentation because during
121  // craft 09 it mbbPhiOff, as well as mbaPhiOff were not existing, thus set to 0 (they are offsets)
122  // and for backward compatibility it needs to be set to 0. Anyway mbbPhiOff since its introduction in the
123  // core will have to be ALWAYS part of the configuration, so it won't be never initialized to the
124  // default value 2048.
125  unsigned int mbbPhiOff = 0;
126 
127  int eta_cnt = 0;
128 
129  // default firmware versions (the ones used from run 132440)
130  unsigned int firmwareSP = 20100210;
131  unsigned int firmwareFA = 20090521;
132  unsigned int firmwareDD = 20090521;
133  unsigned int firmwareVM = 20090521;
134 
135  // default printout
136  LogDebug("L1MuCSCTFConfiguration")
137  << "\nCORE CONFIGURATION DEFAULT VALUES"
138  << "\nrun_core=" << run_core << "\ntrigger_on_ME1a=" << trigger_on_ME1a << "\ntrigger_on_ME1b=" << trigger_on_ME1b
139  << "\ntrigger_on_ME2=" << trigger_on_ME2 << "\ntrigger_on_ME3=" << trigger_on_ME3
140  << "\ntrigger_on_ME4=" << trigger_on_ME4 << "\ntrigger_on_MB1a=" << trigger_on_MB1a
141  << "\ntrigger_on_MB1d=" << trigger_on_MB1d
142 
143  << "\nBXAdepth=" << BXAdepth << "\nuseDT=" << useDT << "\nwidePhi=" << widePhi << "\nPreTrigger=" << PreTrigger
144 
145  << "\nCoreLatency=" << CoreLatency << "\nrescaleSinglesPhi=" << rescaleSinglesPhi
146 
147  << "\n\nVARIOUS CONFIGURATION PARAMETERS DEFAULT VALUES"
148  << "\nAllowALCTonly=" << AllowALCTonly << "\nAllowCLCTonly=" << AllowCLCTonly
149 
150  << "\nQualityEnableME1a=" << QualityEnableME1a << "\nQualityEnableME1b=" << QualityEnableME1b
151  << "\nQualityEnableME1c=" << QualityEnableME1c << "\nQualityEnableME1d=" << QualityEnableME1d
152  << "\nQualityEnableME1e=" << QualityEnableME1e << "\nQualityEnableME1f=" << QualityEnableME1f
153  << "\nQualityEnableME2a=" << QualityEnableME2a << "\nQualityEnableME2b=" << QualityEnableME2b
154  << "\nQualityEnableME2c=" << QualityEnableME2c << "\nQualityEnableME3a=" << QualityEnableME3a
155  << "\nQualityEnableME3b=" << QualityEnableME3b << "\nQualityEnableME3c=" << QualityEnableME3c
156  << "\nQualityEnableME4a=" << QualityEnableME4a << "\nQualityEnableME4b=" << QualityEnableME4b
157  << "\nQualityEnableME4c=" << QualityEnableME4c
158 
159  << "\nkill_fiber=" << kill_fiber << "\nsinglesTrackOutput=" << singlesTrackOutput
160 
161  << "\n\nDEFAULT VALUES FOR DAT_ETA"
162  << "\nmindetap =" << mindetap << "\nmindetap_halo=" << mindetap_halo
163 
164  << "\netamin[0]=" << etamin[0] << "\netamin[1]=" << etamin[1] << "\netamin[2]=" << etamin[2]
165  << "\netamin[3]=" << etamin[3] << "\netamin[4]=" << etamin[4] << "\netamin[5]=" << etamin[5]
166  << "\netamin[6]=" << etamin[6] << "\netamin[7]=" << etamin[7]
167 
168  << "\nmindeta12_accp =" << mindeta12_accp << "\nmindeta13_accp =" << mindeta13_accp
169  << "\nmindeta112_accp=" << mindeta112_accp << "\nmindeta113_accp=" << mindeta113_accp
170 
171  << "\netamax[0]=" << etamax[0] << "\netamax[1]=" << etamax[1] << "\netamax[2]=" << etamax[2]
172  << "\netamax[3]=" << etamax[3] << "\netamax[4]=" << etamax[4] << "\netamax[5]=" << etamax[5]
173  << "\netamax[6]=" << etamax[6] << "\netamax[7]=" << etamax[7]
174 
175  << "\nmaxdeta12_accp =" << maxdeta12_accp << "\nmaxdeta13_accp =" << maxdeta13_accp
176  << "\nmaxdeta112_accp=" << maxdeta112_accp << "\nmaxdeta113_accp=" << maxdeta113_accp
177 
178  << "\netawin[0]=" << etawin[0] << "\netawin[1]=" << etawin[1] << "\netawin[2]=" << etawin[2]
179  << "\netawin[3]=" << etawin[3] << "\netawin[4]=" << etawin[4] << "\netawin[5]=" << etawin[5]
180  << "\netawin[6]=" << etawin[6]
181 
182  << "\nmaxdphi12_accp =" << maxdphi12_accp << "\nmaxdphi13_accp =" << maxdphi13_accp
183  << "\nmaxdphi112_accp=" << maxdphi112_accp << "\nmaxdphi113_accp=" << maxdphi113_accp
184 
185  << "\nmindphip =" << mindphip << "\nmindphip_halo=" << mindphip_halo
186 
187  << "\nstraightp=" << straightp << "\ncurvedp =" << curvedp << "\nmbaPhiOff=" << mbaPhiOff
188  << "\nmbbPhiOff=" << mbbPhiOff
189 
190  << "\n\nFIRMWARE VERSIONS"
191  << "\nSP: " << firmwareSP << "\nFA: " << firmwareFA << "\nDD: " << firmwareDD << "\nVM: " << firmwareVM;
192 
193  // start filling the registers with the values in the DBS
194  std::stringstream conf(registers[sp]);
195  while (!conf.eof()) {
196  char buff[1024];
197  conf.getline(buff, 1024);
198  std::stringstream line(buff);
199  //std::cout<<"buff:"<<buff<<std::endl;
200  std::string register_;
201  line >> register_;
202  std::string chip_;
203  line >> chip_;
204  std::string muon_;
205  line >> muon_;
206  std::string writeValue_;
207  line >> writeValue_;
208  std::string comments_;
209  std::getline(line, comments_);
210 
211  if (register_ == "CSR_REQ" && chip_ == "SP") {
212  unsigned int value = ::strtol(writeValue_.c_str(), nullptr, 16);
213  run_core = (value & 0x8000);
214  trigger_on_ME1a = (value & 0x0001);
215  trigger_on_ME1b = (value & 0x0002);
216  trigger_on_ME2 = (value & 0x0004);
217  trigger_on_ME3 = (value & 0x0008);
218  trigger_on_ME4 = (value & 0x0010);
219  trigger_on_MB1a = (value & 0x0100);
220  trigger_on_MB1d = (value & 0x0200);
221  }
222 
223  if (register_ == "CSR_SCC" && chip_ == "SP") {
224  unsigned int value = ::strtol(writeValue_.c_str(), nullptr, 16);
225 
226  BXAdepth = (value & 0x3);
227  useDT = ((value & 0x80) >> 7);
228  widePhi = ((value & 0x40) >> 6);
229  PreTrigger = ((value & 0x300) >> 8);
230  }
231 
232  if (register_ == "CSR_LQE" && chip_ == "F1" && muon_ == "M1")
233  QualityEnableME1a = ::strtol(writeValue_.c_str(), nullptr, 16);
234  if (register_ == "CSR_LQE" && chip_ == "F1" && muon_ == "M2")
235  QualityEnableME1b = ::strtol(writeValue_.c_str(), nullptr, 16);
236  if (register_ == "CSR_LQE" && chip_ == "F1" && muon_ == "M3")
237  QualityEnableME1c = ::strtol(writeValue_.c_str(), nullptr, 16);
238  if (register_ == "CSR_LQE" && chip_ == "F2" && muon_ == "M1")
239  QualityEnableME1d = ::strtol(writeValue_.c_str(), nullptr, 16);
240  if (register_ == "CSR_LQE" && chip_ == "F2" && muon_ == "M2")
241  QualityEnableME1e = ::strtol(writeValue_.c_str(), nullptr, 16);
242  if (register_ == "CSR_LQE" && chip_ == "F2" && muon_ == "M3")
243  QualityEnableME1f = ::strtol(writeValue_.c_str(), nullptr, 16);
244  if (register_ == "CSR_LQE" && chip_ == "F3" && muon_ == "M1")
245  QualityEnableME2a = ::strtol(writeValue_.c_str(), nullptr, 16);
246  if (register_ == "CSR_LQE" && chip_ == "F3" && muon_ == "M2")
247  QualityEnableME2b = ::strtol(writeValue_.c_str(), nullptr, 16);
248  if (register_ == "CSR_LQE" && chip_ == "F3" && muon_ == "M3")
249  QualityEnableME2c = ::strtol(writeValue_.c_str(), nullptr, 16);
250  if (register_ == "CSR_LQE" && chip_ == "F4" && muon_ == "M1")
251  QualityEnableME3a = ::strtol(writeValue_.c_str(), nullptr, 16);
252  if (register_ == "CSR_LQE" && chip_ == "F4" && muon_ == "M2")
253  QualityEnableME3b = ::strtol(writeValue_.c_str(), nullptr, 16);
254  if (register_ == "CSR_LQE" && chip_ == "F4" && muon_ == "M3")
255  QualityEnableME3c = ::strtol(writeValue_.c_str(), nullptr, 16);
256  if (register_ == "CSR_LQE" && chip_ == "F5" && muon_ == "M1")
257  QualityEnableME4a = ::strtol(writeValue_.c_str(), nullptr, 16);
258  if (register_ == "CSR_LQE" && chip_ == "F5" && muon_ == "M2")
259  QualityEnableME4b = ::strtol(writeValue_.c_str(), nullptr, 16);
260  if (register_ == "CSR_LQE" && chip_ == "F5" && muon_ == "M3")
261  QualityEnableME4c = ::strtol(writeValue_.c_str(), nullptr, 16);
262 
263  if (register_ == "CSR_KFL")
264  kill_fiber = ::strtol(writeValue_.c_str(), nullptr, 16);
265 
266  if (register_ == "CSR_SFC" && chip_ == "SP") {
267  unsigned int value = ::strtol(writeValue_.c_str(), nullptr, 16);
268  singlesTrackOutput = ((value & 0x3000) >> 12);
269  }
270 
271  if (register_ == "CNT_ETA" && chip_ == "SP") {
272  unsigned int value = ::strtol(writeValue_.c_str(), nullptr, 16);
273  eta_cnt = value;
274  }
275 
276  // LATEST VERSION FROM CORE 2010-01-22 at http://www.phys.ufl.edu/~madorsky/sp/2010-01-22
277  if (register_ == "DAT_ETA" && chip_ == "SP") {
278  unsigned int value = ::strtol(writeValue_.c_str(), nullptr, 16);
279 
280  //std::cout<<"DAT_ETA SP value:"<<value<<std::endl;
281 
282  if (eta_cnt == 0)
283  mindetap = value;
284  if (eta_cnt == 1)
285  mindetap_halo = value;
286 
287  if (eta_cnt >= 2 && eta_cnt < 10)
288  etamin[eta_cnt - 2] = value;
289 
290  if (eta_cnt == 10)
291  mindeta12_accp = value;
292  if (eta_cnt == 11)
293  mindeta13_accp = value;
294  if (eta_cnt == 12)
295  mindeta112_accp = value;
296  if (eta_cnt == 13)
297  mindeta113_accp = value;
298 
299  if (eta_cnt >= 14 && eta_cnt < 22)
300  etamax[eta_cnt - 14] = value;
301 
302  if (eta_cnt == 22)
303  maxdeta12_accp = value;
304  if (eta_cnt == 23)
305  maxdeta13_accp = value;
306  if (eta_cnt == 24)
307  maxdeta112_accp = value;
308  if (eta_cnt == 25)
309  maxdeta113_accp = value;
310 
311  if (eta_cnt >= 26 && eta_cnt < 33)
312  etawin[eta_cnt - 26] = value;
313 
314  if (eta_cnt == 33)
315  maxdphi12_accp = value;
316  if (eta_cnt == 34)
317  maxdphi13_accp = value;
318  if (eta_cnt == 35)
319  maxdphi112_accp = value;
320  if (eta_cnt == 36)
321  maxdphi113_accp = value;
322 
323  if (eta_cnt == 37)
324  mindphip = value;
325  if (eta_cnt == 38)
326  mindphip_halo = value;
327 
328  if (eta_cnt == 39)
329  straightp = value;
330  if (eta_cnt == 40)
331  curvedp = value;
332  if (eta_cnt == 41)
333  mbaPhiOff = value;
334  if (eta_cnt == 42)
335  mbbPhiOff = value;
336 
337  eta_cnt++;
338  }
339 
340  // filling the firmware variables: SP MEZZANINE
341  if (register_ == "FIRMWARE" && muon_ == "SP") {
342  unsigned int value = atoi(writeValue_.c_str());
343  firmwareSP = value;
344  }
345 
346  // filling the firmware variables: Front FPGAs
347  if (register_ == "FIRMWARE" && muon_ == "FA") {
348  unsigned int value = atoi(writeValue_.c_str());
349  firmwareFA = value;
350  }
351 
352  // filling the firmware variables: DDU
353  if (register_ == "FIRMWARE" && muon_ == "DD") {
354  unsigned int value = atoi(writeValue_.c_str());
355  firmwareDD = value;
356  }
357 
358  // filling the firmware variables: VM
359  if (register_ == "FIRMWARE" && muon_ == "VM") {
360  unsigned int value = atoi(writeValue_.c_str());
361  firmwareVM = value;
362  }
363  }
364 
365  pset.addParameter<bool>("run_core", run_core);
366  pset.addParameter<bool>("trigger_on_ME1a", trigger_on_ME1a);
367  pset.addParameter<bool>("trigger_on_ME1b", trigger_on_ME1b);
368  pset.addParameter<bool>("trigger_on_ME2", trigger_on_ME2);
369  pset.addParameter<bool>("trigger_on_ME3", trigger_on_ME3);
370  pset.addParameter<bool>("trigger_on_ME4", trigger_on_ME4);
371  pset.addParameter<bool>("trigger_on_MB1a", trigger_on_MB1a);
372  pset.addParameter<bool>("trigger_on_MB1d", trigger_on_MB1d);
373 
374  pset.addParameter<unsigned int>("BXAdepth", BXAdepth);
375  pset.addParameter<unsigned int>("useDT", useDT);
376  pset.addParameter<unsigned int>("widePhi", widePhi);
377  pset.addParameter<unsigned int>("PreTrigger", PreTrigger);
378 
379  // this were two old settings, not used anymore. Set them to zero
380  // ask Alex if he can remove them altogether
381  pset.addParameter<bool>("AllowALCTonly", AllowALCTonly);
382  pset.addParameter<bool>("AllowCLCTonly", AllowCLCTonly);
383 
384  pset.addParameter<int>("CoreLatency", CoreLatency);
385  pset.addParameter<bool>("rescaleSinglesPhi", rescaleSinglesPhi);
386 
387  pset.addParameter<unsigned int>("QualityEnableME1a", QualityEnableME1a);
388  pset.addParameter<unsigned int>("QualityEnableME1b", QualityEnableME1b);
389  pset.addParameter<unsigned int>("QualityEnableME1c", QualityEnableME1c);
390  pset.addParameter<unsigned int>("QualityEnableME1d", QualityEnableME1d);
391  pset.addParameter<unsigned int>("QualityEnableME1e", QualityEnableME1e);
392  pset.addParameter<unsigned int>("QualityEnableME1f", QualityEnableME1f);
393  pset.addParameter<unsigned int>("QualityEnableME2a", QualityEnableME2a);
394  pset.addParameter<unsigned int>("QualityEnableME2b", QualityEnableME2b);
395  pset.addParameter<unsigned int>("QualityEnableME2c", QualityEnableME2c);
396  pset.addParameter<unsigned int>("QualityEnableME3a", QualityEnableME3a);
397  pset.addParameter<unsigned int>("QualityEnableME3b", QualityEnableME3b);
398  pset.addParameter<unsigned int>("QualityEnableME3c", QualityEnableME3c);
399  pset.addParameter<unsigned int>("QualityEnableME4a", QualityEnableME4a);
400  pset.addParameter<unsigned int>("QualityEnableME4b", QualityEnableME4b);
401  pset.addParameter<unsigned int>("QualityEnableME4c", QualityEnableME4c);
402 
403  pset.addParameter<unsigned int>("kill_fiber", kill_fiber);
404  pset.addParameter<unsigned int>("singlesTrackOutput", singlesTrackOutput);
405 
406  // add the DAT_ETA registers to the pset
407  pset.addParameter<unsigned int>("mindetap", mindetap);
408  pset.addParameter<unsigned int>("mindetap_halo", mindetap_halo);
409 
410  pset.addParameter<std::vector<unsigned int> >("EtaMin", etamin);
411 
412  pset.addParameter<unsigned int>("mindeta12_accp", mindeta12_accp);
413  pset.addParameter<unsigned int>("mindeta13_accp", mindeta13_accp);
414  pset.addParameter<unsigned int>("mindeta112_accp", mindeta112_accp);
415  pset.addParameter<unsigned int>("mindeta113_accp", mindeta113_accp);
416 
417  pset.addParameter<std::vector<unsigned int> >("EtaMax", etamax);
418 
419  pset.addParameter<unsigned int>("maxdeta12_accp", maxdeta12_accp);
420  pset.addParameter<unsigned int>("maxdeta13_accp", maxdeta13_accp);
421  pset.addParameter<unsigned int>("maxdeta112_accp", maxdeta112_accp);
422  pset.addParameter<unsigned int>("maxdeta113_accp", maxdeta113_accp);
423 
424  pset.addParameter<std::vector<unsigned int> >("EtaWindows", etawin);
425 
426  pset.addParameter<unsigned int>("maxdphi12_accp", maxdphi12_accp);
427  pset.addParameter<unsigned int>("maxdphi13_accp", maxdphi13_accp);
428  pset.addParameter<unsigned int>("maxdphi112_accp", maxdphi112_accp);
429  pset.addParameter<unsigned int>("maxdphi113_accp", maxdphi113_accp);
430 
431  pset.addParameter<unsigned int>("mindphip", mindphip);
432  pset.addParameter<unsigned int>("mindphip_halo", mindphip_halo);
433 
434  pset.addParameter<unsigned int>("straightp", straightp);
435  pset.addParameter<unsigned int>("curvedp", curvedp);
436  pset.addParameter<unsigned int>("mbaPhiOff", mbaPhiOff);
437  pset.addParameter<unsigned int>("mbbPhiOff", mbbPhiOff);
438 
439  pset.addParameter<unsigned int>("firmwareSP", firmwareSP);
440  pset.addParameter<unsigned int>("firmwareFA", firmwareFA);
441  pset.addParameter<unsigned int>("firmwareDD", firmwareDD);
442  pset.addParameter<unsigned int>("firmwareVM", firmwareVM);
443 
444  // printout
445  LogDebug("L1MuCSCTFConfiguration")
446  << "\nCORE CONFIGURATION AFTER READING THE DBS VALUES"
447  << "\nrun_core=" << run_core << "\ntrigger_on_ME1a=" << trigger_on_ME1a << "\ntrigger_on_ME1b=" << trigger_on_ME1b
448  << "\ntrigger_on_ME2=" << trigger_on_ME2 << "\ntrigger_on_ME3=" << trigger_on_ME3
449  << "\ntrigger_on_ME4=" << trigger_on_ME4 << "\ntrigger_on_MB1a=" << trigger_on_MB1a
450  << "\ntrigger_on_MB1d=" << trigger_on_MB1d
451 
452  << "\nBXAdepth=" << BXAdepth << "\nuseDT=" << useDT << "\nwidePhi=" << widePhi << "\nPreTrigger=" << PreTrigger
453 
454  << "\nCoreLatency=" << CoreLatency << "\nrescaleSinglesPhi=" << rescaleSinglesPhi
455 
456  << "\n\nVARIOUS CONFIGURATION PARAMETERS AFTER READING THE DBS VALUES"
457  << "\nAllowALCTonly=" << AllowALCTonly << "\nAllowCLCTonly=" << AllowCLCTonly
458 
459  << "\nQualityEnableME1a=" << QualityEnableME1a << "\nQualityEnableME1b=" << QualityEnableME1b
460  << "\nQualityEnableME1c=" << QualityEnableME1c << "\nQualityEnableME1d=" << QualityEnableME1d
461  << "\nQualityEnableME1e=" << QualityEnableME1e << "\nQualityEnableME1f=" << QualityEnableME1f
462  << "\nQualityEnableME2a=" << QualityEnableME2a << "\nQualityEnableME2b=" << QualityEnableME2b
463  << "\nQualityEnableME2c=" << QualityEnableME2c << "\nQualityEnableME3a=" << QualityEnableME3a
464  << "\nQualityEnableME3b=" << QualityEnableME3b << "\nQualityEnableME3c=" << QualityEnableME3c
465  << "\nQualityEnableME4a=" << QualityEnableME4a << "\nQualityEnableME4b=" << QualityEnableME4b
466  << "\nQualityEnableME4c=" << QualityEnableME4c
467 
468  << "\nkill_fiber=" << kill_fiber << "\nsinglesTrackOutput=" << singlesTrackOutput
469 
470  << "\n\nDAT_ETA AFTER READING THE DBS VALUES"
471  << "\nmindetap =" << mindetap << "\nmindetap_halo=" << mindetap_halo
472 
473  << "\netamin[0]=" << etamin[0] << "\netamin[1]=" << etamin[1] << "\netamin[2]=" << etamin[2]
474  << "\netamin[3]=" << etamin[3] << "\netamin[4]=" << etamin[4] << "\netamin[5]=" << etamin[5]
475  << "\netamin[6]=" << etamin[6] << "\netamin[7]=" << etamin[7]
476 
477  << "\nmindeta12_accp =" << mindeta12_accp << "\nmindeta13_accp =" << mindeta13_accp
478  << "\nmindeta112_accp=" << mindeta112_accp << "\nmindeta113_accp=" << mindeta113_accp
479 
480  << "\netamax[0]=" << etamax[0] << "\netamax[1]=" << etamax[1] << "\netamax[2]=" << etamax[2]
481  << "\netamax[3]=" << etamax[3] << "\netamax[4]=" << etamax[4] << "\netamax[5]=" << etamax[5]
482  << "\netamax[6]=" << etamax[6] << "\netamax[7]=" << etamax[7]
483 
484  << "\nmaxdeta12_accp =" << maxdeta12_accp << "\nmaxdeta13_accp =" << maxdeta13_accp
485  << "\nmaxdeta112_accp=" << maxdeta112_accp << "\nmaxdeta113_accp=" << maxdeta113_accp
486 
487  << "\netawin[0]=" << etawin[0] << "\netawin[1]=" << etawin[1] << "\netawin[2]=" << etawin[2]
488  << "\netawin[3]=" << etawin[3] << "\netawin[4]=" << etawin[4] << "\netawin[5]=" << etawin[5]
489  << "\netawin[6]=" << etawin[6]
490 
491  << "\nmaxdphi12_accp =" << maxdphi12_accp << "\nmaxdphi13_accp =" << maxdphi13_accp
492  << "\nmaxdphi112_accp=" << maxdphi112_accp << "\nmaxdphi113_accp=" << maxdphi113_accp
493 
494  << "\nmindphip =" << mindphip << "\nmindphip_halo=" << mindphip_halo
495 
496  << "\nstraightp=" << straightp << "\ncurvedp =" << curvedp << "\nmbaPhiOff=" << mbaPhiOff
497  << "\nmbbPhiOff=" << mbbPhiOff
498 
499  << "\n\nFIRMWARE VERSIONS AFTER READING THE DBS VALUES"
500  << "\nSP: " << firmwareSP << "\nFA: " << firmwareFA << "\nDD: " << firmwareDD << "\nVM: " << firmwareVM;
501 
502  // ---------------------------------------------------------
503 
504  return pset;
505 }
506 
507 void L1MuCSCTFConfiguration::print(std::ostream& myStr) const {
508  myStr << "\nL1 Mu CSCTF Parameters \n" << std::endl;
509 
510  for (int iSP = 0; iSP < 12; iSP++) {
511  myStr << "=============================================" << std::endl;
512  myStr << "Printing out Global Tag Content for SP " << iSP + 1 << std::endl;
513  myStr << registers[iSP];
514  myStr << "=============================================" << std::endl;
515  }
516 }
LogDebug
#define LogDebug(id)
Definition: MessageLogger.h:670
csctfTrackDigis_cfi.maxdeta13_accp
maxdeta13_accp
Definition: csctfTrackDigis_cfi.py:71
csctfTrackDigis_cfi.BXAdepth
BXAdepth
Definition: csctfTrackDigis_cfi.py:52
csctfTrackDigis_cfi.trigger_on_ME1a
trigger_on_ME1a
Definition: csctfTrackDigis_cfi.py:43
csctfTrackDigis_cfi.trigger_on_MB1a
trigger_on_MB1a
Definition: csctfTrackDigis_cfi.py:41
csctfTrackDigis_cfi.QualityEnableME4b
QualityEnableME4b
Definition: csctfTrackDigis_cfi.py:105
csctfTrackDigis_cfi.useDT
useDT
Definition: csctfTrackDigis_cfi.py:122
csctfTrackDigis_cfi.QualityEnableME1f
QualityEnableME1f
Definition: csctfTrackDigis_cfi.py:97
csctfTrackDigis_cfi.QualityEnableME3a
QualityEnableME3a
Definition: csctfTrackDigis_cfi.py:101
csctfTrackDigis_cfi.run_core
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Definition: csctfTrackDigis_cfi.py:40
csctfTrackDigis_cfi.singlesTrackOutput
singlesTrackOutput
Definition: csctfTrackDigis_cfi.py:48
csctfTrackDigis_cfi.QualityEnableME2a
QualityEnableME2a
Definition: csctfTrackDigis_cfi.py:98
csctfTrackDigis_cfi.QualityEnableME3c
QualityEnableME3c
Definition: csctfTrackDigis_cfi.py:103
csctfTrackDigis_cfi.firmwareSP
firmwareSP
Definition: csctfTrackDigis_cfi.py:108
csctfTrackDigis_cfi.mindphip
mindphip
Definition: csctfTrackDigis_cfi.py:82
csctfTrackDigis_cfi.trigger_on_ME4
trigger_on_ME4
Definition: csctfTrackDigis_cfi.py:47
csctfTrackDigis_cfi.mindeta12_accp
mindeta12_accp
Definition: csctfTrackDigis_cfi.py:63
csctfTrackDigis_cfi.mbbPhiOff
mbbPhiOff
Definition: csctfTrackDigis_cfi.py:89
csctfTrackDigis_cfi.mindetap
mindetap
Definition: csctfTrackDigis_cfi.py:58
csctfTrackDigis_cfi.CoreLatency
CoreLatency
Definition: csctfTrackDigis_cfi.py:50
csctfTrackDigis_cfi.mindeta113_accp
mindeta113_accp
Definition: csctfTrackDigis_cfi.py:66
csctfTrackDigis_cfi.mindetap_halo
mindetap_halo
Definition: csctfTrackDigis_cfi.py:59
AlCaHLTBitMon_QueryRunRegistry.string
string
Definition: AlCaHLTBitMon_QueryRunRegistry.py:256
csctfTrackDigis_cfi.widePhi
widePhi
Definition: csctfTrackDigis_cfi.py:53
L1MuCSCTFConfiguration::parameters
edm::ParameterSet parameters(int sp) const
Definition: L1MuCSCTFConfiguration.cc:7
muonDTDigis_cfi.pset
pset
Definition: muonDTDigis_cfi.py:27
csctfTrackDigis_cfi.mindphip_halo
mindphip_halo
Definition: csctfTrackDigis_cfi.py:83
muonTiming_cfi.etamin
etamin
Definition: muonTiming_cfi.py:30
csctfTrackDigis_cfi.kill_fiber
kill_fiber
Definition: csctfTrackDigis_cfi.py:91
csctfTrackDigis_cfi.QualityEnableME1d
QualityEnableME1d
Definition: csctfTrackDigis_cfi.py:95
csctfTrackDigis_cfi.curvedp
curvedp
Definition: csctfTrackDigis_cfi.py:86
csctfTrackDigis_cfi.trigger_on_ME1b
trigger_on_ME1b
Definition: csctfTrackDigis_cfi.py:44
csctfTrackDigis_cfi.rescaleSinglesPhi
rescaleSinglesPhi
Definition: csctfTrackDigis_cfi.py:39
csctfTrackDigis_cfi.mindeta13_accp
mindeta13_accp
Definition: csctfTrackDigis_cfi.py:64
csctfTrackDigis_cfi.maxdphi13_accp
maxdphi13_accp
Definition: csctfTrackDigis_cfi.py:78
L1MuCSCTFConfiguration::print
void print(std::ostream &) const
print all the L1 CSCTF Configuration Parameters
Definition: L1MuCSCTFConfiguration.cc:507
csctfTrackDigis_cfi.QualityEnableME1a
QualityEnableME1a
Definition: csctfTrackDigis_cfi.py:92
csctfTrackDigis_cfi.AllowALCTonly
AllowALCTonly
Definition: csctfTrackDigis_cfi.py:37
edm::ParameterSet::addParameter
void addParameter(std::string const &name, T const &value)
Definition: ParameterSet.h:124
csctfTrackDigis_cfi.mindeta112_accp
mindeta112_accp
Definition: csctfTrackDigis_cfi.py:65
csctfTrackDigis_cfi.straightp
straightp
Definition: csctfTrackDigis_cfi.py:85
mps_splice.line
line
Definition: mps_splice.py:76
csctfTrackDigis_cfi.AllowCLCTonly
AllowCLCTonly
Definition: csctfTrackDigis_cfi.py:38
csctfTrackDigis_cfi.maxdphi12_accp
maxdphi12_accp
Definition: csctfTrackDigis_cfi.py:77
csctfTrackDigis_cfi.QualityEnableME4a
QualityEnableME4a
Definition: csctfTrackDigis_cfi.py:104
csctfTrackDigis_cfi.maxdphi113_accp
maxdphi113_accp
Definition: csctfTrackDigis_cfi.py:80
csctfTrackDigis_cfi.QualityEnableME1e
QualityEnableME1e
Definition: csctfTrackDigis_cfi.py:96
value
Definition: value.py:1
csctfTrackDigis_cfi.QualityEnableME3b
QualityEnableME3b
Definition: csctfTrackDigis_cfi.py:102
csctfTrackDigis_cfi.maxdeta112_accp
maxdeta112_accp
Definition: csctfTrackDigis_cfi.py:72
csctfTrackDigis_cfi.QualityEnableME2b
QualityEnableME2b
Definition: csctfTrackDigis_cfi.py:99
muonTiming_cfi.etamax
etamax
Definition: muonTiming_cfi.py:23
csctfTrackDigis_cfi.firmwareVM
firmwareVM
Definition: csctfTrackDigis_cfi.py:111
csctfTrackDigis_cfi.mbaPhiOff
mbaPhiOff
Definition: csctfTrackDigis_cfi.py:88
csctfTrackDigis_cfi.maxdphi112_accp
maxdphi112_accp
Definition: csctfTrackDigis_cfi.py:79
csctfTrackDigis_cfi.maxdeta113_accp
maxdeta113_accp
Definition: csctfTrackDigis_cfi.py:73
csctfTrackDigis_cfi.trigger_on_MB1d
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Definition: csctfTrackDigis_cfi.py:42
csctfTrackDigis_cfi.firmwareDD
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Definition: csctfTrackDigis_cfi.py:110
csctfTrackDigis_cfi.QualityEnableME4c
QualityEnableME4c
Definition: csctfTrackDigis_cfi.py:106
csctfTrackDigis_cfi.trigger_on_ME2
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Definition: csctfTrackDigis_cfi.py:45
csctfTrackDigis_cfi.QualityEnableME1b
QualityEnableME1b
Definition: csctfTrackDigis_cfi.py:93
csctfTrackDigis_cfi.trigger_on_ME3
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Definition: csctfTrackDigis_cfi.py:46
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csctfTrackDigis_cfi.firmwareFA
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Definition: csctfTrackDigis_cfi.py:109
csctfTrackDigis_cfi.PreTrigger
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Definition: csctfTrackDigis_cfi.py:51
csctfTrackDigis_cfi.QualityEnableME1c
QualityEnableME1c
Definition: csctfTrackDigis_cfi.py:94
csctfTrackDigis_cfi.QualityEnableME2c
QualityEnableME2c
Definition: csctfTrackDigis_cfi.py:100
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