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L1GtHwValidation.cc
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1 
16 // this class header
17 #include "DQM/L1TMonitor/interface/L1GtHwValidation.h"
18 
19 // system include files
20 #include <memory>
21 #include <iostream>
22 #include <iomanip>
23 
24 // user include files
25 #include "DataFormats/L1GlobalTrigger/interface/L1GlobalTriggerReadoutSetup.h"
26 #include "DataFormats/L1GlobalTrigger/interface/L1GlobalTriggerReadoutRecord.h"
27 #include "DataFormats/L1GlobalTrigger/interface/L1GlobalTriggerEvmReadoutRecord.h"
28 
29 #include "FWCore/MessageLogger/interface/MessageLogger.h"
30 #include "FWCore/ServiceRegistry/interface/Service.h"
31 
32 #include "FWCore/Framework/interface/EventSetup.h"
33 #include "FWCore/Framework/interface/ESHandle.h"
34 #include "FWCore/Framework/interface/Run.h"
35 
36 #include "CondFormats/L1TObjects/interface/L1GtTriggerMenu.h"
37 #include "CondFormats/DataRecord/interface/L1GtTriggerMenuRcd.h"
38 
39 #include "CondFormats/L1TObjects/interface/L1GtPrescaleFactors.h"
40 #include "CondFormats/DataRecord/interface/L1GtPrescaleFactorsAlgoTrigRcd.h"
41 #include "CondFormats/DataRecord/interface/L1GtPrescaleFactorsTechTrigRcd.h"
42 
43 #include "CondFormats/L1TObjects/interface/L1GtTriggerMask.h"
44 #include "CondFormats/DataRecord/interface/L1GtTriggerMaskAlgoTrigRcd.h"
45 #include "CondFormats/DataRecord/interface/L1GtTriggerMaskTechTrigRcd.h"
46 
47 #include "TH1.h"
48 #include "TH2.h"
49 #include "TTree.h"
50 
51 // constructor(s)
52 L1GtHwValidation::L1GtHwValidation(const edm::ParameterSet& paramSet) :
53  //
54  // input tag for the L1 GT hardware DAQ record
55  m_l1GtDataDaqInputTag(paramSet.getParameter<edm::InputTag>(
56  "L1GtDataDaqInputTag")),
57  // input tag for the L1 GT hardware EVM record
58  m_l1GtDataEvmInputTag(paramSet.getParameter<edm::InputTag>(
59  "L1GtDataEvmInputTag")),
60  // input tag for the L1 GT emulator DAQ record
61  m_l1GtEmulDaqInputTag(paramSet.getParameter<edm::InputTag>(
62  "L1GtEmulDaqInputTag")),
63  // input tag for the L1 GT emulator EVM record
64  m_l1GtEmulEvmInputTag(paramSet.getParameter<edm::InputTag>(
65  "L1GtEmulEvmInputTag")),
66  // input tag for the L1 GCT hardware record
67  m_l1GctDataInputTag(paramSet.getParameter<edm::InputTag>(
68  "L1GctDataInputTag")),
69  //
70  m_dirName(paramSet.getUntrackedParameter("DirName", std::string(
71  "L1TEMU/GTexpert"))),
72  //
73  m_excludeCondCategTypeObject(paramSet.getParameter<std::vector<edm::ParameterSet> >(
74  "ExcludeCondCategTypeObject")),
75  //
76  m_excludeAlgoTrigByName(paramSet.getParameter<std::vector<std::string> >(
77  "ExcludeAlgoTrigByName")),
78  //
79  m_excludeAlgoTrigByBit(paramSet.getParameter<std::vector<int> >(
80  "ExcludeAlgoTrigByBit")),
81  //
82  // initialize counters
83  m_nrDataEventError(0),
84  m_nrEmulEventError(0),
85  // cache
86  m_l1GtMenuCacheID(0ULL), m_l1GtPfAlgoCacheID(0ULL),
87  m_l1GtPfTechCacheID(0ULL), m_l1GtTmAlgoCacheID(0ULL),
88  m_l1GtTmTechCacheID(0ULL),
89  //
90  m_agree(true),
91  m_dataOnly(false),
92  m_emulOnly(false),
93  m_dataOnlyMask(false),
94  m_emulOnlyMask(false),
95  //
96  m_nrEvJob(0), m_nrEvRun(0) {
97 
98 
99  for (std::vector<edm::ParameterSet>::const_iterator
100  itExclud = m_excludeCondCategTypeObject.begin();
101  itExclud != m_excludeCondCategTypeObject.end();
102  ++itExclud) {
103 
104  if (!(itExclud->getParameter<std::string> ("ExcludedCondCategory")).empty()) {
105 
106  m_excludedCondCategory.push_back(l1GtConditionCategoryStringToEnum(
107  itExclud->getParameter<std::string>("ExcludedCondCategory")));
108 
109  } else {
110  m_excludedCondCategory.push_back(CondNull);
111  }
112 
113  if (!(itExclud->getParameter<std::string>("ExcludedCondType")).empty() ) {
114 
115  m_excludedCondType.push_back(l1GtConditionTypeStringToEnum(
116  itExclud->getParameter<std::string> ("ExcludedCondType")));
117 
118  } else {
119  m_excludedCondType.push_back(TypeNull);
120  }
121 
122  if (!(itExclud->getParameter<std::string>("ExcludedL1GtObject")).empty() ) {
123 
124  m_excludedL1GtObject.push_back(l1GtObjectStringToEnum(
125  itExclud->getParameter<std::string> ("ExcludedL1GtObject")));
126 
127  } else {
128  m_excludedL1GtObject.push_back(ObjNull);
129  }
130  }
131 
132 
133  LogDebug("L1GtHwValidation")
134  << "\nInput tag for the L1 GT DAQ hardware record: "
135  << m_l1GtDataDaqInputTag
136  << "\nInput tag for the L1 GT EVM hardware record: "
137  << m_l1GtDataEvmInputTag
138  << "\nInput tag for the L1 GT DAQ emulator records: "
139  << m_l1GtEmulDaqInputTag
140  << "\nInput tag for the L1 GT EVM emulator records: "
141  << m_l1GtEmulEvmInputTag
142  << "\nInput tag for the L1 GCT hardware record: "
143  << m_l1GctDataInputTag << std::endl;
144 
145  // FIXME print in debug mode ExcludeCondCategTypeObject, ExcludeAlgoTrigByName, etc
146 
147  //set Token(-s)
148  m_l1GtDataDaqInputToken_ = consumes<L1GlobalTriggerReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtDataDaqInputTag"));
149  m_l1GtEmulDaqInputToken_ = consumes<L1GlobalTriggerReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtEmulDaqInputTag"));
150  m_l1GtDataEvmInputToken_ = consumes<L1GlobalTriggerEvmReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtDataEvmInputTag"));
151  m_l1GtEmulEvmInputToken_ = consumes<L1GlobalTriggerEvmReadoutRecord>(paramSet.getParameter<edm::InputTag>("L1GtEmulEvmInputTag"));
152 }
153 
154 // destructor
155 L1GtHwValidation::~L1GtHwValidation() {
156  // empty
157 }
158 
159 // member functions
160 
161 void L1GtHwValidation::dqmBeginRun(const edm::Run& iRun, const edm::EventSetup& evSetup){
162 }
163 
164 
165 void L1GtHwValidation::bookHistograms(DQMStore::IBooker &ibooker, const edm::Run& iRun, const edm::EventSetup& evSetup) {
166 
167  ibooker.setCurrentFolder(m_dirName);
168 
169  // histograms
170 
171  const unsigned int numberTechTriggers = L1GlobalTriggerReadoutSetup::NumberTechnicalTriggers;
172 
173  const unsigned int numberAlgoTriggers = L1GlobalTriggerReadoutSetup::NumberPhysTriggers;
174 
175  for (int iRec = 0; iRec < NumberOfGtRecords; ++iRec) {
176 
177  std::string recString;
178  if (iRec == 0) {
179  recString = "Daq_";
180  ibooker.setCurrentFolder(m_dirName + "/DAQ/");
181 
182  } else {
183  recString = "Evm_";
184  ibooker.setCurrentFolder(m_dirName + "/EVM/");
185  }
186 
187  std::string hName;
188  const char* histName;
189 
190  hName = recString + "gtfeDataEmul";
191  histName = hName.c_str();
192 
193  // GTFE histograms
194  m_gtfeDataEmul[iRec] = ibooker.book1D(histName, "GTFE data vs emul mismatch", 8, 0., 7.);
195  m_gtfeDataEmul[iRec]->setBinLabel(1, "BoardId", 1);
196  m_gtfeDataEmul[iRec]->setBinLabel(2, "RecordLength1", 1);
197  m_gtfeDataEmul[iRec]->setBinLabel(3, "RecordLength0", 1);
198  m_gtfeDataEmul[iRec]->setBinLabel(4, "BxNr", 1);
199  m_gtfeDataEmul[iRec]->setBinLabel(5, "SetupVersion", 1);
200  m_gtfeDataEmul[iRec]->setBinLabel(6, "DaqActiveBoards", 1);
201  m_gtfeDataEmul[iRec]->setBinLabel(7, "AltNrBxBoard", 1);
202  m_gtfeDataEmul[iRec]->setBinLabel(8, "TotalTriggerNr", 1);
203 
204  // FDL histograms
205 
206  for (int iHist = 0; iHist < TotalBxInEvent; ++iHist) {
207 
208  // convert [0, TotalBxInEvent] to [-X, +X] and add to histogram name
209  int iIndex = iHist - ((TotalBxInEvent + 1) / 2 - 1);
210  int hIndex = (iIndex + 16) % 16;
211 
212  std::stringstream ss;
213  std::string str;
214  ss << std::uppercase << std::hex << hIndex;
215  ss >> str;
216 
217  if (iRec == 0) {
218  ibooker.setCurrentFolder(m_dirName + "/DAQ/BxInEvent_" + str);
219 
220  } else {
221  ibooker.setCurrentFolder(m_dirName + "/EVM/BxInEvent_" + str);
222  }
223 
224  hName = recString + "FdlDataEmul_" + str;
225  histName = hName.c_str();
226 
227  std::string hTitle = "FDL data vs emul mismatch for BxInEvent = " + str;
228  const char* histTitle = hTitle.c_str();
229 
230  //
231 
232  m_fdlDataEmul[iHist][iRec] = ibooker.book1D(histName, histTitle, 13, 0., 13.);
233  m_fdlDataEmul[iHist][iRec]->setBinLabel(1, "BoardId", 1);
234  m_fdlDataEmul[iHist][iRec]->setBinLabel(2, "BxInEvent", 1);
235  m_fdlDataEmul[iHist][iRec]->setBinLabel(3, "BxNr", 1);
236  m_fdlDataEmul[iHist][iRec]->setBinLabel(4, "EventNr", 1);
237  m_fdlDataEmul[iHist][iRec]->setBinLabel(5, "TechTrigger", 1);
238  m_fdlDataEmul[iHist][iRec]->setBinLabel(6, "TechTriggerMask", 1);
239  m_fdlDataEmul[iHist][iRec]->setBinLabel(7, "AlgoTrigger", 1);
240  m_fdlDataEmul[iHist][iRec]->setBinLabel(8, "AlgoTriggerMask", 1);
241  m_fdlDataEmul[iHist][iRec]->setBinLabel(9, "AlgoExtend", 1);
242  m_fdlDataEmul[iHist][iRec]->setBinLabel(10, "NoAlgo", 1);
243  m_fdlDataEmul[iHist][iRec]->setBinLabel(11, "FinalORAllParts", 1);
244  m_fdlDataEmul[iHist][iRec]->setBinLabel(12, "FinalORPhysPart", 1);
245  m_fdlDataEmul[iHist][iRec]->setBinLabel(13, "LocalBxNr", 1);
246 
247  // algorithm decision
248  // data
249  hName = recString + "Data_AlgoDecision_" + str;
250  histName = hName.c_str();
251 
252  hTitle = "Data: algorithm decision word for BxInEvent = " + str;
253  histTitle = hTitle.c_str();
254 
255  m_fdlDataAlgoDecision[iHist][iRec] = ibooker.book1D(histName,histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
256 
257  // emul
258  hName = recString + "Emul_AlgoDecision_" + str;
259  histName = hName.c_str();
260 
261  hTitle = "Emul: algorithm decision word for BxInEvent = " + str;
262  histTitle = hTitle.c_str();
263 
264  m_fdlEmulAlgoDecision[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
265 
266  // algorithm decision for prescaled algorithms
267  // data
268  hName = recString + "Data_AlgoDecision_Prescaled_" + str;
269  histName = hName.c_str();
270 
271  hTitle = "Data: prescaled algorithms: algorithm decision for BxInEvent = " + str;
272  histTitle = hTitle.c_str();
273 
274  m_fdlDataAlgoDecisionPrescaled[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
275 
276  // emul
277  hName = recString + "Emul_AlgoDecision_Prescaled_" + str;
278  histName = hName.c_str();
279 
280  hTitle
281  = "Emul: prescaled algorithms: algorithm decision for BxInEvent = "
282  + str;
283  histTitle = hTitle.c_str();
284 
285  m_fdlEmulAlgoDecisionPrescaled[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0.,numberAlgoTriggers);
286 
287  // algorithm decision for unprescaled algorithms
288  // data
289  hName = recString + "Data_AlgoDecision_Unprescaled_" + str;
290  histName = hName.c_str();
291 
292  hTitle
293  = "Data: unprescaled algorithms: algorithm decision for BxInEvent = "
294  + str;
295  histTitle = hTitle.c_str();
296 
297  m_fdlDataAlgoDecisionUnprescaled[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
298 
299  // emul
300  hName = recString + "Emul_AlgoDecision_Unprescaled_" + str;
301  histName = hName.c_str();
302 
303  hTitle = "Emul: unprescaled algorithms: algorithm decision for BxInEvent = " + str;
304  histTitle = hTitle.c_str();
305 
306  m_fdlEmulAlgoDecisionUnprescaled[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
307 
308  // algorithm decision after masking (partition physics)
309  // data
310  hName = recString + "Data_AlgoDecisionAfterMask_" + str;
311  histName = hName.c_str();
312 
313  hTitle = "Data, physics partition: algorithm decision word after mask for BxInEvent = " + str;
314  histTitle = hTitle.c_str();
315 
316  m_fdlDataAlgoDecisionMask[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
317 
318  // emul
319  hName = recString + "Emul_AlgoDecisionAfterMask_" + str;
320  histName = hName.c_str();
321 
322  hTitle = "Emul, physics partition: algorithm decision word after mask for BxInEvent = " + str;
323  histTitle = hTitle.c_str();
324 
325  m_fdlEmulAlgoDecisionMask[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
326 
327  //
328  hName = recString + "DataEmul_AlgoDecision_" + str;
329  histName = hName.c_str();
330 
331  hTitle = "Data vs emul: non-matching algorithm decision word for BxInEvent = " + str;
332  histTitle = hTitle.c_str();
333 
334  m_fdlDataEmulAlgoDecision[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
335 
336  //
337  hName = recString + "DataEmul_AlgoDecision_Prescaled_" + str;
338  histName = hName.c_str();
339 
340  hTitle = "Data vs emul: prescaled algorithms with non-matching decision for BxInEvent = " + str;
341  histTitle = hTitle.c_str();
342 
343  m_fdlDataEmulAlgoDecisionPrescaled[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
344 
345  //
346  hName = recString + "DataEmul_AlgoDecision_Unprescaled_" + str;
347  histName = hName.c_str();
348 
349  hTitle = "Data vs emul: unprescaled algorithms with non-matching decision for BxInEvent = " + str;
350  histTitle = hTitle.c_str();
351 
352  m_fdlDataEmulAlgoDecisionUnprescaled[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
353 
354  //
355  hName = recString + "DataEmul_AlgoDecision_Unprescaled_Allowed_" + str;
356  histName = hName.c_str();
357 
358  hTitle = "Data vs emul: unprescaled algorithms not excluded with non-matching decision for BxInEvent = " + str;
359  histTitle = hTitle.c_str();
360 
361  m_fdlDataEmulAlgoDecisionUnprescaledAllowed[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
362 
363  //
364  hName = recString + "Data_AlgoDecision_NoMatch_" + str;
365  histName = hName.c_str();
366 
367  hTitle = "Data: algorithm decision for non-matching cases for BxInEvent = " + str;
368  histTitle = hTitle.c_str();
369 
370  m_fdlDataAlgoDecision_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
371 
372  //
373  hName = recString + "Emul_AlgoDecision_NoMatch_" + str;
374  histName = hName.c_str();
375 
376  hTitle
377  = "Emul: algorithm decision for non-matching cases for BxInEvent = "
378  + str;
379  histTitle = hTitle.c_str();
380 
381  m_fdlEmulAlgoDecision_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
382 
383  // prescaled algorithms
384  hName = recString + "Data_AlgoDecision_Prescaled_NoMatch_" + str;
385  histName = hName.c_str();
386 
387  hTitle = "Data: prescaled algorithms: non-matching algorithm decision for BxInEvent = " + str;
388  histTitle = hTitle.c_str();
389 
390  m_fdlDataAlgoDecisionPrescaled_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
391 
392  //
393  hName = recString + "Emul_AlgoDecision_Prescaled_NoMatch_" + str;
394  histName = hName.c_str();
395 
396  hTitle = "Emul: prescaled algorithms: non-matching algorithm decision for BxInEvent = " + str;
397  histTitle = hTitle.c_str();
398 
399  m_fdlEmulAlgoDecisionPrescaled_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
400 
401 
402  // unprescaled algorithms - non-matching
403  hName = recString + "Data_AlgoDecision_Unprescaled_NoMatch_" + str;
404  histName = hName.c_str();
405 
406  hTitle = "Data: unprescaled algorithms: non-matching algorithm decision for BxInEvent = " + str;
407  histTitle = hTitle.c_str();
408 
409  m_fdlDataAlgoDecisionUnprescaled_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
410 
411  //
412  hName = recString + "Emul_AlgoDecision_Unprescaled_NoMatch_" + str;
413  histName = hName.c_str();
414 
415  hTitle = "Emul: unprescaled algorithms: non-matching algorithm decision for BxInEvent = " + str;
416  histTitle = hTitle.c_str();
417 
418  m_fdlEmulAlgoDecisionUnprescaled_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
419 
420 
421 
422  //
423  hName = recString + "Data_AlgoDecisionMask_NoMatch_" + str;
424  histName = hName.c_str();
425 
426  hTitle = "Data: algorithm decision for non-matching cases after mask for BxInEvent = " + str;
427  histTitle = hTitle.c_str();
428 
429  m_fdlDataAlgoDecisionMask_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
430 
431  //
432  hName = recString + "Emul_AlgoDecisionMask_NoMatch_" + str;
433  histName = hName.c_str();
434 
435  hTitle = "Emul: algorithm decision for non-matching cases after mask for BxInEvent = " + str;
436  histTitle = hTitle.c_str();
437 
438  m_fdlEmulAlgoDecisionMask_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
439 
440  // prescaled algorithms
441  hName = recString + "Data_AlgoDecisionMask_Prescaled_NoMatch_" + str;
442  histName = hName.c_str();
443 
444  hTitle = "Data: prescaled algorithms: non-matching algorithm decision after mask for BxInEvent = " + str;
445  histTitle = hTitle.c_str();
446 
447  m_fdlDataAlgoDecisionPrescaledMask_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
448 
449  //
450  hName = recString + "Emul_AlgoDecision_PrescaledMask_NoMatch_" + str;
451  histName = hName.c_str();
452 
453  hTitle = "Emul: prescaled algorithms: non-matching algorithm decision after mask for BxInEvent = " + str;
454  histTitle = hTitle.c_str();
455 
456  m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
457 
458 
459  // unprescaled algorithms - non-matching
460  hName = recString + "Data_AlgoDecision_UnprescaledMask_NoMatch_" + str;
461  histName = hName.c_str();
462 
463  hTitle = "Data: unprescaled algorithms: non-matching algorithm decision after mask for BxInEvent = " + str;
464  histTitle = hTitle.c_str();
465 
466  m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
467 
468  //
469  hName = recString + "Emul_AlgoDecision_UnprescaledMask_NoMatch_" + str;
470  histName = hName.c_str();
471 
472  hTitle
473  = "Emul: unprescaled algorithms: non-matching algorithm decision after mask for BxInEvent = "
474  + str;
475  histTitle = hTitle.c_str();
476 
477  m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
478 
479 
480 
481  //
482  hName = recString + "DataEmul_AlgoDecisionAfterMask_" + str;
483  histName = hName.c_str();
484 
485  hTitle = "Data vs emul, physics partition: non-matching algorithm decision word after mask for BxInEvent = " + str;
486  histTitle = hTitle.c_str();
487 
488  m_fdlDataEmulAlgoDecisionMask[iHist][iRec] = ibooker.book1D(histName, histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
489 
490  // technical trigger decision
491  // data
492  hName = recString + "Data_TechDecision_" + str;
493  histName = hName.c_str();
494 
495  hTitle = "Data technical trigger decision word for BxInEvent = " + str;
496  histTitle = hTitle.c_str();
497 
498  m_fdlDataTechDecision[iHist][iRec] = ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
499 
500  // emul
501  hName = recString + "Emul_TechDecision_" + str;
502  histName = hName.c_str();
503 
504  hTitle = "Emul: technical trigger decision word for BxInEvent = " + str;
505  histTitle = hTitle.c_str();
506 
507  m_fdlEmulTechDecision[iHist][iRec] = ibooker.book1D(histName,histTitle, numberTechTriggers, 0., numberTechTriggers);
508 
509  // technical trigger decision after masking (partition physics)
510  hName = recString + "Data_TechDecisionAfterMask_" + str;
511  histName = hName.c_str();
512 
513  hTitle = "Data technical trigger decision word after mask for BxInEvent = " + str;
514  histTitle = hTitle.c_str();
515 
516  m_fdlDataTechDecisionMask[iHist][iRec] = ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
517 
518  //
519  hName = recString + "Emul_TechDecisionAfterMask_" + str;
520  histName = hName.c_str();
521 
522  hTitle
523  = "Emul: technical trigger decision word after mask for BxInEvent = "
524  + str;
525  histTitle = hTitle.c_str();
526 
527  m_fdlEmulTechDecisionMask[iHist][iRec] = ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
528 
529  //
530  hName = recString + "DataEmul_TechDecision_" + str;
531  histName = hName.c_str();
532 
533  hTitle = "Data vs emul: non-matching technical trigger decision word for BxInEvent = " + str;
534  histTitle = hTitle.c_str();
535 
536  m_fdlDataEmulTechDecision[iHist][iRec] = ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
537 
538  hName = recString + "DataEmul_TechDecisionAfterMask_" + str;
539  histName = hName.c_str();
540 
541  hTitle = "Data vs emul: non-matching technical trigger decision word after mask for BxInEvent = " + str;
542  histTitle = hTitle.c_str();
543 
544  m_fdlDataEmulTechDecisionMask[iHist][iRec] = ibooker.book1D(histName, histTitle, numberTechTriggers, 0., numberTechTriggers);
545 
546  }
547 
548  if (iRec == 0) {
549  ibooker.setCurrentFolder(m_dirName + "/DAQ/");
550 
551  } else {
552  ibooker.setCurrentFolder(m_dirName + "/EVM/");
553  }
554 
555  hName = recString + "FdlDataEmul_Err";
556  histName = hName.c_str();
557 
558  m_fdlDataEmul_Err[iRec] = ibooker.book1D(histName, "FDL data vs emul mismatch for non-matching BxInEvent in FDL payload", 13, 0., 13.);
559  m_fdlDataEmul_Err[iRec]->setBinLabel(1, "BoardId", 1);
560  m_fdlDataEmul_Err[iRec]->setBinLabel(2, "BxInEvent", 1);
561  m_fdlDataEmul_Err[iRec]->setBinLabel(3, "BxNr", 1);
562  m_fdlDataEmul_Err[iRec]->setBinLabel(4, "EventNr", 1);
563  m_fdlDataEmul_Err[iRec]->setBinLabel(5, "TechTrigger", 1);
564  m_fdlDataEmul_Err[iRec]->setBinLabel(6, "TechTriggerMask", 1);
565  m_fdlDataEmul_Err[iRec]->setBinLabel(7, "AlgoTrigger", 1);
566  m_fdlDataEmul_Err[iRec]->setBinLabel(8, "AlgoTriggerMask", 1);
567  m_fdlDataEmul_Err[iRec]->setBinLabel(9, "AlgoExtend", 1);
568  m_fdlDataEmul_Err[iRec]->setBinLabel(10, "NoAlgo", 1);
569  m_fdlDataEmul_Err[iRec]->setBinLabel(11, "FinalORAllParts", 1);
570  m_fdlDataEmul_Err[iRec]->setBinLabel(12, "FinalORPhysPart", 1);
571  m_fdlDataEmul_Err[iRec]->setBinLabel(13, "LocalBxNr", 1);
572 
573  hName = recString + "FdlDataAlgoDecision_Err";
574  histName = hName.c_str();
575 
576  m_fdlDataAlgoDecision_Err[iRec] = ibooker.book1D(histName, "Data: algorithm trigger decision word, non-matching BxInEvent", numberAlgoTriggers, 0., numberAlgoTriggers);
577 
578  //
579  hName = recString + "Emul_AlgoDecision_Err";
580  histName = hName.c_str();
581 
582  m_fdlEmulAlgoDecision_Err[iRec] = ibooker.book1D(histName, "Emul: algorithm trigger decision word, non-matching BxInEvent", numberAlgoTriggers, 0., numberAlgoTriggers);
583 
584  hName = recString + "DataEmul_AlgoDecision_Err";
585  histName = hName.c_str();
586 
587  m_fdlDataEmulAlgoDecision_Err[iRec] = ibooker.book1D(histName, "Data vs emul: algorithm trigger decision word, non-matching BxInEvent", numberAlgoTriggers, 0., numberAlgoTriggers);
588 
589  //
590  hName = recString + "Data_TechDecision_Err";
591  histName = hName.c_str();
592 
593  m_fdlDataTechDecision_Err[iRec] = ibooker.book1D(histName, "Data: technical trigger decision word, non-matching BxInEvent", numberTechTriggers, 0., numberTechTriggers);
594 
595  hName = recString + "Emul_TechDecision_Err";
596  histName = hName.c_str();
597 
598  m_fdlEmulTechDecision_Err[iRec] = ibooker.book1D(histName, "Emul: technical trigger decision word, non-matching BxInEvent", numberTechTriggers, 0., numberTechTriggers);
599 
600  hName = recString + "DataEmul_TechDecision_Err";
601  histName = hName.c_str();
602 
603  m_fdlDataEmulTechDecision_Err[iRec] = ibooker.book1D(histName, "Data vs emul: technical trigger decision word, non-matching BxInEvent", numberTechTriggers, 0., numberTechTriggers);
604 
605  }
606 
607  ibooker.setCurrentFolder(m_dirName);
608 
609  //
610  m_excludedAlgorithmsAgreement = ibooker.book1D("ExcludedAlgorithmsFromAgreement", "Algorithms excluded from data versus emulator agreement flag", numberAlgoTriggers, 0., numberAlgoTriggers);
611 
612  //
613 
614  m_gtErrorFlag = ibooker.book1D("GTErrorFlag", "L1 GT error flag for data versus emulator comparison", 5, 0., 5);
615 
616  m_gtErrorFlag->setBinLabel(1, "Agree", 1);
617  m_gtErrorFlag->setBinLabel(2, "", 1);
618  m_gtErrorFlag->setBinLabel(3, "", 1);
619  m_gtErrorFlag->setBinLabel(4, "Data only", 1);
620  m_gtErrorFlag->setBinLabel(5, "Emul only", 1);
621 
622 
623  m_nrEvRun = 0;
624 
625  // get / update the trigger menu from the EventSetup
626  // local cache & check on cacheIdentifier
627 
628  unsigned long long l1GtMenuCacheID =
629  evSetup.get<L1GtTriggerMenuRcd>().cacheIdentifier();
630 
631  if (m_l1GtMenuCacheID != l1GtMenuCacheID) {
632 
633  edm::ESHandle<L1GtTriggerMenu> l1GtMenu;
634  evSetup.get<L1GtTriggerMenuRcd>().get(l1GtMenu);
635  m_l1GtMenu = l1GtMenu.product();
636 
637  // compute the list of algorithms excluded from the computing of the agreement flag
638  m_excludedAlgoList.clear();
639  excludedAlgoList();
640 
641  m_l1GtMenuCacheID = l1GtMenuCacheID;
642 
643  }
644 
645 
646 
647  // FIXME when the menu changes, make a copy of histograms, and clear the old one
648  // otherwise the labels are wrong
649 
650  LogDebug("L1GtHwValidation") << "\nUsing L1 menu: \n "
651  << m_l1GtMenu->gtTriggerMenuImplementation() << "\n"
652  << std::endl;
653 
654  const AlgorithmMap& algorithmMap = m_l1GtMenu->gtAlgorithmMap();
655 
656  for (CItAlgo itAlgo = algorithmMap.begin(); itAlgo != algorithmMap.end(); itAlgo++) {
657 
658  const int algBitNumber = (itAlgo->second).algoBitNumber();
659 
660  std::stringstream ss;
661  std::string algBitString;
662  ss << std::uppercase << algBitNumber;
663  ss >> algBitString;
664 
665  const std::string& aName = algBitString + " " + itAlgo->first;
666  const char* algName = aName.c_str();
667 
668  for (int iRec = 0; iRec < NumberOfGtRecords; ++iRec) {
669  for (int iBxInEvent = 0; iBxInEvent < TotalBxInEvent; ++iBxInEvent) {
670 
671 
672  // convert [0, TotalBxInEvent] to [-X, +X]
673  int iIndex = iBxInEvent - ((TotalBxInEvent + 1) / 2 - 1);
674  int hIndex = (iIndex + 16) % 16;
675 
676  std::stringstream ss;
677  std::string str;
678  ss << std::uppercase << std::hex << hIndex;
679  ss >> str;
680 
681  if (iRec == 0) {
682  //if (m_dbe) {
683  ibooker.setCurrentFolder(m_dirName + "/DAQ/BxInEvent_" + str);
684  //}
685 
686  } else {
687  //if (m_dbe) {
688  ibooker.setCurrentFolder(m_dirName + "/EVM/BxInEvent_" + str);
689  //}
690  }
691 
692 
693  m_fdlDataAlgoDecision[iBxInEvent][iRec]->setBinLabel(
694  algBitNumber + 1, algName, 1);
695  m_fdlDataAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(
696  algBitNumber + 1, algName, 1);
697  m_fdlDataAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(
698  algBitNumber + 1, algName, 1);
699  m_fdlDataAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(
700  algBitNumber + 1, algName, 1);
701  m_fdlDataAlgoDecision_NoMatch[iBxInEvent][iRec]->setBinLabel(
702  algBitNumber + 1, algName, 1);
703 
704  m_fdlEmulAlgoDecision[iBxInEvent][iRec]->setBinLabel(
705  algBitNumber + 1, algName, 1);
706  m_fdlEmulAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(
707  algBitNumber + 1, algName, 1);
708  m_fdlEmulAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(
709  algBitNumber + 1, algName, 1);
710  m_fdlEmulAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(
711  algBitNumber + 1, algName, 1);
712  m_fdlEmulAlgoDecision_NoMatch[iBxInEvent][iRec]->setBinLabel(
713  algBitNumber + 1, algName, 1);
714 
715  m_fdlDataEmulAlgoDecision[iBxInEvent][iRec]->setBinLabel(
716  algBitNumber + 1, algName, 1);
717  m_fdlDataEmulAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(
718  algBitNumber + 1, algName, 1);
719  m_fdlDataEmulAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(
720  algBitNumber + 1, algName, 1);
721  m_fdlDataEmulAlgoDecisionUnprescaledAllowed[iBxInEvent][iRec]->setBinLabel(
722  algBitNumber + 1, algName, 1);
723  m_fdlDataEmulAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(
724  algBitNumber + 1, algName, 1);
725  }
726 
727 
728  if (iRec == 0) {
729  ibooker.setCurrentFolder(m_dirName + "/DAQ/");
730 
731  } else {
732  ibooker.setCurrentFolder(m_dirName + "/EVM/");
733  }
734 
735 
736  m_fdlDataAlgoDecision_Err[iRec]->setBinLabel(algBitNumber + 1, algName, 1);
737 
738  m_fdlEmulAlgoDecision_Err[iRec]->setBinLabel(algBitNumber + 1, algName, 1);
739 
740  m_fdlDataEmulAlgoDecision_Err[iRec]->setBinLabel(algBitNumber + 1, algName, 1);
741  }
742 
743  //
744  for (std::vector<int>::const_iterator itAlgo = m_excludedAlgoList.begin(); itAlgo!= m_excludedAlgoList.end(); ++itAlgo) {
745 
746  if (algBitNumber == *itAlgo) {
747  m_excludedAlgorithmsAgreement->setBinLabel(algBitNumber + 1, algName, 1);
748  }
749  }
750 
751 
752  }
753 
754  // get / update the prescale factors from the EventSetup
755  // local cache & check on cacheIdentifier
756 
757  unsigned long long l1GtPfAlgoCacheID = evSetup.get<
758  L1GtPrescaleFactorsAlgoTrigRcd>().cacheIdentifier();
759 
760  if (m_l1GtPfAlgoCacheID != l1GtPfAlgoCacheID) {
761 
762  edm::ESHandle<L1GtPrescaleFactors> l1GtPfAlgo;
763  evSetup.get<L1GtPrescaleFactorsAlgoTrigRcd>().get(l1GtPfAlgo);
764  m_l1GtPfAlgo = l1GtPfAlgo.product();
765 
766  m_prescaleFactorsAlgoTrig = &(m_l1GtPfAlgo->gtPrescaleFactors());
767 
768  m_l1GtPfAlgoCacheID = l1GtPfAlgoCacheID;
769 
770  }
771 
772  unsigned long long l1GtPfTechCacheID = evSetup.get<
773  L1GtPrescaleFactorsTechTrigRcd>().cacheIdentifier();
774 
775  if (m_l1GtPfTechCacheID != l1GtPfTechCacheID) {
776 
777  edm::ESHandle<L1GtPrescaleFactors> l1GtPfTech;
778  evSetup.get<L1GtPrescaleFactorsTechTrigRcd>().get(l1GtPfTech);
779  m_l1GtPfTech = l1GtPfTech.product();
780 
781  m_prescaleFactorsTechTrig = &(m_l1GtPfTech->gtPrescaleFactors());
782 
783  m_l1GtPfTechCacheID = l1GtPfTechCacheID;
784 
785  }
786 
787  // get / update the trigger mask from the EventSetup
788  // local cache & check on cacheIdentifier
789 
790  unsigned long long l1GtTmAlgoCacheID = evSetup.get<
791  L1GtTriggerMaskAlgoTrigRcd>().cacheIdentifier();
792 
793  if (m_l1GtTmAlgoCacheID != l1GtTmAlgoCacheID) {
794 
795  edm::ESHandle<L1GtTriggerMask> l1GtTmAlgo;
796  evSetup.get<L1GtTriggerMaskAlgoTrigRcd>().get(l1GtTmAlgo);
797  m_l1GtTmAlgo = l1GtTmAlgo.product();
798 
799  m_triggerMaskAlgoTrig = m_l1GtTmAlgo->gtTriggerMask();
800 
801  m_l1GtTmAlgoCacheID = l1GtTmAlgoCacheID;
802 
803  }
804 
805  unsigned long long l1GtTmTechCacheID = evSetup.get<
806  L1GtTriggerMaskTechTrigRcd>().cacheIdentifier();
807 
808  if (m_l1GtTmTechCacheID != l1GtTmTechCacheID) {
809 
810  edm::ESHandle<L1GtTriggerMask> l1GtTmTech;
811  evSetup.get<L1GtTriggerMaskTechTrigRcd>().get(l1GtTmTech);
812  m_l1GtTmTech = l1GtTmTech.product();
813 
814  m_triggerMaskTechTrig = m_l1GtTmTech->gtTriggerMask();
815 
816  m_l1GtTmTechCacheID = l1GtTmTechCacheID;
817 
818  }
819 
820 }
821 
822 //compare the GTFE board
823 void L1GtHwValidation::compareGTFE(const edm::Event& iEvent,
824  const edm::EventSetup& evSetup, const L1GtfeWord& gtfeBlockData,
825  const L1GtfeWord& gtfeBlockEmul, const int iRec) {
826 
827  std::string recString;
828  if (gtfeBlockData == gtfeBlockEmul) {
829  m_myCoutStream << "\n" << recString
830  << " Data and emulated GTFE blocks: identical.\n";
831  gtfeBlockData.print(m_myCoutStream);
832  } else {
833  m_myCoutStream << "\n" << recString
834  << " Data and emulated GTFE blocks: different.\n";
835 
836  m_myCoutStream << "\nData: GTFE block\n";
837  gtfeBlockData.print(m_myCoutStream);
838 
839  m_myCoutStream << "\nEmul: GTFE block\n";
840  gtfeBlockEmul.print(m_myCoutStream);
841 
842  }
843 
844  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
845 
846  m_myCoutStream.str("");
847  m_myCoutStream.clear();
848 
849  // get BoardId value
850  const boost::uint16_t boardIdData = gtfeBlockData.boardId();
851  const boost::uint16_t boardIdEmul = gtfeBlockEmul.boardId();
852 
853  if (boardIdData == boardIdEmul) {
854  m_myCoutStream << "\n" << recString
855  << " Data and emulated GTFE boardId identical.";
856  m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4)
857  << std::setfill('0') << boardIdData << std::setfill(' ')
858  << std::dec;
859  m_myCoutStream << "\n";
860 
861  } else {
862  m_myCoutStream << "\n" << recString
863  << " Data and emulated GTFE boardId different.";
864  m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x"
865  << std::setw(4) << std::setfill('0') << boardIdData
866  << std::setfill(' ') << std::dec;
867  m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x"
868  << std::setw(4) << std::setfill('0') << boardIdEmul
869  << std::setfill(' ') << std::dec;
870  m_myCoutStream << "\n";
871  m_gtfeDataEmul[iRec]->Fill(0);
872 
873  }
874 
876  const boost::uint16_t recordLength1Data = gtfeBlockData.recordLength1();
877  const boost::uint16_t recordLength1Emul = gtfeBlockEmul.recordLength1();
878 
879  if (recordLength1Data == recordLength1Emul) {
880  m_myCoutStream << "\n" << recString
881  << " Data and emulated GTFE recordLength for alternative 1 identical.";
882  m_myCoutStream << "\n recordLength1() = " << recordLength1Data;
883  m_myCoutStream << "\n";
884 
885  } else {
886  m_myCoutStream << "\n" << recString
887  << " Data and emulated GTFE recordLength for alternative 1 different.";
888  m_myCoutStream << "\n Data: recordLength1() = " << recordLength1Data;
889  m_myCoutStream << "\n Emul: recordLength1() = " << recordLength1Emul;
890  m_myCoutStream << "\n";
891  m_gtfeDataEmul[iRec]->Fill(1);
892 
893  }
894 
896  const boost::uint16_t recordLengthData = gtfeBlockData.recordLength();
897  const boost::uint16_t recordLengthEmul = gtfeBlockEmul.recordLength();
898 
899  if (recordLengthData == recordLengthEmul) {
900  m_myCoutStream << "\n" << recString
901  << " Data and emulated GTFE recordLength for alternative 0 identical.";
902  m_myCoutStream << "\n recordLength() = " << recordLengthData;
903  m_myCoutStream << "\n";
904 
905  } else {
906  m_myCoutStream << "\n" << recString
907  << " Data and emulated GTFE recordLength for alternative 1 different.";
908  m_myCoutStream << "\n Data: recordLength() = " << recordLengthData;
909  m_myCoutStream << "\n Emul: recordLength() = " << recordLengthEmul;
910  m_myCoutStream << "\n";
911  m_gtfeDataEmul[iRec]->Fill(2);
912 
913  }
914 
916  const boost::uint16_t bxNrData = gtfeBlockData.bxNr();
917  const boost::uint16_t bxNrEmul = gtfeBlockEmul.bxNr();
918 
919  if (bxNrData == bxNrEmul) {
920  m_myCoutStream << "\n" << recString
921  << " Data and emulated GTFE bxNr identical.";
922  m_myCoutStream << "\n bxNr() = " << bxNrData;
923  m_myCoutStream << "\n";
924 
925  } else {
926  m_myCoutStream << "\n" << recString
927  << " Data and emulated GTFE bxNr different.";
928  m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
929  m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
930  m_myCoutStream << "\n";
931  m_gtfeDataEmul[iRec]->Fill(3);
932 
933  }
934 
936  const boost::uint32_t setupVersionData = gtfeBlockData.setupVersion();
937  const boost::uint32_t setupVersionEmul = gtfeBlockEmul.setupVersion();
938 
939  if (setupVersionData == setupVersionEmul) {
940  m_myCoutStream << "\n" << recString
941  << " Data and emulated GTFE setupVersion identical.";
942  m_myCoutStream << "\n setupVersion() = " << setupVersionData;
943  m_myCoutStream << "\n";
944 
945  } else {
946  m_myCoutStream << "\n" << recString
947  << " Data and emulated GTFE setupVersion different.";
948  m_myCoutStream << "\n Data: setupVersion() = " << setupVersionData;
949  m_myCoutStream << "\n Emul: setupVersion() = " << setupVersionEmul;
950  m_myCoutStream << "\n";
951  m_gtfeDataEmul[iRec]->Fill(4);
952 
953  }
954 
956  const boost::uint16_t activeBoardsData = gtfeBlockData.activeBoards();
957  const boost::uint16_t activeBoardsEmul = gtfeBlockEmul.activeBoards();
958 
959  if (activeBoardsData == activeBoardsEmul) {
960  m_myCoutStream << "\n" << recString
961  << " Data and emulated GTFE activeBoards identical.";
962  m_myCoutStream << "\n activeBoards() = " << std::hex << "0x"
963  << std::setw(4) << std::setfill('0') << activeBoardsData
964  << std::setfill(' ') << std::dec;
965  m_myCoutStream << "\n";
966 
967  } else {
968  m_myCoutStream << "\n" << recString
969  << " Data and emulated GTFE activeBoards different.";
970  m_myCoutStream << "\n Data: activeBoards() = " << std::hex << "0x"
971  << std::setw(4) << std::setfill('0') << activeBoardsData
972  << std::setfill(' ') << std::dec;
973  m_myCoutStream << "\n Emul: activeBoards() = " << std::hex << "0x"
974  << std::setw(4) << std::setfill('0') << activeBoardsEmul
975  << std::setfill(' ') << std::dec;
976  m_myCoutStream << "\n";
977  m_gtfeDataEmul[iRec]->Fill(5);
978 
979  }
984  const boost::uint16_t altNrBxBoardData = gtfeBlockData.altNrBxBoard();
985  const boost::uint16_t altNrBxBoardEmul = gtfeBlockEmul.altNrBxBoard();
986 
987  if (altNrBxBoardData == altNrBxBoardEmul) {
988  m_myCoutStream << "\n" << recString
989  << " Data and emulated GTFE altNrBxBoard identical.";
990  m_myCoutStream << "\n altNrBxBoard() = " << altNrBxBoardData;
991  m_myCoutStream << "\n";
992 
993  } else {
994  m_myCoutStream << "\n" << recString
995  << " Data and emulated GTFE altNrBxBoard different.";
996  m_myCoutStream << "\n Data: altNrBxBoard() = " << altNrBxBoardData;
997  m_myCoutStream << "\n Emul: altNrBxBoard() = " << altNrBxBoardEmul;
998  m_myCoutStream << "\n";
999  m_gtfeDataEmul[iRec]->Fill(6);
1000 
1001  }
1002 
1004  const boost::uint32_t totalTriggerNrData = gtfeBlockData.totalTriggerNr();
1005  const boost::uint32_t totalTriggerNrEmul = gtfeBlockEmul.totalTriggerNr();
1006 
1007  if (totalTriggerNrData == totalTriggerNrEmul) {
1008  m_myCoutStream << "\n" << recString
1009  << " Data and emulated GTFE totalTriggerNr identical.";
1010  m_myCoutStream << "\n totalTriggerNr() = " << totalTriggerNrData;
1011  m_myCoutStream << "\n";
1012 
1013  } else {
1014  m_myCoutStream << "\n" << recString
1015  << " Data and emulated GTFE totalTriggerNr different.";
1016  m_myCoutStream << "\n Data: totalTriggerNr() = " << totalTriggerNrData;
1017  m_myCoutStream << "\n Emul: totalTriggerNr() = " << totalTriggerNrEmul;
1018  m_myCoutStream << "\n";
1019  m_gtfeDataEmul[iRec]->Fill(7);
1020 
1021  }
1022 
1023  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1024  m_myCoutStream.str("");
1025  m_myCoutStream.clear();
1026 
1027 }
1028 
1029 //compare the FDL board
1030 void L1GtHwValidation::compareFDL(const edm::Event& iEvent,
1031  const edm::EventSetup& evSetup, const L1GtFdlWord& fdlBlockData,
1032  const L1GtFdlWord& fdlBlockEmul, const int iRec) {
1033 
1034  // index of physics partition
1035  int PhysicsPartition = 0;
1036 
1037  //
1038  std::string recString;
1039 
1040  if (fdlBlockData == fdlBlockEmul) {
1041  m_myCoutStream << "\n" << recString
1042  << " Data and emulated FDL blocks: identical.\n";
1043  fdlBlockData.print(m_myCoutStream);
1044 
1045  } else {
1046  m_myCoutStream << "\n" << recString
1047  << " Data and emulated FDL blocks: different.\n";
1048 
1049  m_myCoutStream << "\nData: FDL block\n";
1050  fdlBlockData.print(m_myCoutStream);
1051 
1052  m_myCoutStream << "\nEmul: FDL block\n";
1053  fdlBlockEmul.print(m_myCoutStream);
1054 
1055  }
1056 
1057  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1058 
1059  m_myCoutStream.str("");
1060  m_myCoutStream.clear();
1061 
1062  // get bunch cross in the GT event record -
1063  // move it first as histograms are BxInEvent dependent
1064  const int bxInEventData = fdlBlockData.bxInEvent();
1065  const int bxInEventEmul = fdlBlockEmul.bxInEvent();
1066 
1067  bool matchBxInEvent = false;
1068 
1069  if (bxInEventData == bxInEventEmul) {
1070  m_myCoutStream << "\n" << recString
1071  << " Data and emulated FDL bxInEvent identical.";
1072  m_myCoutStream << "\n bxInEvent() = " << bxInEventData;
1073  m_myCoutStream << "\n";
1074  matchBxInEvent = true;
1075 
1076  } else {
1077  m_myCoutStream << "\n" << recString
1078  << " Data and emulated FDL bxInEvent different.";
1079  m_myCoutStream << "\n Data: bxInEvent() = " << bxInEventData;
1080  m_myCoutStream << "\n Emul: bxInEvent() = " << bxInEventEmul;
1081  m_myCoutStream << "\n";
1082 
1083  m_fdlDataEmul_Err[iRec]->Fill(1);
1084 
1085  if (iRec == 0) {
1086  m_agree = false;
1087 
1088  m_myCoutStream << "\nDisagreement data versus emulator: "
1089  << "\n Data and emulated FDL bxInEvent different \n";
1090  }
1091 
1092  }
1093 
1094  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1095  m_myCoutStream.str("");
1096  m_myCoutStream.clear();
1097 
1098  // symmetrize
1099  bool validBxInEvent = false;
1100  int histIndex = bxInEventData + (TotalBxInEvent + 1) / 2 - 1;
1101  LogDebug("L1GtHwValidation") << "\n Convert bxInEvent = " << bxInEventData
1102  << " to histIndex = " << histIndex << std::endl;
1103  if ((histIndex <= TotalBxInEvent) && (histIndex >= 0)) {
1104  validBxInEvent = true;
1105  }
1106 
1107  // loop over algorithms and increase the corresponding counters
1108 
1109  // get BoardId value
1110  const boost::uint16_t boardIdData = fdlBlockData.boardId();
1111  const boost::uint16_t boardIdEmul = fdlBlockEmul.boardId();
1112 
1113  if (boardIdData == boardIdEmul) {
1114  m_myCoutStream << "\n" << recString
1115  << " Data and emulated FDL boardId identical.";
1116  m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4)
1117  << std::setfill('0') << boardIdData << std::setfill(' ')
1118  << std::dec;
1119  m_myCoutStream << "\n";
1120 
1121  } else {
1122  m_myCoutStream << "\n" << recString
1123  << " Data and emulated FDL boardId different.";
1124  m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x"
1125  << std::setw(4) << std::setfill('0') << boardIdData
1126  << std::setfill(' ') << std::dec;
1127  m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x"
1128  << std::setw(4) << std::setfill('0') << boardIdEmul
1129  << std::setfill(' ') << std::dec;
1130  m_myCoutStream << "\n";
1131 
1132  if (matchBxInEvent && validBxInEvent) {
1133  m_fdlDataEmul[histIndex][iRec]->Fill(0);
1134  } else {
1135  m_fdlDataEmul_Err[iRec]->Fill(0);
1136  }
1137 
1138  }
1139 
1140  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1141  m_myCoutStream.str("");
1142  m_myCoutStream.clear();
1143 
1144  // get BxNr - bunch cross number of the actual bx
1145  const boost::uint16_t bxNrData = fdlBlockData.bxNr();
1146  const boost::uint16_t bxNrEmul = fdlBlockEmul.bxNr();
1147 
1148  if (bxNrData == bxNrEmul) {
1149  m_myCoutStream << "\n" << recString
1150  << " Data and emulated FDL bxNr identical.";
1151  m_myCoutStream << "\n bxNr() = " << bxNrData;
1152  m_myCoutStream << "\n";
1153 
1154  } else {
1155  m_myCoutStream << "\n" << recString
1156  << " Data and emulated FDL bxNr different.";
1157  m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
1158  m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
1159  m_myCoutStream << "\n";
1160 
1161  if (matchBxInEvent && validBxInEvent) {
1162  m_fdlDataEmul[histIndex][iRec]->Fill(2);
1163  } else {
1164  m_fdlDataEmul_Err[iRec]->Fill(2);
1165  }
1166  }
1167 
1168  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1169  m_myCoutStream.str("");
1170  m_myCoutStream.clear();
1171 
1172  // get event number since last L1 reset generated in FDL
1173  const boost::uint32_t eventNrData = fdlBlockData.eventNr();
1174  const boost::uint32_t eventNrEmul = fdlBlockEmul.eventNr();
1175 
1176  if (eventNrData == eventNrEmul) {
1177  m_myCoutStream << "\n" << recString
1178  << " Data and emulated FDL eventNr identical.";
1179  m_myCoutStream << "\n eventNr() = " << eventNrData;
1180  m_myCoutStream << "\n";
1181 
1182  } else {
1183  m_myCoutStream << "\n" << recString
1184  << " Data and emulated FDL eventNr different.";
1185  m_myCoutStream << "\n Data: eventNr() = " << eventNrData;
1186  m_myCoutStream << "\n Emul: eventNr() = " << eventNrEmul;
1187  m_myCoutStream << "\n";
1188 
1189  if (matchBxInEvent && validBxInEvent) {
1190  m_fdlDataEmul[histIndex][iRec]->Fill(3);
1191  } else {
1192  m_fdlDataEmul_Err[iRec]->Fill(3);
1193  }
1194 
1195  }
1196 
1197  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1198  m_myCoutStream.str("");
1199  m_myCoutStream.clear();
1200 
1201  // get technical trigger bits
1202  const TechnicalTriggerWord& gtTechnicalTriggerWordData =
1203  fdlBlockData.gtTechnicalTriggerWord();
1204  const TechnicalTriggerWord& gtTechnicalTriggerWordEmul =
1205  fdlBlockEmul.gtTechnicalTriggerWord();
1206 
1207  int nTechBits = gtTechnicalTriggerWordData.size();
1208 
1209  TechnicalTriggerWord gtTechnicalTriggerWordDataMask(nTechBits);
1210  TechnicalTriggerWord gtTechnicalTriggerWordEmulMask(nTechBits);
1211 
1212  unsigned int bitValue = 0;
1213 
1214  if (matchBxInEvent && validBxInEvent) {
1215  for (int iBit = 0; iBit < nTechBits; ++iBit) {
1216 
1217  unsigned int triggerMask = (m_triggerMaskTechTrig.at(iBit)) & (1
1218  << PhysicsPartition);
1219 
1220  if (gtTechnicalTriggerWordData[iBit]) {
1221  m_fdlDataTechDecision[histIndex][iRec]->Fill(iBit);
1222 
1223  bitValue = (triggerMask) ? 0 : 1;
1224  gtTechnicalTriggerWordDataMask[iBit] = bitValue;
1225  if (bitValue) {
1226  m_fdlDataTechDecisionMask[histIndex][iRec]->Fill(iBit);
1227  }
1228  }
1229 
1230  if (gtTechnicalTriggerWordEmul.at(iBit)) {
1231  m_fdlEmulTechDecision[histIndex][iRec]->Fill(iBit);
1232 
1233  bitValue = (triggerMask) ? 0 : 1;
1234  gtTechnicalTriggerWordEmulMask[iBit] = bitValue;
1235  if (bitValue) {
1236  m_fdlEmulTechDecisionMask[histIndex][iRec]->Fill(iBit);
1237  }
1238  }
1239  }
1240  } else {
1241  for (int iBit = 0; iBit < nTechBits; ++iBit) {
1242 
1243  if (gtTechnicalTriggerWordData[iBit]) {
1244  m_fdlDataTechDecision_Err[iRec]->Fill(iBit);
1245  }
1246 
1247  if (gtTechnicalTriggerWordEmul.at(iBit)) {
1248  m_fdlEmulTechDecision_Err[iRec]->Fill(iBit);
1249  }
1250  }
1251  }
1252 
1253  if (gtTechnicalTriggerWordData == gtTechnicalTriggerWordEmul) {
1254  m_myCoutStream << "\n" << recString
1255  << " Data and emulated FDL gtTechnicalTriggerWord identical.\n";
1256  fdlBlockData.printGtTechnicalTriggerWord(m_myCoutStream);
1257  m_myCoutStream << "\n";
1258 
1259  } else {
1260  m_myCoutStream << "\n" << recString
1261  << " Data and emulated FDL gtTechnicalTriggerWord different.";
1262  m_myCoutStream << "\n Data: ";
1263  fdlBlockData.printGtTechnicalTriggerWord(m_myCoutStream);
1264  m_myCoutStream << "\n Emul: ";
1265  fdlBlockEmul.printGtTechnicalTriggerWord(m_myCoutStream);
1266  m_myCoutStream << "\n";
1267 
1268  if (matchBxInEvent && validBxInEvent) {
1269  m_fdlDataEmul[histIndex][iRec]->Fill(4);
1270  } else {
1271  m_fdlDataEmul_Err[iRec]->Fill(4);
1272  }
1273 
1274  if (matchBxInEvent && validBxInEvent) {
1275  for (int iBit = 0; iBit < nTechBits; ++iBit) {
1276  if (gtTechnicalTriggerWordData[iBit]
1277  != gtTechnicalTriggerWordEmul.at(iBit)) {
1278  m_fdlDataEmulTechDecision[histIndex][iRec]->Fill(iBit);
1279  }
1280  }
1281  } else {
1282  for (int iBit = 0; iBit < nTechBits; ++iBit) {
1283  if (gtTechnicalTriggerWordData[iBit]
1284  != gtTechnicalTriggerWordEmul.at(iBit)) {
1285  m_fdlDataEmulTechDecision_Err[iRec]->Fill(iBit);
1286  }
1287  }
1288  }
1289  }
1290 
1291  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1292  m_myCoutStream.str("");
1293  m_myCoutStream.clear();
1294 
1295  if (gtTechnicalTriggerWordDataMask == gtTechnicalTriggerWordEmulMask) {
1296  m_myCoutStream << "\n" << recString
1297  << " Data and emulated FDL gtTechnicalTriggerWord after mask identical.\n";
1298  m_myCoutStream << "\n";
1299 
1300  } else {
1301  m_myCoutStream << "\n" << recString
1302  << " Data and emulated FDL gtTechnicalTriggerWord after mask different.";
1303  m_myCoutStream << "\n Data: ";
1304  m_myCoutStream << "\n Emul: ";
1305  m_myCoutStream << "\n";
1306 
1307  if (matchBxInEvent && validBxInEvent) {
1308  m_fdlDataEmul[histIndex][iRec]->Fill(5);
1309  } else {
1310  m_fdlDataEmul_Err[iRec]->Fill(5);
1311  }
1312 
1313  if (matchBxInEvent && validBxInEvent) {
1314  for (int iBit = 0; iBit < nTechBits; ++iBit) {
1315  if (gtTechnicalTriggerWordData[iBit]
1316  != gtTechnicalTriggerWordEmul.at(iBit)) {
1317  m_fdlDataEmulTechDecisionMask[histIndex][iRec]->Fill(iBit);
1318  }
1319  }
1320  }
1321  }
1322 
1323  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1324  m_myCoutStream.str("");
1325  m_myCoutStream.clear();
1326 
1327  // get algorithms bits (decision word)
1328  const DecisionWord& gtDecisionWordData = fdlBlockData.gtDecisionWord();
1329  const DecisionWord& gtDecisionWordEmul = fdlBlockEmul.gtDecisionWord();
1330 
1331  int nAlgoBits = gtDecisionWordData.size();
1332 
1333  DecisionWord gtDecisionWordDataMask(nAlgoBits);
1334  DecisionWord gtDecisionWordEmulMask(nAlgoBits);
1335 
1336  // get the index of the prescale factor set from data
1337  int iPfSet = fdlBlockData.gtPrescaleFactorIndexAlgo();
1338 
1339  // check that the prescale factor is not out of range for the prescale factor
1340  // record retrieved from event setup
1341  size_t pfSetsSize = (*m_prescaleFactorsAlgoTrig).size();
1342 
1343  if (iPfSet < 0) {
1344 
1345  LogDebug("L1GtHwValidation")
1346  << "\nError: index of prescale factor set retrieved from the data \n"
1347  << "less than zero."
1348  << "\n Value of index retrieved from data = " << iPfSet
1349  << std::endl;
1350 
1351  // FIXME add a histogram to be used for a quality test
1352 
1353  return;
1354 
1355  } else if (iPfSet >= (static_cast<int>(pfSetsSize))) {
1356 
1357  LogDebug("L1GtHwValidation")
1358  << "\nError: index of prescale factor set retrieved from the data \n"
1359  << "greater than the size of the vector of prescale factor sets."
1360  << "\n Value of index retrieved from data = " << iPfSet
1361  << "\n Vector size = " << pfSetsSize << std::endl;
1362 
1363  // FIXME add a histogram to be used for a quality test
1364 
1365  return;
1366 
1367  }
1368 
1369  const std::vector<int>& prescaleFactorsAlgoTrig =
1370  (*m_prescaleFactorsAlgoTrig).at(iPfSet);
1371 
1372 
1373  if (matchBxInEvent && validBxInEvent) {
1374 
1375  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1376 
1377  unsigned int triggerMask = (m_triggerMaskAlgoTrig.at(iBit)) & (1
1378  << PhysicsPartition);
1379 
1380  int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
1381 
1382  LogTrace("L1GtHwValidation") << "Bit " << iBit
1383  << ": prescale factor = " << prescaleFactor
1384  << " trigger mask = " << triggerMask << std::endl;
1385 
1386  if (gtDecisionWordData[iBit]) {
1387  m_fdlDataAlgoDecision[histIndex][iRec]->Fill(iBit);
1388 
1389  if (prescaleFactor == 1) {
1390  m_fdlDataAlgoDecisionUnprescaled[histIndex][iRec]->Fill(
1391  iBit);
1392  } else {
1393  m_fdlDataAlgoDecisionPrescaled[histIndex][iRec]->Fill(iBit);
1394  }
1395 
1396  bitValue = (triggerMask) ? 0 : 1;
1397  gtDecisionWordDataMask[iBit] = bitValue;
1398  if (bitValue) {
1399  m_fdlDataAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
1400  }
1401  }
1402 
1403  if (gtDecisionWordEmul.at(iBit)) {
1404  m_fdlEmulAlgoDecision[histIndex][iRec]->Fill(iBit);
1405 
1406  bitValue = (triggerMask) ? 0 : 1;
1407  gtDecisionWordEmulMask[iBit] = bitValue;
1408  if (bitValue) {
1409  m_fdlEmulAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
1410  }
1411  }
1412  }
1413  } else {
1414  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1415  if (gtDecisionWordData[iBit]) {
1416  m_fdlDataAlgoDecision_Err[iRec]->Fill(iBit);
1417  }
1418  }
1419 
1420  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1421  if (gtDecisionWordEmul.at(iBit)) {
1422  m_fdlEmulAlgoDecision_Err[iRec]->Fill(iBit);
1423  }
1424  }
1425 
1426  if (iRec == 0) {
1427  m_agree = false;
1428 
1429  m_myCoutStream << "\nDisagreement data versus emulator: "
1430  << "\n matchBxInEvent && validBxInEvent false \n";
1431  }
1432 
1433  }
1434 
1435  if (gtDecisionWordData == gtDecisionWordEmul) {
1436  m_myCoutStream << "\n" << recString
1437  << " Data and emulated FDL gtDecisionWord identical.";
1438  fdlBlockData.printGtDecisionWord(m_myCoutStream);
1439  m_myCoutStream << "\n";
1440 
1441  } else {
1442  m_myCoutStream << "\n" << recString
1443  << " Data and emulated FDL gtDecisionWord different.";
1444  m_myCoutStream << "\n Data: ";
1445  fdlBlockData.printGtDecisionWord(m_myCoutStream);
1446  m_myCoutStream << "\n Emul: ";
1447  fdlBlockEmul.printGtDecisionWord(m_myCoutStream);
1448  m_myCoutStream << "\n";
1449 
1450  if (matchBxInEvent && validBxInEvent) {
1451  m_fdlDataEmul[histIndex][iRec]->Fill(6);
1452  } else {
1453  m_fdlDataEmul_Err[iRec]->Fill(6);
1454  }
1455 
1456  if (matchBxInEvent && validBxInEvent) {
1457  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1458 
1459  int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
1460 
1461  if (gtDecisionWordData[iBit] != gtDecisionWordEmul.at(iBit)) {
1462 
1463  m_fdlDataEmulAlgoDecision[histIndex][iRec]->Fill(iBit);
1464 
1465  // for excluded algorithms, fill mismatch for BxInEvent = 0 and DAQ record only
1466  if (excludedAlgo(iBit) && (bxInEventData == 0) && (iRec
1467  == 0)) {
1468  m_excludedAlgorithmsAgreement->Fill(iBit);
1469  }
1470 
1471  if (prescaleFactor == 1) {
1472  m_fdlDataEmulAlgoDecisionUnprescaled[histIndex][iRec]->Fill(
1473  iBit);
1474 
1475  // fill a histogram for allowed algorithm triggers only
1476  if (!excludedAlgo(iBit)) {
1477  m_fdlDataEmulAlgoDecisionUnprescaledAllowed[histIndex][iRec]->Fill(
1478  iBit);
1479  }
1480 
1481  } else {
1482  m_fdlDataEmulAlgoDecisionPrescaled[histIndex][iRec]->Fill(
1483  iBit);
1484  }
1485 
1486  if (gtDecisionWordData[iBit]) {
1487  m_fdlDataAlgoDecision_NoMatch[histIndex][iRec]->Fill(
1488  iBit);
1489 
1490  if (prescaleFactor == 1) {
1491  m_fdlDataAlgoDecisionUnprescaled_NoMatch[histIndex][iRec]->Fill(
1492  iBit);
1493 
1494  // compare for agreement only unprescaled algorithms and algorithms which
1495  // are not excluded from comparison
1496  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1497  && (iRec == 0)) {
1498  m_agree = false;
1499  m_dataOnly = true;
1500 
1501  m_myCoutStream
1502  << "\nDisagreement data versus emulator: "
1503  << "result before mask for algorithm with bit number "
1504  << iBit
1505  << "\n Data: true, emulator: false \n";
1506  }
1507 
1508  } else {
1509  m_fdlDataAlgoDecisionPrescaled_NoMatch[histIndex][iRec]->Fill(
1510  iBit);
1511  }
1512 
1513  } else {
1514  m_fdlEmulAlgoDecision_NoMatch[histIndex][iRec]->Fill(
1515  iBit);
1516 
1517  if (prescaleFactor == 1) {
1518  m_fdlEmulAlgoDecisionUnprescaled_NoMatch[histIndex][iRec]->Fill(
1519  iBit);
1520 
1521  // compare for agreement only unprescaled algorithms and algorithms which
1522  // are not excluded from comparison
1523  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1524  && (iRec == 0)) {
1525  m_agree = false;
1526  m_emulOnly = true;
1527 
1528  m_myCoutStream
1529  << "\nDisagreement data versus emulator: "
1530  << "result before mask for algorithm with bit number "
1531  << iBit
1532  << "\n Data: false, emulator: true \n";
1533  }
1534 
1535  } else {
1536  m_fdlEmulAlgoDecisionPrescaled_NoMatch[histIndex][iRec]->Fill(
1537  iBit);
1538  }
1539  }
1540  }
1541  }
1542  } else {
1543  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1544  if (gtDecisionWordData[iBit] != gtDecisionWordEmul.at(iBit)) {
1545  m_fdlDataEmulAlgoDecision_Err[iRec]->Fill(iBit);
1546  }
1547  }
1548 
1549  if (iRec == 0) {
1550  m_agree = false;
1551 
1552  m_myCoutStream << "\nDisagreement data versus emulator: "
1553  << "\n matchBxInEvent && validBxInEvent false \n";
1554  }
1555  }
1556 
1557  }
1558 
1559  if (gtDecisionWordDataMask == gtDecisionWordEmulMask) {
1560  m_myCoutStream << "\n" << recString
1561  << " Data and emulated FDL gtDecisionWord after mask identical.";
1562  m_myCoutStream << "\n";
1563 
1564  } else {
1565  m_myCoutStream << "\n" << recString
1566  << " Data and emulated FDL gtDecisionWord after mask different.";
1567  m_myCoutStream << "\n Data: ";
1568  m_myCoutStream << "\n Emul: ";
1569  m_myCoutStream << "\n";
1570 
1571  if (matchBxInEvent && validBxInEvent) {
1572  m_fdlDataEmul[histIndex][iRec]->Fill(7);
1573  } else {
1574  m_fdlDataEmul_Err[iRec]->Fill(7);
1575  }
1576 
1577  if (matchBxInEvent && validBxInEvent) {
1578  for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
1579  if (gtDecisionWordDataMask[iBit] != gtDecisionWordEmulMask.at(
1580  iBit)) {
1581  m_fdlDataEmulAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
1582 
1583 
1584  int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
1585 
1586  if (gtDecisionWordDataMask[iBit]) {
1587  m_fdlDataAlgoDecisionMask_NoMatch[histIndex][iRec]->Fill(
1588  iBit);
1589 
1590  if (prescaleFactor == 1) {
1591  m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[histIndex][iRec]->Fill(
1592  iBit);
1593 
1594  // compare for agreement only unprescaled algorithms and algorithms which
1595  // are not excluded from comparison
1596  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1597  && (iRec == 0)) {
1598  m_agree = false;
1599  m_dataOnlyMask = true;
1600 
1601  m_myCoutStream
1602  << "\nDisagreement data versus emulator: "
1603  << "result after mask for algorithm with bit number "
1604  << iBit
1605  << " different in data versus emulator "
1606  << "\n Data: true, emulator: false \n";
1607  }
1608 
1609  } else {
1610  m_fdlDataAlgoDecisionPrescaledMask_NoMatch[histIndex][iRec]->Fill(
1611  iBit);
1612  }
1613 
1614  } else {
1615  m_fdlEmulAlgoDecisionMask_NoMatch[histIndex][iRec]->Fill(
1616  iBit);
1617 
1618  if (prescaleFactor == 1) {
1619  m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[histIndex][iRec]->Fill(
1620  iBit);
1621 
1622  // compare for agreement only unprescaled algorithms and algorithms which
1623  // are not excluded from comparison
1624  if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
1625  && (iRec == 0)) {
1626  m_agree = false;
1627  m_emulOnlyMask = true;
1628 
1629  m_myCoutStream
1630  << "\nDisagreement data versus emulator: "
1631  << "result after mask for algorithm with bit number "
1632  << iBit
1633  << " different in data versus emulator "
1634  << "\n Data: false, emulator: true \n";
1635  }
1636 
1637  } else {
1638  m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[histIndex][iRec]->Fill(
1639  iBit);
1640  }
1641  }
1642 
1643 
1644  }
1645  }
1646  }
1647 
1648  }
1649 
1650  // get extended algorithms bits (extended decision word)
1651  const DecisionWordExtended& gtDecisionWordExtendedData =
1652  fdlBlockData.gtDecisionWordExtended();
1653  const DecisionWordExtended& gtDecisionWordExtendedEmul =
1654  fdlBlockEmul.gtDecisionWordExtended();
1655 
1656  if (gtDecisionWordExtendedData == gtDecisionWordExtendedEmul) {
1657  m_myCoutStream << "\n" << recString
1658  << " Data and emulated FDL gtDecisionWordExtended identical.\n";
1659  fdlBlockData.printGtDecisionWordExtended(m_myCoutStream);
1660  m_myCoutStream << "\n";
1661 
1662  } else {
1663  m_myCoutStream << "\n" << recString
1664  << " Data and emulated FDL gtDecisionWordExtended different.\n";
1665  m_myCoutStream << "\n Data: ";
1666  fdlBlockData.printGtDecisionWordExtended(m_myCoutStream);
1667  m_myCoutStream << "\n Emul: ";
1668  fdlBlockEmul.printGtDecisionWordExtended(m_myCoutStream);
1669  m_myCoutStream << "\n";
1670 
1671  if (matchBxInEvent && validBxInEvent) {
1672  m_fdlDataEmul[histIndex][iRec]->Fill(8);
1673  } else {
1674  m_fdlDataEmul_Err[iRec]->Fill(8);
1675  }
1676 
1677  }
1678 
1679  // get NoAlgo
1680  const boost::uint16_t noAlgoData = fdlBlockData.noAlgo();
1681  const boost::uint16_t noAlgoEmul = fdlBlockEmul.noAlgo();
1682 
1683  if (noAlgoData == noAlgoEmul) {
1684  m_myCoutStream << "\n" << recString
1685  << " Data and emulated FDL noAlgo identical.";
1686  m_myCoutStream << "\n noAlgo() = " << noAlgoData;
1687  m_myCoutStream << "\n";
1688 
1689  } else {
1690  m_myCoutStream << "\n" << recString
1691  << " Data and emulated FDL noAlgo different.";
1692  m_myCoutStream << "\n Data: noAlgo() = " << noAlgoData;
1693  m_myCoutStream << "\n Emul: noAlgo() = " << noAlgoEmul;
1694  m_myCoutStream << "\n";
1695 
1696  if (matchBxInEvent && validBxInEvent) {
1697  m_fdlDataEmul[histIndex][iRec]->Fill(9);
1698  } else {
1699  m_fdlDataEmul_Err[iRec]->Fill(9);
1700  }
1701 
1702  }
1703 
1704  // get "Final OR" bits
1705  const boost::uint16_t finalORData = fdlBlockData.finalOR();
1706  const boost::uint16_t finalOREmul = fdlBlockEmul.finalOR();
1707 
1708  if (finalORData == finalOREmul) {
1709  m_myCoutStream << "\n" << recString
1710  << " Data and emulated FDL finalOR identical.";
1711  m_myCoutStream << "\n finalOR() = " << std::hex << "0x" << std::setw(2)
1712  << std::setfill('0') << finalORData << std::setfill(' ')
1713  << std::dec;
1714  m_myCoutStream << "\n";
1715 
1716  } else {
1717  m_myCoutStream << "\n" << recString
1718  << " Data and emulated FDL finalOR different.";
1719  m_myCoutStream << "\n Data: finalOR() = " << std::hex << "0x"
1720  << std::setw(2) << std::setfill('0') << finalORData
1721  << std::setfill(' ') << std::dec;
1722  m_myCoutStream << "\n Emul: finalOR() = " << std::hex << "0x"
1723  << std::setw(2) << std::setfill('0') << finalOREmul
1724  << std::setfill(' ') << std::dec;
1725  m_myCoutStream << "\n";
1726 
1727  if (matchBxInEvent && validBxInEvent) {
1728  m_fdlDataEmul[histIndex][iRec]->Fill(10);
1729  } else {
1730  m_fdlDataEmul_Err[iRec]->Fill(10);
1731  }
1732 
1733  }
1734 
1735  // get "Final OR" for physics partition
1736  const int finalORPhysData = finalORData & (1 << PhysicsPartition);
1737  const int finalORPhysEmul = finalOREmul & (1 << PhysicsPartition);
1738 
1739  if (finalORPhysData == finalORPhysEmul) {
1740  m_myCoutStream << "\n" << recString
1741  << " Data and emulated FDL finalOR for the physics partition identical.";
1742  m_myCoutStream << "\n finalOR() = " << finalORPhysData;
1743  m_myCoutStream << "\n";
1744 
1745  } else {
1746  m_myCoutStream << "\n" << recString
1747  << " Data and emulated FDL finalOR for the physics partition different.";
1748  m_myCoutStream << "\n Data: finalOR() = " << finalORPhysData;
1749  m_myCoutStream << "\n Emul: finalOR() = " << finalORPhysEmul;
1750  m_myCoutStream << "\n";
1751 
1752  if (matchBxInEvent && validBxInEvent) {
1753  m_fdlDataEmul[histIndex][iRec]->Fill(11);
1754  } else {
1755  m_fdlDataEmul_Err[iRec]->Fill(11);
1756  }
1757 
1758  }
1759 
1760  // get local bunch cross number of the actual bx
1761  const boost::uint16_t localBxNrData = fdlBlockData.localBxNr();
1762  const boost::uint16_t localBxNrEmul = fdlBlockEmul.localBxNr();
1763 
1764  if (localBxNrData == localBxNrEmul) {
1765  m_myCoutStream << "\n" << recString
1766  << " Data and emulated FDL localBxNr identical.";
1767  m_myCoutStream << "\n localBxNr() = " << localBxNrData;
1768  m_myCoutStream << "\n";
1769 
1770  } else {
1771  m_myCoutStream << "\n" << recString
1772  << " Data and emulated FDL localBxNr different.";
1773  m_myCoutStream << "\n Data: localBxNr() = " << localBxNrData;
1774  m_myCoutStream << "\n Emul: localBxNr() = " << localBxNrEmul;
1775  m_myCoutStream << "\n";
1776 
1777  if (matchBxInEvent && validBxInEvent) {
1778  m_fdlDataEmul[histIndex][iRec]->Fill(12);
1779  } else {
1780  m_fdlDataEmul_Err[iRec]->Fill(12);
1781  }
1782 
1783  }
1784 
1785  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1786  m_myCoutStream.str("");
1787  m_myCoutStream.clear();
1788 
1789 }
1790 
1791 //compare the PSB board
1792 void L1GtHwValidation::comparePSB(const edm::Event& iEvent,
1793  const edm::EventSetup& evSetup, const L1GtPsbWord& psbBlockData,
1794  const L1GtPsbWord& psbBlockEmul) {
1795 
1796  if (psbBlockData == psbBlockEmul) {
1797  m_myCoutStream << "\nData and emulated PSB blocks: identical.\n";
1798  psbBlockData.print(m_myCoutStream);
1799 
1800  } else {
1801  m_myCoutStream << "\nData and emulated PSB blocks: different.\n";
1802 
1803  m_myCoutStream << "\nData: PSB block\n";
1804  psbBlockData.print(m_myCoutStream);
1805 
1806  m_myCoutStream << "\nEmul: PSB block\n";
1807  psbBlockEmul.print(m_myCoutStream);
1808 
1809  }
1810 
1811  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1812 
1813  m_myCoutStream.str("");
1814  m_myCoutStream.clear();
1815 
1816  // get BoardId value
1817  const boost::uint16_t boardIdData = psbBlockData.boardId();
1818  const boost::uint16_t boardIdEmul = psbBlockEmul.boardId();
1819 
1820  if (boardIdData == boardIdEmul) {
1821  m_myCoutStream << "\nData and emulated PSB boardId identical.";
1822  m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4)
1823  << std::setfill('0') << boardIdData << std::setfill(' ')
1824  << std::dec;
1825  m_myCoutStream << "\n";
1826 
1827  } else {
1828  m_myCoutStream << "\nData and emulated PSB boardId different.";
1829  m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x"
1830  << std::setw(4) << std::setfill('0') << boardIdData
1831  << std::setfill(' ') << std::dec;
1832  m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x"
1833  << std::setw(4) << std::setfill('0') << boardIdEmul
1834  << std::setfill(' ') << std::dec;
1835  m_myCoutStream << "\n";
1836 
1837  }
1838 
1839  // get bunch cross in the GT event record
1840  const int bxInEventData = psbBlockData.bxInEvent();
1841  const int bxInEventEmul = psbBlockEmul.bxInEvent();
1842 
1843  if (bxInEventData == bxInEventEmul) {
1844  m_myCoutStream << "\nData and emulated PSB bxInEvent identical.";
1845  m_myCoutStream << "\n bxInEvent() = " << bxInEventData;
1846  m_myCoutStream << "\n";
1847 
1848  } else {
1849  m_myCoutStream << "\nData and emulated PSB bxInEvent different.";
1850  m_myCoutStream << "\n Data: bxInEvent() = " << bxInEventData;
1851  m_myCoutStream << "\n Emul: bxInEvent() = " << bxInEventEmul;
1852  m_myCoutStream << "\n";
1853 
1854  }
1855 
1856  // get BxNr - bunch cross number of the actual bx
1857  const boost::uint16_t bxNrData = psbBlockData.bxNr();
1858  const boost::uint16_t bxNrEmul = psbBlockEmul.bxNr();
1859 
1860  if (bxNrData == bxNrEmul) {
1861  m_myCoutStream << "\nData and emulated PSB bxNr identical.";
1862  m_myCoutStream << "\n bxNr() = " << bxNrData;
1863  m_myCoutStream << "\n";
1864 
1865  } else {
1866  m_myCoutStream << "\nData and emulated PSB bxNr different.";
1867  m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
1868  m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
1869  m_myCoutStream << "\n";
1870 
1871  }
1872 
1873  // get event number since last L1 reset generated in FDL
1874  const boost::uint32_t eventNrData = psbBlockData.eventNr();
1875  const boost::uint32_t eventNrEmul = psbBlockEmul.eventNr();
1876 
1877  if (eventNrData == eventNrEmul) {
1878  m_myCoutStream << "\nData and emulated PSB eventNr identical.";
1879  m_myCoutStream << "\n eventNr() = " << eventNrData;
1880  m_myCoutStream << "\n";
1881 
1882  } else {
1883  m_myCoutStream << "\nData and emulated PSB eventNr different.";
1884  m_myCoutStream << "\n Data: eventNr() = " << eventNrData;
1885  m_myCoutStream << "\n Emul: eventNr() = " << eventNrEmul;
1886  m_myCoutStream << "\n";
1887 
1888  }
1889 
1891  boost::uint16_t valData;
1892  boost::uint16_t valEmul;
1893 
1894  for (int iA = 0; iA < psbBlockData.NumberAData; ++iA) {
1895  valData = psbBlockData.aData(iA);
1896  valEmul = psbBlockEmul.aData(iA);
1897 
1898  if (valData == valEmul) {
1899  m_myCoutStream << "\nData and emulated PSB aData(" << iA
1900  << ") identical.";
1901  m_myCoutStream << "\n aData(iA) = " << std::hex << "0x"
1902  << std::setw(4) << std::setfill('0') << valData
1903  << std::setfill(' ') << std::dec;
1904  m_myCoutStream << "\n";
1905 
1906  } else {
1907  m_myCoutStream << "\nData and emulated PSB aData(" << iA
1908  << ") different.";
1909  m_myCoutStream << "\n Data: aData(iA) = " << std::hex << "0x"
1910  << std::setw(4) << std::setfill('0') << valData
1911  << std::setfill(' ') << std::dec;
1912  m_myCoutStream << "\n Emul: aData(iA) = " << std::hex << "0x"
1913  << std::setw(4) << std::setfill('0') << valEmul
1914  << std::setfill(' ') << std::dec;
1915  m_myCoutStream << "\n";
1916 
1917  }
1918 
1919  }
1920 
1922  for (int iB = 0; iB < psbBlockData.NumberBData; ++iB) {
1923  valData = psbBlockData.bData(iB);
1924  valEmul = psbBlockEmul.bData(iB);
1925 
1926  if (valData == valEmul) {
1927  m_myCoutStream << "\nData and emulated PSB bData(" << iB
1928  << ") identical.";
1929  m_myCoutStream << "\n bData(iA) = " << std::hex << "0x"
1930  << std::setw(4) << std::setfill('0') << valData
1931  << std::setfill(' ') << std::dec;
1932  m_myCoutStream << "\n";
1933 
1934  } else {
1935  m_myCoutStream << "\nData and emulated PSB bData(" << iB
1936  << ") different.";
1937  m_myCoutStream << "\n Data: bData(iA) = " << std::hex << "0x"
1938  << std::setw(4) << std::setfill('0') << valData
1939  << std::setfill(' ') << std::dec;
1940  m_myCoutStream << "\n Emul: bData(iA) = " << std::hex << "0x"
1941  << std::setw(4) << std::setfill('0') << valEmul
1942  << std::setfill(' ') << std::dec;
1943  m_myCoutStream << "\n";
1944 
1945  }
1946 
1947  }
1948 
1949  // get local bunch cross number of the actual bx
1950  const boost::uint16_t localBxNrData = psbBlockData.localBxNr();
1951  const boost::uint16_t localBxNrEmul = psbBlockEmul.localBxNr();
1952 
1953  if (localBxNrData == localBxNrEmul) {
1954  m_myCoutStream << "\nData and emulated PSB localBxNr identical.";
1955  m_myCoutStream << "\n localBxNr() = " << localBxNrData;
1956  m_myCoutStream << "\n";
1957 
1958  } else {
1959  m_myCoutStream << "\nData and emulated PSB localBxNr different.";
1960  m_myCoutStream << "\n Data: localBxNr() = " << localBxNrData;
1961  m_myCoutStream << "\n Emul: localBxNr() = " << localBxNrEmul;
1962  m_myCoutStream << "\n";
1963 
1964  }
1965 
1966  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
1967  m_myCoutStream.str("");
1968  m_myCoutStream.clear();
1969 
1970 }
1971 
1972 //compare the TCS board
1973 void L1GtHwValidation::compareTCS(const edm::Event& iEvent,
1974  const edm::EventSetup& evSetup, const L1TcsWord&, const L1TcsWord&) {
1975  // empty
1976 }
1977 
1978 //L1 GT DAQ record comparison
1979 void L1GtHwValidation::compareDaqRecord(const edm::Event& iEvent, const edm::EventSetup& evSetup) {
1980 
1981  // formal index for DAQ record
1982  int iRec = 0;
1983 
1984  // reset the flags - they are used for DAQ recor only
1985  m_agree = true;
1986  m_dataOnly = false;
1987  m_emulOnly = false;
1988  m_dataOnlyMask = false;
1989  m_emulOnlyMask = false;
1990 
1991 
1992  // get the L1 GT hardware DAQ record L1GlobalTriggerReadoutRecord
1993  edm::Handle<L1GlobalTriggerReadoutRecord> gtReadoutRecordData;
1994  iEvent.getByToken(m_l1GtDataDaqInputToken_, gtReadoutRecordData);
1995 
1996  bool validData = false;
1997 
1998  if (!gtReadoutRecordData.isValid()) {
1999  m_nrDataEventError++;
2000  } else {
2001  validData = true;
2002  }
2003 
2004  // get the L1 GT emulator DAQ record L1GlobalTriggerReadoutRecord
2005  edm::Handle<L1GlobalTriggerReadoutRecord> gtReadoutRecordEmul;
2006  iEvent.getByToken(m_l1GtEmulDaqInputToken_, gtReadoutRecordEmul);
2007 
2008  bool validEmul = false;
2009 
2010  if (!gtReadoutRecordEmul.isValid()) {
2011  m_nrEmulEventError++;
2012  } else {
2013  validEmul = true;
2014  }
2015 
2016  if ((!validData) || (!validEmul)) {
2017  edm::LogWarning("L1GtHwValidation")
2018  << "\n No valid product found: DAQ L1GlobalTriggerReadoutRecord"
2019  << "\n Data validity [1 = true; 0 = false]: " << validData
2020  << "\n Emulator validity: [1 = true; 0 = false]: "
2021  << validEmul << "\n DAQ histograms will not be filled.\n"
2022  << std::endl;
2023 
2024  return;
2025  }
2026 
2027  // compare GTFE
2028  const L1GtfeWord& gtfeBlockData = gtReadoutRecordData->gtfeWord();
2029  const L1GtfeWord& gtfeBlockEmul = gtReadoutRecordEmul->gtfeWord();
2030 
2031  compareGTFE(iEvent, evSetup, gtfeBlockData, gtfeBlockEmul, iRec);
2032 
2033  // FDL comparison
2034  const std::vector<L1GtFdlWord>& gtFdlVectorData =
2035  gtReadoutRecordData->gtFdlVector();
2036  const std::vector<L1GtFdlWord>& gtFdlVectorEmul =
2037  gtReadoutRecordEmul->gtFdlVector();
2038 
2039  int gtFdlVectorDataSize = gtFdlVectorData.size();
2040  int gtFdlVectorEmulSize = gtFdlVectorEmul.size();
2041 
2042  if (gtFdlVectorDataSize == gtFdlVectorEmulSize) {
2043  m_myCoutStream << "\nData and emulated FDL vector size: identical.\n";
2044  m_myCoutStream << " Size: " << gtFdlVectorDataSize << std::endl;
2045 
2046  for (int iFdl = 0; iFdl < gtFdlVectorDataSize; ++iFdl) {
2047 
2048  const L1GtFdlWord& fdlBlockData = gtFdlVectorData[iFdl];
2049  const L1GtFdlWord& fdlBlockEmul = gtFdlVectorEmul[iFdl];
2050 
2051  compareFDL(iEvent, evSetup, fdlBlockData, fdlBlockEmul, iRec);
2052  }
2053  } else {
2054  m_myCoutStream << "\nData and emulated FDL vector size: different.\n";
2055  m_myCoutStream << " Data: size = " << gtFdlVectorDataSize << std::endl;
2056  m_myCoutStream << " Emul: size = " << gtFdlVectorEmulSize << std::endl;
2057 
2058  }
2059 
2060  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
2061 
2062  m_myCoutStream.str("");
2063  m_myCoutStream.clear();
2064 
2065  // PSB comparison
2066  const std::vector<L1GtPsbWord>& gtPsbVectorData =
2067  gtReadoutRecordData->gtPsbVector();
2068  const std::vector<L1GtPsbWord>& gtPsbVectorEmul =
2069  gtReadoutRecordEmul->gtPsbVector();
2070 
2071  int gtPsbVectorDataSize = gtPsbVectorData.size();
2072  int gtPsbVectorEmulSize = gtPsbVectorEmul.size();
2073 
2074  if (gtPsbVectorDataSize == gtPsbVectorEmulSize) {
2075  m_myCoutStream << "\nData and emulated PSB vector size: identical.\n";
2076  m_myCoutStream << " Size: " << gtPsbVectorDataSize << std::endl;
2077  } else {
2078  m_myCoutStream << "\nData and emulated PSB vector size: different.\n";
2079  m_myCoutStream << " Data: size = " << gtPsbVectorDataSize << std::endl;
2080  m_myCoutStream << " Emul: size = " << gtPsbVectorEmulSize << std::endl;
2081 
2082  }
2083 
2084  // the order of PSB block in the gtPsbVector is different in emulator and in data
2085  // in emulator: all active PSB in one BxInEvent, ordered L1A-1, L1A, L1A+1
2086  // in unpacker: every PSB in all BxInEvent
2087  for (int iPsb = 0; iPsb < gtPsbVectorDataSize; ++iPsb) {
2088 
2089  const L1GtPsbWord& psbBlockData = gtPsbVectorData[iPsb];
2090  const boost::uint16_t boardIdData = psbBlockData.boardId();
2091  const int bxInEventData = psbBlockData.bxInEvent();
2092 
2093  // search the corresponding PSB in the emulated record using the
2094  // BoardId and the BxInEvent
2095 
2096  bool foundPSB = false;
2097 
2098  for (int iPsbF = 0; iPsbF < gtPsbVectorEmulSize; ++iPsbF) {
2099 
2100  const L1GtPsbWord& psbBlockEmul = gtPsbVectorEmul[iPsbF];
2101  const boost::uint16_t boardIdEmul = psbBlockEmul.boardId();
2102  const int bxInEventEmul = psbBlockEmul.bxInEvent();
2103 
2104  if ((boardIdEmul == boardIdData)
2105  && (bxInEventData == bxInEventEmul)) {
2106 
2107  foundPSB = true;
2108 
2109  // compare the boards
2110  comparePSB(iEvent, evSetup, psbBlockData, psbBlockEmul);
2111  }
2112 
2113  }
2114 
2115  if (!foundPSB) {
2116  m_myCoutStream << "\nNo emulated PSB with boardId() = " << std::hex
2117  << "0x" << std::setw(4) << std::setfill('0') << boardIdData
2118  << std::setfill(' ') << std::dec << " and BxInEvent = "
2119  << bxInEventData << " was found";
2120 
2121  }
2122 
2123  }
2124 
2125  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
2126 
2127  m_myCoutStream.str("");
2128  m_myCoutStream.clear();
2129 
2130  // fill the m_gtErrorFlag histogram (only for L1 GT DAQ record)
2131 
2132  if (m_agree) {
2133  m_gtErrorFlag->Fill(0.0001);
2134  }
2135 
2136  if (m_dataOnly || m_dataOnlyMask) {
2137  m_gtErrorFlag->Fill(3.0001);
2138  }
2139 
2140  if (m_emulOnly || m_emulOnlyMask) {
2141  m_gtErrorFlag->Fill(4.0001);
2142  }
2143 
2144 }
2145 
2146 // L1 GT EVM record comparison
2147 void L1GtHwValidation::compareEvmRecord(const edm::Event& iEvent,
2148  const edm::EventSetup& evSetup) {
2149 
2150  // formal index for EVM record
2151  int iRec = 1;
2152 
2153  // get the L1 GT hardware EVM record L1GlobalTriggerEvmReadoutRecord
2154  edm::Handle<L1GlobalTriggerEvmReadoutRecord> gtReadoutRecordData;
2155  iEvent.getByToken(m_l1GtDataEvmInputToken_, gtReadoutRecordData);
2156 
2157  bool validData = false;
2158 
2159  if (!gtReadoutRecordData.isValid()) {
2160  m_nrDataEventError++;
2161  } else {
2162  validData = true;
2163  }
2164 
2165  // get the L1 GT emulator EVM record L1GlobalTriggerEvmReadoutRecord
2166  edm::Handle<L1GlobalTriggerEvmReadoutRecord> gtReadoutRecordEmul;
2167  iEvent.getByToken(m_l1GtEmulEvmInputToken_, gtReadoutRecordEmul);
2168 
2169  bool validEmul = false;
2170 
2171  if (!gtReadoutRecordEmul.isValid()) {
2172  m_nrEmulEventError++;
2173  } else {
2174  validEmul = true;
2175  }
2176 
2177  if ((!validData) || (!validEmul)) {
2178  edm::LogWarning("L1GtHwValidation")
2179  << "\n No valid product found: EVM L1GlobalTriggerEvmReadoutRecord"
2180  << "\n Data validity [1 = true; 0 = false]: " << validData
2181  << "\n Emulator validity: [1 = true; 0 = false]: "
2182  << validEmul << "\n EVM histograms will not be filled.\n"
2183  << std::endl;
2184 
2185  return;
2186  }
2187 
2188  // compare GTFE
2189  const L1GtfeWord& gtfeBlockData = gtReadoutRecordData->gtfeWord();
2190  const L1GtfeWord& gtfeBlockEmul = gtReadoutRecordEmul->gtfeWord();
2191 
2192  compareGTFE(iEvent, evSetup, gtfeBlockData, gtfeBlockEmul, iRec);
2193 
2194  // FDL comparison
2195  const std::vector<L1GtFdlWord>& gtFdlVectorData =
2196  gtReadoutRecordData->gtFdlVector();
2197  const std::vector<L1GtFdlWord>& gtFdlVectorEmul =
2198  gtReadoutRecordEmul->gtFdlVector();
2199 
2200  int gtFdlVectorDataSize = gtFdlVectorData.size();
2201  int gtFdlVectorEmulSize = gtFdlVectorEmul.size();
2202 
2203  if (gtFdlVectorDataSize == gtFdlVectorEmulSize) {
2204  m_myCoutStream << "\nData and emulated FDL vector size: identical.\n";
2205  m_myCoutStream << " Size: " << gtFdlVectorDataSize << std::endl;
2206 
2207  for (int iFdl = 0; iFdl < gtFdlVectorDataSize; ++iFdl) {
2208 
2209  const L1GtFdlWord& fdlBlockData = gtFdlVectorData[iFdl];
2210  const L1GtFdlWord& fdlBlockEmul = gtFdlVectorEmul[iFdl];
2211 
2212  compareFDL(iEvent, evSetup, fdlBlockData, fdlBlockEmul, iRec);
2213  }
2214  } else {
2215  m_myCoutStream << "\nData and emulated FDL vector size: different.\n";
2216  m_myCoutStream << " Data: size = " << gtFdlVectorDataSize << std::endl;
2217  m_myCoutStream << " Emul: size = " << gtFdlVectorEmulSize << std::endl;
2218 
2219  }
2220 
2221  // FIXME compare TCS
2222 
2223  LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
2224 
2225  m_myCoutStream.str("");
2226  m_myCoutStream.clear();
2227 
2228  edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
2229 
2230  m_myCoutStream.str("");
2231  m_myCoutStream.clear();
2232 
2233 }
2234 
2235 // compare the GCT collections obtained from L1 GT PSB with the input
2236 // GCT collections
2237 void L1GtHwValidation::compareGt_Gct(const edm::Event& iEvent,
2238  const edm::EventSetup&) {
2239 
2240  // FIXME
2241 
2242 }
2243 
2244 // analyze each event: event loop
2245 void L1GtHwValidation::analyze(const edm::Event& iEvent,
2246  const edm::EventSetup& evSetup) {
2247 
2248  ++m_nrEvJob;
2249  ++m_nrEvRun;
2250 
2251  // L1 GT DAQ record comparison
2252  compareDaqRecord(iEvent, evSetup);
2253 
2254  // L1 GT EVM record comparison
2255  compareEvmRecord(iEvent, evSetup);
2256 
2257  // GCT collections from L1 GT PSB versus unpacked GCT
2258  compareGt_Gct(iEvent, evSetup);
2259 
2260 }
2261 
2262 
2263 bool L1GtHwValidation::matchCondCategory(
2264  const L1GtConditionCategory& conditionCategory,
2265  const L1GtConditionCategory& excludedCategory) {
2266 
2267  bool matchValue = false;
2268 
2269  if (excludedCategory == CondNull) {
2270  matchValue = true;
2271  } else {
2272  if (conditionCategory == excludedCategory) {
2273  matchValue = true;
2274  }
2275  }
2276 
2277  return matchValue;
2278 }
2279 
2280 
2281 bool L1GtHwValidation::matchCondType(const L1GtConditionType& conditionType,
2282  const L1GtConditionType& excludedType) {
2283 
2284  bool matchValue = false;
2285 
2286  if (excludedType == TypeNull) {
2287  matchValue = true;
2288  } else {
2289  if (conditionType == excludedType) {
2290  matchValue = true;
2291  }
2292  }
2293 
2294  return matchValue;
2295 }
2296 
2297 
2298 bool L1GtHwValidation::matchCondL1GtObject(
2299  const std::vector<L1GtObject>& condObjects,
2300  const L1GtObject& excludedObject) {
2301 
2302  bool matchValue = false;
2303 
2304  if (excludedObject == ObjNull) {
2305 
2306  matchValue = true;
2307 
2308  } else {
2309 
2310  for (std::vector<L1GtObject>::const_iterator itCondObj =
2311  condObjects.begin(); itCondObj != condObjects.end(); ++itCondObj) {
2312 
2313  if ((*itCondObj) == excludedObject) {
2314 
2315  matchValue = true;
2316 
2317  }
2318  }
2319  }
2320 
2321  return matchValue;
2322 
2323 }
2324 
2325 
2326 void L1GtHwValidation::excludedAlgoList() {
2327 
2328 
2329  const AlgorithmMap& algorithmMap = m_l1GtMenu->gtAlgorithmMap();
2330 
2331  for (CItAlgo itAlgo = algorithmMap.begin(); itAlgo != algorithmMap.end(); itAlgo++) {
2332 
2333  const std::string& algName = itAlgo->first;
2334  const int algBitNumber = (itAlgo->second).algoBitNumber();
2335  const int chipNr = (itAlgo->second).algoChipNumber();
2336 
2337  const ConditionMap& conditionMap = (m_l1GtMenu->gtConditionMap()).at(
2338  chipNr);
2339 
2340  const std::vector<L1GtLogicParser::TokenRPN>& aRpnVector =
2341  (itAlgo->second).algoRpnVector();
2342  size_t aRpnVectorSize = aRpnVector.size();
2343 
2344  bool algWithExcludedCondition = false;
2345  bool algWithConditionNotInMap = false;
2346 
2347  // loop over RpnVector and check each conditions against list of excluded conditions
2348  for (size_t opI = 0; opI < aRpnVectorSize; ++opI) {
2349 
2350  const std::string& cndName = (aRpnVector[opI]).operand;
2351 
2352  if (!cndName.empty()) {
2353  bool foundCond = false;
2354 
2355  CItCond itCond = conditionMap.find(cndName);
2356  if (itCond != conditionMap.end()) {
2357 
2358  const L1GtConditionCategory& cCateg = (itCond->second)->condCategory();
2359  const L1GtConditionType& cType = (itCond->second)->condType();
2360  const std::vector<L1GtObject>& objType = (itCond->second)->objectType();
2361 
2362  // condition index in the m_excludedCondCategory, m_excludedCondType, m_excludedL1GtObject vectors
2363  int iCond = -1;
2364 
2365  for (std::vector<L1GtConditionCategory>::const_iterator
2366  itCateg = m_excludedCondCategory.begin();
2367  itCateg != m_excludedCondCategory.end(); ++itCateg) {
2368 
2369  iCond++;
2370 
2371  bool matchCondCategoryValue = matchCondCategory(cCateg, (*itCateg));
2372  bool matchCondTypeValue = matchCondType(cType, m_excludedCondType.at(iCond));
2373  bool matchCondL1GtObjectValue = matchCondL1GtObject(objType, m_excludedL1GtObject.at(iCond));
2374 
2375  LogTrace("L1GtHwValidation")
2376  << "\n "
2377  << "Algorithm: " << algName
2378  << " Condition: " << cndName
2379  << "\n "
2380  << "Category: " << l1GtConditionCategoryEnumToString(cCateg)
2381  << "; excluded: " << l1GtConditionCategoryEnumToString((*itCateg))
2382  << "\n "
2383  << "Type: " << l1GtConditionTypeEnumToString(cType)
2384  << "; excluded: " << l1GtConditionTypeEnumToString(m_excludedCondType.at(iCond))
2385  << "\n "
2386  << "Object excluded: " << l1GtObjectEnumToString(m_excludedL1GtObject.at(iCond))
2387  << std::endl;
2388 
2389 
2390  if (matchCondCategoryValue && matchCondTypeValue && matchCondL1GtObjectValue) {
2391 
2392  algWithExcludedCondition = true;
2393 
2394  }
2395 
2396  }
2397 
2398  foundCond = true;
2399  }
2400 
2401  if (!foundCond) {
2402  // it should never be happen, all conditions are in the maps
2403 
2404  algWithConditionNotInMap = true;
2405 
2406  LogTrace("L1GtHwValidation") << "\n Error: condition "
2407  << cndName << " not found in condition map!"
2408  << "\n Add algorithm " << algName
2409  << " (bit number " << algBitNumber << ") "
2410  << "\n to list of algorithms excluded from comparison"
2411  << "\n data versus emulator." << std::endl;
2412  }
2413 
2414  }
2415  }
2416 
2417  if (algWithConditionNotInMap) {
2418  // it should never be happen, all conditions are in the maps
2419 
2420  m_excludedAlgoList.push_back(algBitNumber);
2421 
2422  LogTrace("L1GtHwValidation")
2423  << "\n Error: one or more conditions from algorithm "
2424  << algName << " (bit number " << algBitNumber << ") "
2425  << " not found in condition map!"
2426  << "\n Add it to list of algorithms excluded from comparison"
2427  << "\n data versus emulator." << std::endl;
2428  }
2429 
2430  if (algWithExcludedCondition) {
2431 
2432  m_excludedAlgoList.push_back(algBitNumber);
2433 
2434  LogTrace("L1GtHwValidation") << "\n Algorithm " << algName
2435  << " (bit number " << algBitNumber
2436  << ") contains an excluded condition."
2437  << "\n Add it to list of algorithms excluded from comparison"
2438  << "\n data versus emulator." << std::endl;
2439 
2440  }
2441 
2442  // add algorithm triggers from ExcludeAlgoTrigByName
2443  for (std::vector<std::string>::const_iterator
2444  itExcl = m_excludeAlgoTrigByName.begin();
2445  itExcl!= m_excludeAlgoTrigByName.end(); ++itExcl) {
2446 
2447  if ((*itExcl) == algName) {
2448 
2449  m_excludedAlgoList.push_back(algBitNumber);
2450 
2451  LogTrace("L1GtHwValidation") << "\n Algorithm " << algName
2452  << " (bit number " << algBitNumber
2453  << ")\n added to list of algorithms excluded from comparison"
2454  << " \n data versus emulator by ExcludeAlgoTrigByName." << std::endl;
2455  }
2456 
2457  }
2458 
2459 
2460  // add algorithm triggers from ExcludeAlgoTrigByBit
2461  for (std::vector<int>::const_iterator
2462  itExcl = m_excludeAlgoTrigByBit.begin();
2463  itExcl!= m_excludeAlgoTrigByBit.end(); ++itExcl) {
2464 
2465  if ((*itExcl) == algBitNumber) {
2466 
2467  m_excludedAlgoList.push_back(algBitNumber);
2468 
2469  LogTrace("L1GtHwValidation") << "\n Algorithm " << algName
2470  << " (bit number " << algBitNumber
2471  << ")\n added to list of algorithms excluded from comparison"
2472  << " \n data versus emulator by ExcludeAlgoTrigByBit." << std::endl;
2473  }
2474 
2475  }
2476 
2477  }
2478 
2479 }
2480 
2481 bool L1GtHwValidation::excludedAlgo(const int& iBit) const {
2482 
2483  for (std::vector<int>::const_iterator itAlgo = m_excludedAlgoList.begin(); itAlgo
2484  != m_excludedAlgoList.end(); ++itAlgo) {
2485 
2486  if (iBit == *itAlgo) {
2487  return true;
2488  }
2489  }
2490 
2491  return false;
2492 
2493 }
LogDebug
#define LogDebug(id)
Definition: MessageLogger.h:601
edm::ParameterSet::getParameter
T getParameter(std::string const &) const
L1GtPsbWord::bData
const cms_uint16_t bData(int iB) const
get/set B_DATA_CH_IB
Definition: L1GtPsbWord.cc:323
L1GtHwValidation::m_fdlDataEmulAlgoDecision
MonitorElement * m_fdlDataEmulAlgoDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:243
L1GtHwValidation::m_fdlDataAlgoDecisionPrescaledMask_NoMatch
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Definition: L1GtHwValidation.h:226
L1GtPsbWord::bxNr
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get/set bunch cross number of the actual bx
Definition: L1GtPsbWord.h:108
L1GtFdlWord::gtTechnicalTriggerWord
const TechnicalTriggerWord & gtTechnicalTriggerWord() const
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Definition: L1GtFdlWord.h:149
L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaled_NoMatch
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L1GtHwValidation::m_l1GtTmTech
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Definition: L1GtHwValidation.h:189
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get/set board ID
Definition: L1GtPsbWord.h:66
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~L1GtHwValidation() override
Definition: L1GtHwValidation.cc:155
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get/set NoAlgo
Definition: L1GtFdlWord.h:286
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L1GtHwValidation::compareGTFE
virtual void compareGTFE(const edm::Event &, const edm::EventSetup &, const L1GtfeWord &, const L1GtfeWord &, const int)
compare the GTFE board
Definition: L1GtHwValidation.cc:823
L1GtHwValidation::matchCondCategory
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book all histograms for the module
Definition: L1GtHwValidation.cc:2263
L1GtHwValidation::comparePSB
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Definition: L1GtHwValidation.cc:1792
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pretty print the content of a L1GtfeWord
Definition: L1GtfeWord.cc:321
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Definition: L1GtHwValidation.h:182
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Definition: L1GtHwValidation.h:271
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Definition: Event.h:579
ConditionMap
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map containing the conditions
Definition: L1GtTriggerMenuFwd.h:28
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Definition: AlCaHLTBitMon_QueryRunRegistry.py:256
AlgorithmMap
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map containing the algorithms
Definition: L1GtTriggerMenuFwd.h:31
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Definition: L1GlobalTriggerReadoutSetup.h:41
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Definition: L1GtHwValidation.h:256
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iterators through map containing the conditions
Definition: L1GtTriggerMenuFwd.h:34
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excluded condition types
Definition: L1GtHwValidation.h:156
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get / set GTFE word (record) in the GT readout record
Definition: L1GlobalTriggerEvmReadoutRecord.cc:347
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get the vector of L1GtFdlWord
Definition: L1GlobalTriggerReadoutRecord.h:132
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get / set GTFE word (record) in the GT readout record
Definition: L1GlobalTriggerReadoutRecord.cc:509
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set bin label for x, y or z axis (axis=1, 2, 3 respectively)
Definition: MonitorElement.cc:942
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Definition: L1GtHwValidation.h:244
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Definition: L1GtTriggerMenu.h:106
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Definition: L1GtHwValidation.h:246
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exclude from comparison some bits with known disagreement - bit list
Definition: L1GtHwValidation.cc:2326
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get the vector of L1GtPsbWord
Definition: L1GlobalTriggerReadoutRecord.h:150
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Definition: L1GtDefinitions.cc:248
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Definition: L1GtHwValidation.h:131
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Definition: L1GtDefinitions.h:100
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Definition: L1GtTriggerMenu.h:84
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Definition: L1GtHwValidation.h:220
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Definition: L1GtHwValidation.h:238
L1GtHwValidation::compareFDL
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Definition: L1GtHwValidation.cc:1030
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get/set alternative for number of BX per board
Definition: L1GtfeWord.h:187
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Definition: L1GtHwValidation.cc:2298
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exclude algorithm triggers from comparison data - emulator by algorithm bit number ...
Definition: L1GtHwValidation.h:147
L1GtHwValidation::compareTCS
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compare the TCS board
Definition: L1GtHwValidation.cc:1973
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Definition: MonitorElement.h:166
CItAlgo
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Definition: L1GtTriggerMenuFwd.h:38
L1GtHwValidation::m_l1GtTmAlgoCacheID
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Definition: L1GtHwValidation.h:187
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Definition: L1GtHwValidation.h:257
L1GtFdlWord::bxNr
const cms_uint16_t bxNr() const
get/set BxNr - bunch cross number of the actual bx
Definition: L1GtFdlWord.h:110
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Definition: L1GtHwValidation.h:219
L1GtFdlWord::boardId
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get/set board ID
Definition: L1GtFdlWord.h:69
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Definition: L1GtHwValidation.h:225
L1GtFdlWord::printGtDecisionWord
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Definition: L1GtFdlWord.cc:345
L1GtfeWord::recordLength
const cms_uint16_t recordLength() const
get/set record length for alternative 0
Definition: L1GtfeWord.h:104
L1GtFdlWord::eventNr
const cms_uint32_t eventNr() const
get/set event number since last L1 reset generated in FDL
Definition: L1GtFdlWord.h:130
L1GtHwValidation::m_gtfeDataEmul
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histograms
Definition: L1GtHwValidation.h:213
l1GtConditionTypeStringToEnum
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Definition: L1GtDefinitions.cc:195
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MonitorElement * m_fdlDataAlgoDecisionUnprescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:224
DecisionWordExtended
std::vector< bool > DecisionWordExtended
Definition: L1GlobalTriggerReadoutSetupFwd.h:38
L1GtHwValidation::m_triggerMaskTechTrig
std::vector< unsigned int > m_triggerMaskTechTrig
Definition: L1GtHwValidation.h:193
iEvent
int iEvent
Definition: GenABIO.cc:230
L1GtHwValidation::m_fdlDataEmulAlgoDecisionMask
MonitorElement * m_fdlDataEmulAlgoDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:247
l1GtObjectStringToEnum
L1GtObject l1GtObjectStringToEnum(const std::string &)
Definition: L1GtObject.cc:24
L1GtPsbWord::aData
const cms_uint16_t aData(int iA) const
get/set A_DATA_CH_IA
Definition: L1GtPsbWord.cc:228
DQMStore::IBooker::setCurrentFolder
void setCurrentFolder(std::string const &fullpath)
Definition: DQMStore.cc:268
L1GtHwValidation::m_excludedL1GtObject
std::vector< L1GtObject > m_excludedL1GtObject
excluded L1 GT objects
Definition: L1GtHwValidation.h:159
electrons_cff.objType
objType
Definition: electrons_cff.py:414
L1GtHwValidation::m_fdlDataAlgoDecisionPrescaled_NoMatch
MonitorElement * m_fdlDataAlgoDecisionPrescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:223
L1GtTriggerMask::gtTriggerMask
const std::vector< unsigned int > & gtTriggerMask() const
get the trigger mask
Definition: L1GtTriggerMask.h:51
L1GtHwValidation::m_excludeAlgoTrigByName
std::vector< std::string > m_excludeAlgoTrigByName
exclude algorithm triggers from comparison data - emulator by algorithm name
Definition: L1GtHwValidation.h:144
DecisionWord
std::vector< bool > DecisionWord
typedefs
Definition: L1GlobalTriggerReadoutSetupFwd.h:34
L1GtHwValidation::m_excludedAlgorithmsAgreement
MonitorElement * m_excludedAlgorithmsAgreement
Definition: L1GtHwValidation.h:264
L1GtHwValidation::m_l1GtTmAlgo
const L1GtTriggerMask * m_l1GtTmAlgo
trigger masks
Definition: L1GtHwValidation.h:186
L1GtHwValidation::m_agree
bool m_agree
internal members
Definition: L1GtHwValidation.h:199
L1GtHwValidation::m_l1GtEmulDaqInputTag
edm::InputTag m_l1GtEmulDaqInputTag
input tag for the L1 GT emulator DAQ record
Definition: L1GtHwValidation.h:128
L1GtHwValidation::m_fdlDataEmulTechDecision
MonitorElement * m_fdlDataEmulTechDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:260
L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:239
L1GtFdlWord::bxInEvent
const int bxInEvent() const
get/set bunch cross in the GT event record
Definition: L1GtFdlWord.h:90
L1GtfeWord::totalTriggerNr
const cms_uint32_t totalTriggerNr() const
get/set total number of L1A sent since start of run
Definition: L1GtfeWord.h:211
L1GtFdlWord::printGtDecisionWordExtended
void printGtDecisionWordExtended(std::ostream &myCout) const
Definition: L1GtFdlWord.cc:503
DQMStore::IBooker::book1D
MonitorElement * book1D(Args &&...args)
Definition: DQMStore.h:106
L1GtConditionCategory
L1GtConditionCategory
condition categories
Definition: L1GtDefinitions.h:130
L1GtHwValidation::compareEvmRecord
virtual void compareEvmRecord(const edm::Event &, const edm::EventSetup &)
L1 GT EVM record comparison.
Definition: L1GtHwValidation.cc:2147
L1GtHwValidation::m_fdlDataTechDecision_Err
MonitorElement * m_fdlDataTechDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:254
L1GtHwValidation::matchCondType
bool matchCondType(const L1GtConditionType &, const L1GtConditionType &)
Definition: L1GtHwValidation.cc:2281
L1GtHwValidation::m_fdlDataAlgoDecision
MonitorElement * m_fdlDataAlgoDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:218
TechnicalTriggerWord
std::vector< bool > TechnicalTriggerWord
technical trigger bits (64 bits)
Definition: L1GlobalTriggerReadoutSetupFwd.h:41
L1GtHwValidation::L1GtHwValidation
L1GtHwValidation(const edm::ParameterSet &)
Definition: L1GtHwValidation.cc:52
L1GlobalTriggerReadoutSetup::NumberPhysTriggers
static const unsigned int NumberPhysTriggers
Definition: L1GlobalTriggerReadoutSetup.h:39
l1GtConditionCategoryStringToEnum
L1GtConditionCategory l1GtConditionCategoryStringToEnum(const std::string &)
Definition: L1GtDefinitions.cc:229
L1GtHwValidation::m_l1GtDataDaqInputToken_
edm::EDGetTokenT< L1GlobalTriggerReadoutRecord > m_l1GtDataDaqInputToken_
Definition: L1GtHwValidation.h:282
L1GtHwValidation::TotalBxInEvent
static const int TotalBxInEvent
Definition: L1GtHwValidation.h:207
L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaled
MonitorElement * m_fdlEmulAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:232
L1GtPsbWord::localBxNr
const cms_uint16_t localBxNr() const
get/set local bunch cross number of the actual bx
Definition: L1GtPsbWord.h:178
edm::HandleBase::isValid
bool isValid() const
Definition: HandleBase.h:74
L1GtfeWord::activeBoards
const cms_uint16_t activeBoards() const
get/set boards contributing to EVM respectively DAQ record
Definition: L1GtfeWord.h:163
LogTrace
#define LogTrace(id)
Definition: MessageLogger.h:602
L1GtHwValidation::m_l1GtMenu
const L1GtTriggerMenu * m_l1GtMenu
trigger menu
Definition: L1GtHwValidation.h:172
L1GtHwValidation::m_fdlEmulAlgoDecision_Err
MonitorElement * m_fdlEmulAlgoDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:240
L1GtfeWord::bxNr
const cms_uint16_t bxNr() const
get/set bunch cross number as counted in the GTFE board
Definition: L1GtfeWord.h:122
L1GtHwValidation::m_l1GtEmulEvmInputToken_
edm::EDGetTokenT< L1GlobalTriggerEvmReadoutRecord > m_l1GtEmulEvmInputToken_
Definition: L1GtHwValidation.h:285
L1GtFdlWord::print
void print(std::ostream &myCout) const
pretty print the content of a L1GtFdlWord
Definition: L1GtFdlWord.cc:766
L1GtPsbWord::print
void print(std::ostream &myCout) const
pretty print
Definition: L1GtPsbWord.cc:453
l1GtConditionTypeEnumToString
std::string l1GtConditionTypeEnumToString(const L1GtConditionType &)
Definition: L1GtDefinitions.cc:215
L1GtfeWord::boardId
const cms_uint16_t boardId() const
get/set board ID
Definition: L1GtfeWord.h:65
L1GtHwValidation::m_l1GtPfAlgoCacheID
unsigned long long m_l1GtPfAlgoCacheID
Definition: L1GtHwValidation.h:177
L1GtPsbWord::eventNr
const cms_uint32_t eventNr() const
get/set event number since last L1 reset generated in PSB
Definition: L1GtPsbWord.h:129
L1GtHwValidation::m_fdlDataTechDecisionMask
MonitorElement * m_fdlDataTechDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:253
L1GtHwValidation::m_l1GtDataDaqInputTag
edm::InputTag m_l1GtDataDaqInputTag
input tag for the L1 GT hardware DAQ record
Definition: L1GtHwValidation.h:122
L1GtHwValidation::m_fdlDataAlgoDecision_NoMatch
MonitorElement * m_fdlDataAlgoDecision_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:222
L1GtHwValidation::m_fdlDataEmul
MonitorElement * m_fdlDataEmul[TotalBxInEvent][NumberOfGtRecords]
FDL (0 for DAQ, 1 for EVM record)
Definition: L1GtHwValidation.h:216
L1GtFdlWord::gtPrescaleFactorIndexAlgo
const cms_uint16_t gtPrescaleFactorIndexAlgo() const
Definition: L1GtFdlWord.h:267
L1GtHwValidation::m_fdlDataEmul_Err
MonitorElement * m_fdlDataEmul_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:249
L1GtPrescaleFactors::gtPrescaleFactors
const std::vector< std::vector< int > > & gtPrescaleFactors() const
get the prescale factors by reference
Definition: L1GtPrescaleFactors.h:49
L1GtHwValidation::m_l1GtEmulDaqInputToken_
edm::EDGetTokenT< L1GlobalTriggerReadoutRecord > m_l1GtEmulDaqInputToken_
Definition: L1GtHwValidation.h:283
L1GtHwValidation::m_excludedCondCategory
std::vector< L1GtConditionCategory > m_excludedCondCategory
excluded condition categories
Definition: L1GtHwValidation.h:153
L1GtHwValidation::m_myCoutStream
std::ostringstream m_myCoutStream
Definition: L1GtHwValidation.h:163
L1GtHwValidation::bookHistograms
void bookHistograms(DQMStore::IBooker &ibooker, const edm::Run &, const edm::EventSetup &) override
Definition: L1GtHwValidation.cc:165
L1GtPsbWord::NumberBData
static const int NumberBData
Definition: L1GtPsbWord.h:35
L1GtHwValidation::m_nrDataEventError
int m_nrDataEventError
counters
Definition: L1GtHwValidation.h:166
L1GtHwValidation::m_fdlEmulAlgoDecisionMask_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionMask_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:237
L1GtPsbWord::bxInEvent
const int bxInEvent() const
get/set bunch cross in the GT event record
Definition: L1GtPsbWord.h:87
L1GtFdlWord::gtDecisionWord
const DecisionWord & gtDecisionWord() const
get/set/print algorithms bits (decision word)
Definition: L1GtFdlWord.h:171
L1GtHwValidation::m_l1GtTmTechCacheID
unsigned long long m_l1GtTmTechCacheID
Definition: L1GtHwValidation.h:190
L1GtHwValidation::compareGt_Gct
virtual void compareGt_Gct(const edm::Event &, const edm::EventSetup &)
Definition: L1GtHwValidation.cc:2237
L1GtHwValidation::m_fdlEmulTechDecision_Err
MonitorElement * m_fdlEmulTechDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:258
L1GtPsbWord::NumberAData
static const int NumberAData
Definition: L1GtPsbWord.h:34
edm
HLT enums.
Definition: AlignableModifier.h:17
L1GtHwValidation::m_l1GctDataInputTag
edm::InputTag m_l1GctDataInputTag
input tag for the L1 GCT hardware record
Definition: L1GtHwValidation.h:134
edm::EventSetup::get
T get() const
Definition: EventSetup.h:62
L1GtHwValidation::m_excludeCondCategTypeObject
std::vector< edm::ParameterSet > m_excludeCondCategTypeObject
Definition: L1GtHwValidation.h:141
L1GtFdlWord::printGtTechnicalTriggerWord
void printGtTechnicalTriggerWord(std::ostream &myCout) const
Definition: L1GtFdlWord.cc:271
L1GtHwValidation::m_fdlDataEmulAlgoDecision_Err
MonitorElement * m_fdlDataEmulAlgoDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:248
L1GtfeWord::setupVersion
const cms_uint32_t setupVersion() const
get/set setup version
Definition: L1GtfeWord.h:140
L1GtTriggerMenu::gtAlgorithmMap
const AlgorithmMap & gtAlgorithmMap() const
get / set the algorithm map (by name)
Definition: L1GtTriggerMenu.h:241
L1GtHwValidation::NumberOfGtRecords
static const int NumberOfGtRecords
Definition: L1GtHwValidation.h:208
L1GtHwValidation::m_fdlDataTechDecision
MonitorElement * m_fdlDataTechDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:252
L1GtHwValidation::m_fdlEmulAlgoDecision
MonitorElement * m_fdlEmulAlgoDecision[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:230
L1GtHwValidation::m_prescaleFactorsTechTrig
const std::vector< std::vector< int > > * m_prescaleFactorsTechTrig
Definition: L1GtHwValidation.h:183
L1GtHwValidation::m_fdlEmulAlgoDecision_NoMatch
MonitorElement * m_fdlEmulAlgoDecision_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:234
L1GtFdlWord::gtDecisionWordExtended
const DecisionWordExtended & gtDecisionWordExtended() const
get/set extended algorithms bits (extended decision word)
Definition: L1GtFdlWord.h:203
L1GtHwValidation::m_fdlDataEmulTechDecisionMask
MonitorElement * m_fdlDataEmulTechDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:261
L1GtHwValidation::dqmBeginRun
void dqmBeginRun(const edm::Run &, const edm::EventSetup &) override
Definition: L1GtHwValidation.cc:161
L1GtHwValidation::m_fdlDataAlgoDecisionMask
MonitorElement * m_fdlDataAlgoDecisionMask[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:221
L1GtHwValidation::compareDaqRecord
virtual void compareDaqRecord(const edm::Event &, const edm::EventSetup &)
L1 GT DAQ record comparison.
Definition: L1GtHwValidation.cc:1979
L1GtfeWord::recordLength1
const cms_uint16_t recordLength1() const
get/set record length for alternative 1
Definition: L1GtfeWord.h:85
str
#define str(s)
Definition: TestProcessor.cc:47
L1GtHwValidation::m_triggerMaskAlgoTrig
std::vector< unsigned int > m_triggerMaskAlgoTrig
Definition: L1GtHwValidation.h:192
edm::ESHandle::product
T const * product() const
Definition: ESHandle.h:86
L1GtHwValidation::m_excludedAlgoList
std::vector< int > m_excludedAlgoList
Definition: L1GtHwValidation.h:279
L1GtHwValidation::m_fdlDataEmulTechDecision_Err
MonitorElement * m_fdlDataEmulTechDecision_Err[NumberOfGtRecords]
Definition: L1GtHwValidation.h:262
L1GtHwValidation::m_fdlEmulAlgoDecisionPrescaled_NoMatch
MonitorElement * m_fdlEmulAlgoDecisionPrescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:235
L1GtHwValidation::analyze
void analyze(const edm::Event &, const edm::EventSetup &) override
Definition: L1GtHwValidation.cc:2245
nanoDQM_cff.prescaleFactor
prescaleFactor
Definition: nanoDQM_cff.py:35
L1GtFdlWord::localBxNr
const cms_uint16_t localBxNr() const
get/set local bunch cross number of the actual bx
Definition: L1GtFdlWord.h:372
L1GtHwValidation::m_l1GtPfAlgo
const L1GtPrescaleFactors * m_l1GtPfAlgo
prescale factors
Definition: L1GtHwValidation.h:176
L1GtHwValidation::m_l1GtDataEvmInputTag
edm::InputTag m_l1GtDataEvmInputTag
input tag for the L1 GT hardware EVM record
Definition: L1GtHwValidation.h:125
edm::Run
Definition: Run.h:44
L1GtFdlWord::finalOR
const cms_uint16_t finalOR() const
get/set "Final OR" bits
Definition: L1GtFdlWord.h:306
L1GtHwValidation::m_l1GtPfTechCacheID
unsigned long long m_l1GtPfTechCacheID
Definition: L1GtHwValidation.h:180
L1GtHwValidation::m_fdlEmulAlgoDecisionPrescaled
MonitorElement * m_fdlEmulAlgoDecisionPrescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:231
L1GtHwValidation::excludedAlgo
bool excludedAlgo(const int &) const
exclusion status for algorithm with bit i
Definition: L1GtHwValidation.cc:2481
L1GlobalTriggerEvmReadoutRecord::gtFdlVector
const std::vector< L1GtFdlWord > gtFdlVector() const
get the vector of L1GtFdlWord
Definition: L1GlobalTriggerEvmReadoutRecord.h:105
L1GtHwValidation::m_dirName
std::string m_dirName
directory name for L1Extra plots
Definition: L1GtHwValidation.h:137
L1GtHwValidation::m_fdlDataEmulAlgoDecisionUnprescaled
MonitorElement * m_fdlDataEmulAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords]
Definition: L1GtHwValidation.h:245
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