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SiStripSpyDigiConverter.cc
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1 #include <vector>
2 
5 
11 
14 
17 
20 
21 namespace sistrip {
22 
23  std::auto_ptr<SpyDigiConverter::DSVRawDigis>
25  std::vector<uint32_t> * pAPVAddresses,
26  const bool discardDigisWithAPVAddrErr,
27  const sistrip::SpyUtilities::FrameQuality & aQuality,
28  const uint16_t expectedPos)
29  {
30  // Data is already sorted so push back fast into vector to avoid sorts and create DSV later
31  std::vector<DetSetRawDigis> outputData;
32  outputData.reserve(inputScopeDigis->size());
33 
34  //APV address vector indexed by fedid, majority value written.
35  pAPVAddresses->resize(sistrip::FED_ID_MAX+1,0);
36  std::vector<uint16_t> lAddrVec;
37  lAddrVec.reserve(2*sistrip::FEDCH_PER_FED);
38  uint16_t lPreviousFedId = 0;
39  std::vector<uint16_t> lHeaderBitVec;
40  lHeaderBitVec.reserve(sistrip::FEDCH_PER_FED);
41 
42 
43  //local DSVRawDigis per FED
44  std::vector<DSVRawDigis::const_iterator> lFedScopeDigis;
45  lFedScopeDigis.reserve(sistrip::FEDCH_PER_FED);
46 
47  // Loop over channels in input collection
48  DSVRawDigis::const_iterator inputChannel = inputScopeDigis->begin();
49  const DSVRawDigis::const_iterator endChannels = inputScopeDigis->end();
50  bool hasBeenProcessed = false;
51 
52  for (; inputChannel != endChannels; ++inputChannel) {
53 
54  // Fill frame parameters. Second parameter is to print debug info (if logDebug enabled....)
56 
57  const uint32_t lFedIndex = inputChannel->detId();
58  const uint16_t fedId = static_cast<uint16_t>(lFedIndex/sistrip::FEDCH_PER_FED);
59  const uint16_t fedCh = static_cast<uint16_t>(lFedIndex%sistrip::FEDCH_PER_FED);
60 
61  if (lPreviousFedId == 0) {
62  lPreviousFedId = fedId;
63  }
64 
65  //print out warning only for non-empty frames....
66  if (!sistrip::SpyUtilities::isValid(lFrame,aQuality,expectedPos)){
67  //print out only for non-empty frames, else too many prints...
69  edm::LogWarning("SiStripSpyDigiConverter") << " FED ID: " << fedId << ", channel: " << fedCh << std::endl
71  std::string(" -- Invalid Frame ")
72  );
73  }
74 
75  continue;
76  }
77 
78  //fill local vectors per FED
79  if (fedId == lPreviousFedId) {
80  if (hasBeenProcessed) hasBeenProcessed = false;
81  }
82  if (fedId != lPreviousFedId) {
83  SpyDigiConverter::processFED(lPreviousFedId,
84  discardDigisWithAPVAddrErr,
85  pAPVAddresses,
86  outputData,
87  lAddrVec,
88  lHeaderBitVec,
89  lFedScopeDigis
90  );
91  lPreviousFedId = fedId;
92  hasBeenProcessed = true;
93  }
94  lFedScopeDigis.push_back(inputChannel);
95  lAddrVec.push_back(lFrame.apvAddress.first);
96  lAddrVec.push_back(lFrame.apvAddress.second);
97  lHeaderBitVec.push_back(lFrame.firstHeaderBit);
98 
99 
100  } // end of loop over channels.
101 
102  //process the last one if not already done.
103  if (!hasBeenProcessed) {
104  SpyDigiConverter::processFED(lPreviousFedId,
105  discardDigisWithAPVAddrErr,
106  pAPVAddresses,
107  outputData,
108  lAddrVec,
109  lHeaderBitVec,
110  lFedScopeDigis
111  );
112  }
113 
114  //return DSV of output
115  return std::auto_ptr<DSVRawDigis>( new DSVRawDigis(outputData, true) );
116 
117  } // end of SpyDigiConverter::extractPayloadDigis method
118 
119 
120  void SpyDigiConverter::processFED(const uint16_t aPreviousFedId,
121  const bool discardDigisWithAPVAddrErr,
122  std::vector<uint32_t> * pAPVAddresses,
123  std::vector<DetSetRawDigis> & outputData,
124  std::vector<uint16_t> & aAddrVec,
125  std::vector<uint16_t> & aHeaderBitVec,
126  std::vector<DSVRawDigis::const_iterator> & aFedScopeDigis
127  )
128  {
129 
130  //extract majority address
131  uint32_t lMaj = sistrip::SpyUtilities::findMajorityValue(aAddrVec,aPreviousFedId).first;
132  if (pAPVAddresses) (*pAPVAddresses)[aPreviousFedId] = lMaj;
133 
134  //loop over iterators and fill payload
135  std::vector<DSVRawDigis::const_iterator>::iterator lIter;
136  unsigned int lCh = 0;
137  for (lIter = aFedScopeDigis.begin(); lIter != aFedScopeDigis.end(); ++lIter,++lCh) {
138 
139  //discard if APV address different from majority.
140  //Keep if only one of them is wrong: the other APV might be alright ??
141 
142  if ( discardDigisWithAPVAddrErr &&
143  aAddrVec[2*lCh] != lMaj &&
144  aAddrVec[2*lCh+1] != lMaj ) {
145  continue;
146  }
147 
148  DetSetRawDigis::const_iterator iDigi = (*lIter)->begin();
149  const DetSetRawDigis::const_iterator endOfChannel = (*lIter)->end();
150 
151  if (iDigi == endOfChannel) {
152  continue;
153  }
154 
155  //header starts in sample firstHeaderBit and is 18+6 samples long
156  const DetSetRawDigis::const_iterator payloadBegin = iDigi+aHeaderBitVec[lCh]+24;
157  const DetSetRawDigis::const_iterator payloadEnd = payloadBegin + STRIPS_PER_FEDCH;
158 
159 
160  // Copy data into output collection
161  // Create new detSet with same key (in this case it is the fedKey, not detId)
162  outputData.push_back( DetSetRawDigis((*lIter)->detId()) );
163  std::vector<SiStripRawDigi>& outputDetSetData = outputData.back().data;
164  outputDetSetData.resize(STRIPS_PER_FEDCH);
165  std::vector<SiStripRawDigi>::iterator outputBegin = outputDetSetData.begin();
166  std::copy(payloadBegin, payloadEnd, outputBegin);
167 
168  }
169 
170  aFedScopeDigis.clear();
171  aAddrVec.clear();
172  aHeaderBitVec.clear();
173 
174  aAddrVec.reserve(2*sistrip::FEDCH_PER_FED);
175  aHeaderBitVec.reserve(sistrip::FEDCH_PER_FED);
176  aFedScopeDigis.reserve(sistrip::FEDCH_PER_FED);
177 
178 
179  }
180 
181 
182 
183 
184  std::auto_ptr<SpyDigiConverter::DSVRawDigis> SpyDigiConverter::reorderDigis(const DSVRawDigis* inputPayloadDigis)
185  {
186  // Data is already sorted so push back fast into vector to avoid sorts and create DSV later
187  std::vector<DetSetRawDigis> outputData;
188  outputData.reserve(inputPayloadDigis->size());
189 
190  // Loop over channels in input collection
191  for (DSVRawDigis::const_iterator inputChannel = inputPayloadDigis->begin(); inputChannel != inputPayloadDigis->end(); ++inputChannel) {
192  const std::vector<SiStripRawDigi>& inputDetSetData = inputChannel->data;
193  // Create new detSet with same key (in this case it is the fedKey, not detId)
194  outputData.push_back( DetSetRawDigis(inputChannel->detId()) );
195  std::vector<SiStripRawDigi>& outputDetSetData = outputData.back().data;
196  outputDetSetData.resize(STRIPS_PER_FEDCH);
197  // Copy the data into the output vector reordering
198  for (uint16_t readoutOrderStripIndex = 0; readoutOrderStripIndex < inputDetSetData.size(); ++readoutOrderStripIndex) {
199  const uint16_t physicalOrderStripIndex = FEDStripOrdering::physicalOrderForStripInChannel(readoutOrderStripIndex);
200  outputDetSetData.at(physicalOrderStripIndex) = inputDetSetData.at(readoutOrderStripIndex);
201  }
202  }
203 
204  //return DSV of output
205  return std::auto_ptr<DSVRawDigis>( new DSVRawDigis(outputData,true) );
206  } // end of SpyDigiConverter::reorderDigis method.
207 
208  std::auto_ptr<SpyDigiConverter::DSVRawDigis>
209  SpyDigiConverter::mergeModuleChannels(const DSVRawDigis* inputPhysicalOrderChannelDigis,
210  const SiStripFedCabling& cabling)
211  {
212  // Create filler for detSetVector to create output (with maximum number of DetSets and digis)
213  uint16_t nFeds = static_cast<uint16_t>( FED_ID_MAX - FED_ID_MIN + 1);
214 
216  // Loop over FEDs in cabling
217  std::vector<uint16_t>::const_iterator iFed = cabling.feds().begin();
218  const std::vector<uint16_t>::const_iterator endFeds = cabling.feds().end();
219  for (; iFed != endFeds; ++iFed) {
220  // Loop over cabled channels
221  const std::vector<FedChannelConnection>& conns = cabling.connections(*iFed);
222  std::vector<FedChannelConnection>::const_iterator iConn = conns.begin();
223  const std::vector<FedChannelConnection>::const_iterator endConns = conns.end();
224  for (; iConn != endConns; ++iConn) {
225  // Skip channels not connected to a detector.
226  if (!iConn->isConnected()) continue;
227  if (iConn->detId() == sistrip::invalid32_) continue;
228 
229  // Find the data from the input collection
230  const uint32_t fedIndex = SiStripFedKey::fedIndex(iConn->fedId(),iConn->fedCh());
231  const DSVRawDigis::const_iterator iDetSet = inputPhysicalOrderChannelDigis->find(fedIndex);
232  if (iDetSet == inputPhysicalOrderChannelDigis->end()) {
233  // NOTE: It will display this warning if channel hasn't been unpacked...
234  // Will comment out for now.
235  //edm::LogWarning("SiStripSpyDigiConverter") << "No data found for FED ID: " << iConn->fedId() << " channel: " << iConn->fedCh();
236  continue;
237  }
238 
239  // Start a new channel indexed by the detId in the filler
240  dsvFiller.newChannel(iConn->detId(),iConn->apvPairNumber()*STRIPS_PER_FEDCH);
241 
242  // Add the data
243  DetSetRawDigis::const_iterator iDigi = iDetSet->begin();
244  const DetSetRawDigis::const_iterator endDetSetDigis = iDetSet->end();
245  for (; iDigi != endDetSetDigis; ++iDigi) {
246  dsvFiller.addItem(*iDigi);
247  } // end of loop over the digis.
248  } // end of loop over channels.
249  } // end of loop over FEDs
250 
251  return dsvFiller.createDetSetVector();
252  } // end of SpyDigiConverter::mergeModuleChannels method.
253 
254 
255 
256 } // end of sistrip namespace.
static uint8_t physicalOrderForStripInChannel(const uint8_t readoutOrderStripIndexInChannel)
static const uint16_t FED_ID_MIN
const std::vector< uint16_t > & feds() const
iterator find(det_id_type id)
Definition: DetSetVector.h:285
static const bool isValid(const Frame &aFrame, const FrameQuality &aQuality, const uint16_t aExpectedPos)
static const uint32_t invalid32_
Definition: Constants.h:16
static std::auto_ptr< DSVRawDigis > mergeModuleChannels(const DSVRawDigis *inputPhysicalOrderChannelDigis, const SiStripFedCabling &cabling)
void newChannel(const uint32_t key, const uint16_t firstItem=0)
DSVRawDigis::detset DetSetRawDigis
static const uint16_t SPY_SAMPLES_PER_CHANNEL
std::pair< uint8_t, uint8_t > apvAddress
static uint32_t fedIndex(const uint16_t &fed_id, const uint16_t &fed_ch)
std::auto_ptr< edm::DetSetVector< T > > createDetSetVector()
static const Frame extractFrameInfo(const edm::DetSetVector< SiStripRawDigi >::detset &channelDigis, bool aPrintDebug=false)
static void processFED(const uint16_t aPreviousFedId, const bool discardDigisWithAPVAddrErr, std::vector< uint32_t > *pAPVAddresses, std::vector< DetSetRawDigis > &outputData, std::vector< uint16_t > &aAddrVec, std::vector< uint16_t > &aHeaderBitVec, std::vector< DSVRawDigis::const_iterator > &aFedScopeDigis)
static std::auto_ptr< DSVRawDigis > extractPayloadDigis(const DSVRawDigis *inputScopeDigis, std::vector< uint32_t > *pAPVAddresses, const bool discardDigisWithAPVAddrErr, const sistrip::SpyUtilities::FrameQuality &aQuality, const uint16_t expectedPos)
Extract frames from the scope digis.
static std::auto_ptr< DSVRawDigis > reorderDigis(const DSVRawDigis *inputPayloadDigis)
iterator end()
Return the off-the-end iterator.
Definition: DetSetVector.h:356
size_type size() const
Return the number of contained DetSets.
Definition: DetSetVector.h:278
static std::pair< uint16_t, uint32_t > findMajorityValue(std::vector< uint16_t > &values, const uint16_t aFedId=0)
static const uint16_t STRIPS_PER_FEDCH
edm::DetSetVector< SiStripRawDigi > DSVRawDigis
Constants and enumerated types for FED/FEC systems.
Contains cabling info at the device level, including DetId, APV pair numbers, hardware addresses...
static const uint16_t FEDCH_PER_FED
iterator begin()
Return an iterator to the first DetSet.
Definition: DetSetVector.h:341
static const uint16_t FED_ID_MAX
collection_type::const_iterator const_iterator
Definition: DetSet.h:34
static std::string print(const Frame &aFrame, std::string aErr)
collection_type::const_iterator const_iterator
Definition: DetSetVector.h:106
const std::vector< FedChannelConnection > & connections(uint16_t fed_id) const