Reference Manual

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00001 #include "CondFormats/L1TObjects/interface/L1MuCSCTFConfiguration.h"
00002 #include <sstream>
00003 #include <iostream>
00004 #include "FWCore/MessageLogger/interface/MessageLogger.h"
00005 
00006 edm::ParameterSet L1MuCSCTFConfiguration::parameters(int sp) const {
00007   
00008   LogDebug("L1MuCSCTFConfiguration") << "SP:"<<int(sp)<< std::endl;
00009   
00010   edm::ParameterSet pset;
00011   if(sp>=12) return pset;
00012 
00013   // ------------------------------------------------------
00014   // core configuration
00015   // by default everything is disabled: we need to set them
00016   // coincidence and singles
00017   bool run_core        = 0;
00018   bool trigger_on_ME1a = 0;
00019   bool trigger_on_ME1b = 0;
00020   bool trigger_on_ME2  = 0;
00021   bool trigger_on_ME3  = 0;
00022   bool trigger_on_ME4  = 0;
00023   bool trigger_on_MB1a = 0;
00024   bool trigger_on_MB1d = 0;
00025 
00026   unsigned int BXAdepth   = 0;
00027   unsigned int useDT      = 0;
00028   unsigned int widePhi    = 0;
00029   unsigned int PreTrigger = 0;
00030   // ------------------------------------------------------
00031 
00032   // ------------------------------------------------------
00033   // these are very important parameters.
00034   // Double check with Alex
00035   unsigned int CoreLatency = 7;
00036   bool rescaleSinglesPhi = 1;
00037 
00038   // ask Alex if use or remove them or what
00039   bool AllowALCTonly = 0;
00040   bool AllowCLCTonly = 0;
00041 
00042   // other useful parameters in general not set in the OMDS  
00043   unsigned int QualityEnableME1a = 0xFFFF;
00044   unsigned int QualityEnableME1b = 0xFFFF;
00045   unsigned int QualityEnableME1c = 0xFFFF;
00046   unsigned int QualityEnableME1d = 0xFFFF;
00047   unsigned int QualityEnableME1e = 0xFFFF;
00048   unsigned int QualityEnableME1f = 0xFFFF;
00049   unsigned int QualityEnableME2a = 0xFFFF;
00050   unsigned int QualityEnableME2b = 0xFFFF;
00051   unsigned int QualityEnableME2c = 0xFFFF;
00052   unsigned int QualityEnableME3a = 0xFFFF;
00053   unsigned int QualityEnableME3b = 0xFFFF;
00054   unsigned int QualityEnableME3c = 0xFFFF;
00055   unsigned int QualityEnableME4a = 0xFFFF;
00056   unsigned int QualityEnableME4b = 0xFFFF;
00057   unsigned int QualityEnableME4c = 0xFFFF;
00058                
00059   unsigned int kill_fiber = 0;
00060   unsigned int singlesTrackOutput = 1;
00061   // ------------------------------------------------------
00062 
00063   
00064   //initialization of the DAT_ETA registers with default values
00065   //the DAT_ETA registers meaning are explained at Table 2 of
00066   //http://www.phys.ufl.edu/~uvarov/SP05/LU-SP_ReferenceGuide_090915_Update.pdf
00067   std::vector<unsigned int> etamin(8), etamax(8), etawin(7);
00068 
00069   unsigned int mindetap      = 8;
00070   unsigned int mindetap_halo = 8;
00071 
00072   etamin[0] = 22;
00073   etamin[1] = 22;
00074   etamin[2] = 14;
00075   etamin[3] = 14;
00076   etamin[4] = 14;
00077   etamin[5] = 14;
00078   etamin[6] = 10;
00079   etamin[7] = 22;
00080 
00081   unsigned int mindeta12_accp  =  8; 
00082   unsigned int mindeta13_accp  = 19;
00083   unsigned int mindeta112_accp = 19;
00084   unsigned int mindeta113_accp = 30;
00085 
00086   etamax[0] = 127;
00087   etamax[1] = 127;
00088   etamax[2] = 127;
00089   etamax[3] = 127;
00090   etamax[4] = 127;
00091   etamax[5] =  24;
00092   etamax[6] =  24;
00093   etamax[7] = 127;
00094 
00095   unsigned int maxdeta12_accp  = 14;
00096   unsigned int maxdeta13_accp  = 25;
00097   unsigned int maxdeta112_accp = 25;
00098   unsigned int maxdeta113_accp = 36;
00099 
00100   etawin[0] = 4;
00101   etawin[1] = 4;
00102   etawin[2] = 4;
00103   etawin[3] = 4;
00104   etawin[4] = 4;
00105   etawin[5] = 4;
00106   etawin[6] = 4;
00107 
00108   unsigned int maxdphi12_accp  = 64;
00109   unsigned int maxdphi13_accp  = 64;
00110   unsigned int maxdphi112_accp = 64;
00111   unsigned int maxdphi113_accp = 64;
00112                                
00113   unsigned int mindphip      = 128;
00114   unsigned int mindphip_halo = 128;
00115                
00116   unsigned int straightp =   60;
00117   unsigned int curvedp   =  200;
00118   
00119   unsigned int mbaPhiOff =    0;
00120   // this differ from the default value in the documentation because during
00121   // craft 09 it mbbPhiOff, as well as mbaPhiOff were not existing, thus set to 0 (they are offsets)
00122   // and for backward compatibility it needs to be set to 0. Anyway mbbPhiOff since its introduction in the
00123   // core will have to be ALWAYS part of the configuration, so it won't be never initialized to the
00124   // default value 2048.
00125   unsigned int mbbPhiOff =    0;
00126 
00127   int eta_cnt=0;
00128 
00129   // default firmware versions (the ones used from run 132440)
00130   unsigned int firmwareSP=20100210;
00131   unsigned int firmwareFA=20090521;
00132   unsigned int firmwareDD=20090521;
00133   unsigned int firmwareVM=20090521;
00134 
00135   // default printout
00136   LogDebug("L1MuCSCTFConfiguration") << "\nCORE CONFIGURATION  DEFAULT VALUES" 
00137                                      << "\nrun_core="        << run_core       
00138                                      << "\ntrigger_on_ME1a=" << trigger_on_ME1a
00139                                      << "\ntrigger_on_ME1b=" << trigger_on_ME1b
00140                                      << "\ntrigger_on_ME2="  << trigger_on_ME2 
00141                                      << "\ntrigger_on_ME3="  << trigger_on_ME3 
00142                                      << "\ntrigger_on_ME4="  << trigger_on_ME4 
00143                                      << "\ntrigger_on_MB1a=" << trigger_on_MB1a
00144                                      << "\ntrigger_on_MB1d=" << trigger_on_MB1d
00145 
00146                                      << "\nBXAdepth="   << BXAdepth   
00147                                      << "\nuseDT="      << useDT      
00148                                      << "\nwidePhi="    << widePhi    
00149                                      << "\nPreTrigger=" << PreTrigger 
00150       
00151                                      << "\nCoreLatency="<< CoreLatency
00152                                      << "\nrescaleSinglesPhi=" << rescaleSinglesPhi 
00153 
00154                                      << "\n\nVARIOUS CONFIGURATION PARAMETERS DEFAULT VALUES" 
00155                                      << "\nAllowALCTonly=" <<  AllowALCTonly 
00156                                      << "\nAllowCLCTonly=" <<  AllowCLCTonly 
00157 
00158                                      << "\nQualityEnableME1a=" << QualityEnableME1a 
00159                                      << "\nQualityEnableME1b=" << QualityEnableME1b 
00160                                      << "\nQualityEnableME1c=" << QualityEnableME1c 
00161                                      << "\nQualityEnableME1d=" << QualityEnableME1d 
00162                                      << "\nQualityEnableME1e=" << QualityEnableME1e 
00163                                      << "\nQualityEnableME1f=" << QualityEnableME1f 
00164                                      << "\nQualityEnableME2a=" << QualityEnableME2a 
00165                                      << "\nQualityEnableME2b=" << QualityEnableME2b 
00166                                      << "\nQualityEnableME2c=" << QualityEnableME2c 
00167                                      << "\nQualityEnableME3a=" << QualityEnableME3a 
00168                                      << "\nQualityEnableME3b=" << QualityEnableME3b 
00169                                      << "\nQualityEnableME3c=" << QualityEnableME3c 
00170                                      << "\nQualityEnableME4a=" << QualityEnableME4a 
00171                                      << "\nQualityEnableME4b=" << QualityEnableME4b 
00172                                      << "\nQualityEnableME4c=" << QualityEnableME4c 
00173                                      
00174                                      << "\nkill_fiber="         << kill_fiber 
00175                                      << "\nsinglesTrackOutput=" << singlesTrackOutput 
00176 
00177                                      << "\n\nDEFAULT VALUES FOR DAT_ETA" 
00178                                      << "\nmindetap     =" << mindetap      
00179                                      << "\nmindetap_halo=" << mindetap_halo 
00180       
00181                                      << "\netamin[0]=" << etamin[0] 
00182                                      << "\netamin[1]=" << etamin[1] 
00183                                      << "\netamin[2]=" << etamin[2] 
00184                                      << "\netamin[3]=" << etamin[3] 
00185                                      << "\netamin[4]=" << etamin[4] 
00186                                      << "\netamin[5]=" << etamin[5] 
00187                                      << "\netamin[6]=" << etamin[6] 
00188                                      << "\netamin[7]=" << etamin[7] 
00189 
00190                                      << "\nmindeta12_accp =" << mindeta12_accp   
00191                                      << "\nmindeta13_accp =" << mindeta13_accp  
00192                                      << "\nmindeta112_accp=" << mindeta112_accp 
00193                                      << "\nmindeta113_accp=" << mindeta113_accp 
00194       
00195                                      << "\netamax[0]=" << etamax[0] 
00196                                      << "\netamax[1]=" << etamax[1] 
00197                                      << "\netamax[2]=" << etamax[2] 
00198                                      << "\netamax[3]=" << etamax[3] 
00199                                      << "\netamax[4]=" << etamax[4] 
00200                                      << "\netamax[5]=" << etamax[5] 
00201                                      << "\netamax[6]=" << etamax[6] 
00202                                      << "\netamax[7]=" << etamax[7] 
00203 
00204                                      << "\nmaxdeta12_accp =" << maxdeta12_accp  
00205                                      << "\nmaxdeta13_accp =" << maxdeta13_accp  
00206                                      << "\nmaxdeta112_accp=" << maxdeta112_accp 
00207                                      << "\nmaxdeta113_accp=" << maxdeta113_accp 
00208   
00209                                      << "\netawin[0]=" << etawin[0] 
00210                                      << "\netawin[1]=" << etawin[1] 
00211                                      << "\netawin[2]=" << etawin[2] 
00212                                      << "\netawin[3]=" << etawin[3] 
00213                                      << "\netawin[4]=" << etawin[4] 
00214                                      << "\netawin[5]=" << etawin[5] 
00215                                      << "\netawin[6]=" << etawin[6] 
00216   
00217                                      << "\nmaxdphi12_accp =" << maxdphi12_accp  
00218                                      << "\nmaxdphi13_accp =" << maxdphi13_accp  
00219                                      << "\nmaxdphi112_accp=" << maxdphi112_accp 
00220                                      << "\nmaxdphi113_accp=" << maxdphi113_accp 
00221                            
00222                                      << "\nmindphip     =" << mindphip      
00223                                      << "\nmindphip_halo=" << mindphip_halo 
00224   
00225                                      << "\nstraightp=" << straightp 
00226                                      << "\ncurvedp  =" << curvedp   
00227                                      << "\nmbaPhiOff=" << mbaPhiOff 
00228                                      << "\nmbbPhiOff=" << mbbPhiOff 
00229     
00230                                      << "\n\nFIRMWARE VERSIONS"
00231                                      << "\nSP: " << firmwareSP
00232                                      << "\nFA: " << firmwareFA
00233                                      << "\nDD: " << firmwareDD
00234                                      << "\nVM: " << firmwareVM;
00235   
00236   // start filling the registers with the values in the DBS
00237   std::stringstream conf(registers[sp]);
00238   while( !conf.eof() ){
00239     char buff[1024];
00240     conf.getline(buff,1024);
00241     std::stringstream line(buff);
00242     //std::cout<<"buff:"<<buff<<std::endl;
00243     std::string register_;     line>>register_;
00244     std::string chip_;         line>>chip_;
00245     std::string muon_;         line>>muon_;
00246     std::string writeValue_;   line>>writeValue_;
00247     std::string comments_;     std::getline(line,comments_);
00248 
00249     if( register_=="CSR_REQ" && chip_=="SP" ){
00250       unsigned int value = strtol(writeValue_.c_str(),'\0',16);
00251       run_core        = (value&0x8000);
00252       trigger_on_ME1a = (value&0x0001);
00253       trigger_on_ME1b = (value&0x0002);
00254       trigger_on_ME2  = (value&0x0004);
00255       trigger_on_ME3  = (value&0x0008);
00256       trigger_on_ME4  = (value&0x0010);
00257       trigger_on_MB1a = (value&0x0100);
00258       trigger_on_MB1d = (value&0x0200);
00259     }
00260 
00261 
00262     if( register_=="CSR_SCC" && chip_=="SP" ){
00263       unsigned int value = strtol(writeValue_.c_str(),'\0',16);
00264       
00265       BXAdepth   = (value&0x3);
00266       useDT      = ( (value&0x80)>>7 );
00267       widePhi    = ( (value&0x40)>>6 );
00268       PreTrigger = ( (value&0x300)>>8);      
00269     }
00270 
00271 
00272     if( register_=="CSR_LQE" && chip_=="F1" && muon_=="M1" )
00273       QualityEnableME1a = strtol(writeValue_.c_str(),'\0',16);
00274     if( register_=="CSR_LQE" && chip_=="F1" && muon_=="M2" )
00275       QualityEnableME1b = strtol(writeValue_.c_str(),'\0',16);
00276     if( register_=="CSR_LQE" && chip_=="F1" && muon_=="M3" )
00277       QualityEnableME1c = strtol(writeValue_.c_str(),'\0',16);
00278     if( register_=="CSR_LQE" && chip_=="F2" && muon_=="M1" )
00279       QualityEnableME1d = strtol(writeValue_.c_str(),'\0',16);
00280     if( register_=="CSR_LQE" && chip_=="F2" && muon_=="M2" )
00281       QualityEnableME1e = strtol(writeValue_.c_str(),'\0',16);
00282     if( register_=="CSR_LQE" && chip_=="F2" && muon_=="M3" )
00283       QualityEnableME1f = strtol(writeValue_.c_str(),'\0',16);
00284     if( register_=="CSR_LQE" && chip_=="F3" && muon_=="M1" )
00285       QualityEnableME2a = strtol(writeValue_.c_str(),'\0',16);
00286     if( register_=="CSR_LQE" && chip_=="F3" && muon_=="M2" )
00287       QualityEnableME2b = strtol(writeValue_.c_str(),'\0',16);
00288     if( register_=="CSR_LQE" && chip_=="F3" && muon_=="M3" )
00289       QualityEnableME2c = strtol(writeValue_.c_str(),'\0',16);
00290     if( register_=="CSR_LQE" && chip_=="F4" && muon_=="M1" )
00291       QualityEnableME3a = strtol(writeValue_.c_str(),'\0',16);
00292     if( register_=="CSR_LQE" && chip_=="F4" && muon_=="M2" )
00293       QualityEnableME3b = strtol(writeValue_.c_str(),'\0',16);
00294     if( register_=="CSR_LQE" && chip_=="F4" && muon_=="M3" )
00295       QualityEnableME3c = strtol(writeValue_.c_str(),'\0',16);
00296     if( register_=="CSR_LQE" && chip_=="F5" && muon_=="M1" )
00297       QualityEnableME4a = strtol(writeValue_.c_str(),'\0',16);
00298     if( register_=="CSR_LQE" && chip_=="F5" && muon_=="M2" )
00299       QualityEnableME4b = strtol(writeValue_.c_str(),'\0',16);
00300     if( register_=="CSR_LQE" && chip_=="F5" && muon_=="M3" )
00301       QualityEnableME4c = strtol(writeValue_.c_str(),'\0',16);
00302 
00303     if( register_=="CSR_KFL" )
00304       kill_fiber = strtol(writeValue_.c_str(),'\0',16);
00305 
00306     if( register_=="CSR_SFC" && chip_=="SP" ){
00307       unsigned int value = strtol(writeValue_.c_str(),'\0',16);
00308       singlesTrackOutput = ((value&0x3000)>>12);
00309     }
00310 
00311     if( register_=="CNT_ETA" && chip_=="SP" ){
00312       unsigned int value = strtol(writeValue_.c_str(),'\0',16);
00313       eta_cnt = value;
00314     }
00315     
00316 
00317     // LATEST VERSION FROM CORE 2010-01-22 at http://www.phys.ufl.edu/~madorsky/sp/2010-01-22
00318     if( register_=="DAT_ETA" && chip_=="SP" ){
00319       
00320       unsigned int value = strtol(writeValue_.c_str(),'\0',16);
00321 
00322       //std::cout<<"DAT_ETA SP value:"<<value<<std::endl;
00323 
00324       if (eta_cnt== 0) mindetap = value;
00325       if (eta_cnt== 1) mindetap_halo = value;
00326 
00327       if (eta_cnt>= 2 && eta_cnt<10 ) etamin[eta_cnt-2] = value;
00328 
00329       if (eta_cnt==10) mindeta12_accp  = value;
00330       if (eta_cnt==11) mindeta13_accp  = value;
00331       if (eta_cnt==12) mindeta112_accp = value;
00332       if (eta_cnt==13) mindeta113_accp = value;
00333 
00334       if (eta_cnt>=14 && eta_cnt<22 ) etamax[eta_cnt-14] = value;
00335 
00336       if (eta_cnt==22) maxdeta12_accp  = value;
00337       if (eta_cnt==23) maxdeta13_accp  = value;
00338       if (eta_cnt==24) maxdeta112_accp = value;
00339       if (eta_cnt==25) maxdeta113_accp = value;
00340 
00341       if( eta_cnt>=26 && eta_cnt<33) etawin[eta_cnt-26] = value;
00342 
00343       if (eta_cnt==33) maxdphi12_accp  = value;
00344       if (eta_cnt==34) maxdphi13_accp  = value;
00345       if (eta_cnt==35) maxdphi112_accp = value;
00346       if (eta_cnt==36) maxdphi113_accp = value;
00347 
00348       if (eta_cnt==37) mindphip      = value;
00349       if (eta_cnt==38) mindphip_halo = value;
00350 
00351       if (eta_cnt==39) straightp = value;
00352       if (eta_cnt==40) curvedp   = value;
00353       if (eta_cnt==41) mbaPhiOff = value;
00354       if (eta_cnt==42) mbbPhiOff = value;
00355       
00356       eta_cnt++;
00357     }
00358 
00359     // filling the firmware variables: SP MEZZANINE
00360     if( register_=="FIRMWARE" && muon_=="SP" ){
00361       unsigned int value = atoi(writeValue_.c_str());
00362       firmwareSP=value;
00363     }
00364 
00365     // filling the firmware variables: Front FPGAs
00366     if( register_=="FIRMWARE" && muon_=="FA" ){
00367       unsigned int value = atoi(writeValue_.c_str());
00368       firmwareFA=value;
00369     }
00370 
00371     // filling the firmware variables: DDU
00372     if( register_=="FIRMWARE" && muon_=="DD" ){
00373       unsigned int value = atoi(writeValue_.c_str());
00374       firmwareDD=value;
00375     }
00376 
00377     // filling the firmware variables: VM
00378     if( register_=="FIRMWARE" && muon_=="VM" ){
00379       unsigned int value = atoi(writeValue_.c_str());
00380       firmwareVM=value;
00381     }
00382   }
00383 
00384   
00385 
00386   pset.addParameter<bool>("run_core"       , run_core       );
00387   pset.addParameter<bool>("trigger_on_ME1a", trigger_on_ME1a);
00388   pset.addParameter<bool>("trigger_on_ME1b", trigger_on_ME1b);
00389   pset.addParameter<bool>("trigger_on_ME2" , trigger_on_ME2 );
00390   pset.addParameter<bool>("trigger_on_ME3" , trigger_on_ME3 );
00391   pset.addParameter<bool>("trigger_on_ME4" , trigger_on_ME4 );
00392   pset.addParameter<bool>("trigger_on_MB1a", trigger_on_MB1a);
00393   pset.addParameter<bool>("trigger_on_MB1d", trigger_on_MB1d);
00394 
00395   pset.addParameter<unsigned int>("BXAdepth"  , BXAdepth  );
00396   pset.addParameter<unsigned int>("useDT"     , useDT     );
00397   pset.addParameter<unsigned int>("widePhi"   , widePhi   );
00398   pset.addParameter<unsigned int>("PreTrigger", PreTrigger);
00399       
00400   // this were two old settings, not used anymore. Set them to zero
00401   // ask Alex if he can remove them altogether
00402   pset.addParameter<bool>("AllowALCTonly", AllowALCTonly);
00403   pset.addParameter<bool>("AllowCLCTonly", AllowCLCTonly);
00404 
00405   pset.addParameter<int>("CoreLatency", CoreLatency);
00406   pset.addParameter<bool>("rescaleSinglesPhi", rescaleSinglesPhi);
00407 
00408   pset.addParameter<unsigned int>("QualityEnableME1a",QualityEnableME1a);
00409   pset.addParameter<unsigned int>("QualityEnableME1b",QualityEnableME1b);
00410   pset.addParameter<unsigned int>("QualityEnableME1c",QualityEnableME1c);
00411   pset.addParameter<unsigned int>("QualityEnableME1d",QualityEnableME1d);
00412   pset.addParameter<unsigned int>("QualityEnableME1e",QualityEnableME1e);
00413   pset.addParameter<unsigned int>("QualityEnableME1f",QualityEnableME1f);
00414   pset.addParameter<unsigned int>("QualityEnableME2a",QualityEnableME2a);
00415   pset.addParameter<unsigned int>("QualityEnableME2b",QualityEnableME2b);
00416   pset.addParameter<unsigned int>("QualityEnableME2c",QualityEnableME2c);
00417   pset.addParameter<unsigned int>("QualityEnableME3a",QualityEnableME3a);
00418   pset.addParameter<unsigned int>("QualityEnableME3b",QualityEnableME3b);
00419   pset.addParameter<unsigned int>("QualityEnableME3c",QualityEnableME3c);
00420   pset.addParameter<unsigned int>("QualityEnableME4a",QualityEnableME4a);
00421   pset.addParameter<unsigned int>("QualityEnableME4b",QualityEnableME4b);
00422   pset.addParameter<unsigned int>("QualityEnableME4c",QualityEnableME4c);
00423 
00424   pset.addParameter<unsigned int>("kill_fiber",kill_fiber);
00425   pset.addParameter<unsigned int>("singlesTrackOutput",singlesTrackOutput);
00426 
00427   // add the DAT_ETA registers to the pset
00428   pset.addParameter<unsigned int>("mindetap"     , mindetap     );
00429   pset.addParameter<unsigned int>("mindetap_halo", mindetap_halo);
00430   
00431   pset.addParameter< std::vector<unsigned int> >("EtaMin",etamin);
00432 
00433   pset.addParameter<unsigned int>("mindeta12_accp",  mindeta12_accp );
00434   pset.addParameter<unsigned int>("mindeta13_accp" , mindeta13_accp );
00435   pset.addParameter<unsigned int>("mindeta112_accp", mindeta112_accp);
00436   pset.addParameter<unsigned int>("mindeta113_accp", mindeta113_accp);
00437 
00438   pset.addParameter< std::vector<unsigned int> >("EtaMax",etamax);
00439 
00440   pset.addParameter<unsigned int>("maxdeta12_accp",  maxdeta12_accp );
00441   pset.addParameter<unsigned int>("maxdeta13_accp" , maxdeta13_accp );
00442   pset.addParameter<unsigned int>("maxdeta112_accp", maxdeta112_accp);
00443   pset.addParameter<unsigned int>("maxdeta113_accp", maxdeta113_accp);
00444 
00445   pset.addParameter< std::vector<unsigned int> >("EtaWindows",etawin);
00446 
00447   pset.addParameter<unsigned int>("maxdphi12_accp",  maxdphi12_accp );
00448   pset.addParameter<unsigned int>("maxdphi13_accp" , maxdphi13_accp );
00449   pset.addParameter<unsigned int>("maxdphi112_accp", maxdphi112_accp);
00450   pset.addParameter<unsigned int>("maxdphi113_accp", maxdphi113_accp);
00451   
00452   pset.addParameter<unsigned int>("mindphip",      mindphip     );
00453   pset.addParameter<unsigned int>("mindphip_halo", mindphip_halo);
00454   
00455   pset.addParameter<unsigned int>("straightp", straightp);
00456   pset.addParameter<unsigned int>("curvedp"  , curvedp  );
00457   pset.addParameter<unsigned int>("mbaPhiOff", mbaPhiOff);
00458   pset.addParameter<unsigned int>("mbbPhiOff", mbbPhiOff);
00459 
00460   pset.addParameter<unsigned int>("firmwareSP", firmwareSP);
00461   pset.addParameter<unsigned int>("firmwareFA", firmwareFA);
00462   pset.addParameter<unsigned int>("firmwareDD", firmwareDD);
00463   pset.addParameter<unsigned int>("firmwareVM", firmwareVM);
00464 
00465 
00466   // printout
00467   LogDebug("L1MuCSCTFConfiguration") << "\nCORE CONFIGURATION AFTER READING THE DBS VALUES" 
00468                                      << "\nrun_core="        << run_core       
00469                                      << "\ntrigger_on_ME1a=" << trigger_on_ME1a
00470                                      << "\ntrigger_on_ME1b=" << trigger_on_ME1b
00471                                      << "\ntrigger_on_ME2="  << trigger_on_ME2 
00472                                      << "\ntrigger_on_ME3="  << trigger_on_ME3 
00473                                      << "\ntrigger_on_ME4="  << trigger_on_ME4 
00474                                      << "\ntrigger_on_MB1a=" << trigger_on_MB1a
00475                                      << "\ntrigger_on_MB1d=" << trigger_on_MB1d
00476 
00477                                      << "\nBXAdepth="   << BXAdepth   
00478                                      << "\nuseDT="      << useDT      
00479                                      << "\nwidePhi="    << widePhi    
00480                                      << "\nPreTrigger=" << PreTrigger 
00481       
00482                                      << "\nCoreLatency="       << CoreLatency       
00483                                      << "\nrescaleSinglesPhi=" << rescaleSinglesPhi 
00484                                      
00485                                      << "\n\nVARIOUS CONFIGURATION PARAMETERS AFTER READING THE DBS VALUES" 
00486                                      << "\nAllowALCTonly=" <<  AllowALCTonly 
00487                                      << "\nAllowCLCTonly=" <<  AllowCLCTonly 
00488 
00489                                      << "\nQualityEnableME1a=" << QualityEnableME1a 
00490                                      << "\nQualityEnableME1b=" << QualityEnableME1b 
00491                                      << "\nQualityEnableME1c=" << QualityEnableME1c 
00492                                      << "\nQualityEnableME1d=" << QualityEnableME1d 
00493                                      << "\nQualityEnableME1e=" << QualityEnableME1e 
00494                                      << "\nQualityEnableME1f=" << QualityEnableME1f 
00495                                      << "\nQualityEnableME2a=" << QualityEnableME2a 
00496                                      << "\nQualityEnableME2b=" << QualityEnableME2b 
00497                                      << "\nQualityEnableME2c=" << QualityEnableME2c 
00498                                      << "\nQualityEnableME3a=" << QualityEnableME3a 
00499                                      << "\nQualityEnableME3b=" << QualityEnableME3b 
00500                                      << "\nQualityEnableME3c=" << QualityEnableME3c 
00501                                      << "\nQualityEnableME4a=" << QualityEnableME4a 
00502                                      << "\nQualityEnableME4b=" << QualityEnableME4b 
00503                                      << "\nQualityEnableME4c=" << QualityEnableME4c 
00504                                      
00505                                      << "\nkill_fiber="         << kill_fiber 
00506                                      << "\nsinglesTrackOutput=" << singlesTrackOutput 
00507     
00508                                      << "\n\nDAT_ETA AFTER READING THE DBS VALUES" 
00509                                      << "\nmindetap     =" << mindetap      
00510                                      << "\nmindetap_halo=" << mindetap_halo 
00511       
00512                                      << "\netamin[0]=" << etamin[0] 
00513                                      << "\netamin[1]=" << etamin[1] 
00514                                      << "\netamin[2]=" << etamin[2] 
00515                                      << "\netamin[3]=" << etamin[3] 
00516                                      << "\netamin[4]=" << etamin[4] 
00517                                      << "\netamin[5]=" << etamin[5] 
00518                                      << "\netamin[6]=" << etamin[6] 
00519                                      << "\netamin[7]=" << etamin[7] 
00520 
00521                                      << "\nmindeta12_accp =" << mindeta12_accp   
00522                                      << "\nmindeta13_accp =" << mindeta13_accp  
00523                                      << "\nmindeta112_accp=" << mindeta112_accp 
00524                                      << "\nmindeta113_accp=" << mindeta113_accp 
00525       
00526                                      << "\netamax[0]=" << etamax[0] 
00527                                      << "\netamax[1]=" << etamax[1] 
00528                                      << "\netamax[2]=" << etamax[2] 
00529                                      << "\netamax[3]=" << etamax[3] 
00530                                      << "\netamax[4]=" << etamax[4] 
00531                                      << "\netamax[5]=" << etamax[5] 
00532                                      << "\netamax[6]=" << etamax[6] 
00533                                      << "\netamax[7]=" << etamax[7] 
00534 
00535                                      << "\nmaxdeta12_accp =" << maxdeta12_accp  
00536                                      << "\nmaxdeta13_accp =" << maxdeta13_accp  
00537                                      << "\nmaxdeta112_accp=" << maxdeta112_accp 
00538                                      << "\nmaxdeta113_accp=" << maxdeta113_accp 
00539   
00540                                      << "\netawin[0]=" << etawin[0] 
00541                                      << "\netawin[1]=" << etawin[1] 
00542                                      << "\netawin[2]=" << etawin[2] 
00543                                      << "\netawin[3]=" << etawin[3] 
00544                                      << "\netawin[4]=" << etawin[4] 
00545                                      << "\netawin[5]=" << etawin[5] 
00546                                      << "\netawin[6]=" << etawin[6] 
00547   
00548                                      << "\nmaxdphi12_accp =" << maxdphi12_accp  
00549                                      << "\nmaxdphi13_accp =" << maxdphi13_accp  
00550                                      << "\nmaxdphi112_accp=" << maxdphi112_accp 
00551                                      << "\nmaxdphi113_accp=" << maxdphi113_accp 
00552                            
00553                                      << "\nmindphip     =" << mindphip      
00554                                      << "\nmindphip_halo=" << mindphip_halo 
00555   
00556                                      << "\nstraightp=" << straightp 
00557                                      << "\ncurvedp  =" << curvedp   
00558                                      << "\nmbaPhiOff=" << mbaPhiOff 
00559                                      << "\nmbbPhiOff=" << mbbPhiOff 
00560 
00561                                      << "\n\nFIRMWARE VERSIONS AFTER READING THE DBS VALUES"
00562                                      << "\nSP: " << firmwareSP
00563                                      << "\nFA: " << firmwareFA
00564                                      << "\nDD: " << firmwareDD
00565                                      << "\nVM: " << firmwareVM;
00566   
00567   // ---------------------------------------------------------
00568 
00569   return pset;
00570 
00571 }
00572 
00573 
00574 
00575 void L1MuCSCTFConfiguration::print(std::ostream& myStr) const {
00576   myStr << "\nL1 Mu CSCTF Parameters \n" << std::endl;
00577 
00578   for (int iSP=0;iSP<12;iSP++) {
00579     myStr << "============================================="    << std::endl;
00580     myStr << "Printing out Global Tag Content for SP " << iSP+1 << std::endl;
00581     myStr << registers[iSP];
00582     myStr << "============================================="    << std::endl;
00583   }
00584 }
/afs/cern.ch/work/a/aaltunda/public/www/CMSSW_5_3_13_patch3/src/CondFormats/L1TObjects/src/L1MuCSCTFConfiguration.cc
