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/afs/cern.ch/work/a/aaltunda/public/www/CMSSW_5_3_13_patch3/src/CalibTracker/SiStripESProducers/plugins/fake/SiStripFedCablingFakeESSource.cc

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00001 #include "CalibTracker/SiStripESProducers/plugins/fake/SiStripFedCablingFakeESSource.h"
00002 #include "CalibFormats/SiStripObjects/interface/SiStripFecCabling.h"
00003 #include "CalibFormats/SiStripObjects/interface/SiStripModule.h"
00004 #include "CalibTracker/Records/interface/SiStripHashedDetIdRcd.h"
00005 #include "CalibTracker/SiStripCommon/interface/SiStripDetInfoFileReader.h"
00006 #include "CalibTracker/SiStripCommon/interface/SiStripFedIdListReader.h"
00007 #include "CondFormats/SiStripObjects/interface/FedChannelConnection.h"
00008 #include "CondFormats/SiStripObjects/interface/SiStripFedCabling.h"
00009 #include "FWCore/MessageLogger/interface/MessageLogger.h"
00010 #include <sstream>
00011 #include <vector>
00012 #include <map>
00013 
00014 using namespace sistrip;
00015 
00016 // -----------------------------------------------------------------------------
00017 //
00018 SiStripFedCablingFakeESSource::SiStripFedCablingFakeESSource( const edm::ParameterSet& pset )
00019   : SiStripFedCablingESProducer( pset ),
00020     detIds_( pset.getParameter<edm::FileInPath>("DetIdsFile") ),
00021     fedIds_( pset.getParameter<edm::FileInPath>("FedIdsFile") ),
00022     pset_(pset)
00023 {
00024   findingRecord<SiStripFedCablingRcd>();
00025   edm::LogVerbatim("FedCabling") 
00026     << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
00027     << " Constructing object...";
00028 }
00029 
00030 // -----------------------------------------------------------------------------
00031 //
00032 SiStripFedCablingFakeESSource::~SiStripFedCablingFakeESSource() {
00033   edm::LogVerbatim("FedCabling")
00034     << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
00035     << " Destructing object...";
00036 }
00037 
00038 // -----------------------------------------------------------------------------
00039 // 
00040 SiStripFedCabling* SiStripFedCablingFakeESSource::make( const SiStripFedCablingRcd& ) {
00041   edm::LogVerbatim("FedCabling")
00042     << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
00043     << " Building \"fake\" FED cabling map"
00044     << " from real DetIds and FedIds (read from ascii file)";
00045   
00046   // Create FEC cabling object 
00047   SiStripFecCabling* fec_cabling = new SiStripFecCabling();
00048   
00049   // Read DetId list from file
00050   SiStripDetInfoFileReader Detreader( detIds_.fullPath() );
00051   typedef std::vector<uint32_t>  Dets;
00052   
00053   Dets dets = Detreader.getAllDetIds();
00054   
00055   // Read FedId list from file
00056   typedef std::vector<uint16_t> Feds;
00057   Feds feds = SiStripFedIdListReader( fedIds_.fullPath() ).fedIds();
00058   
00059   bool populateAllFeds=pset_.getParameter<bool>("PopulateAllFeds");
00060 
00061   // Iterator through DetInfo objects and populate FEC cabling object
00062   uint32_t imodule = 0;
00063   Dets::const_iterator idet = dets.begin();
00064   Dets::const_iterator jdet = dets.end();
00065   for ( ; idet != jdet; ++idet ) {
00066     uint16_t npairs =  Detreader.getNumberOfApvsAndStripLength(*idet).first / 2;
00067     for ( uint16_t ipair = 0; ipair < npairs; ++ipair ) {
00068       uint16_t addr = 0;
00069       if      ( npairs == 2 && ipair == 0 ) { addr = 32; }
00070       else if ( npairs == 2 && ipair == 1 ) { addr = 36; }
00071       else if ( npairs == 3 && ipair == 0 ) { addr = 32; }
00072       else if ( npairs == 3 && ipair == 1 ) { addr = 34; }
00073       else if ( npairs == 3 && ipair == 2 ) { addr = 36; }
00074       else {
00075         edm::LogWarning("FedCabling") 
00076           << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
00077           << " Inconsistent values for nPairs (" << npairs
00078           << ") and ipair (" << ipair << ")!";
00079       }
00080       uint32_t module_key = SiStripFecKey(fecCrate( imodule ), 
00081                                           fecSlot( imodule ),  
00082                                           fecRing( imodule ), 
00083                                           ccuAddr( imodule ), 
00084                                           ccuChan( imodule )).key();
00085       FedChannelConnection conn( fecCrate( imodule ),
00086                                  fecSlot( imodule ), 
00087                                  fecRing( imodule ), 
00088                                  ccuAddr( imodule ), 
00089                                  ccuChan( imodule ), 
00090                                  addr, addr+1, // apv i2c addresses
00091                                  module_key,         // dcu id
00092                                  *idet,  // det id
00093                                  npairs );     // apv pairs
00094       fec_cabling->addDevices( conn );
00095     }
00096     imodule++;
00097   }
00098   
00099   // Assign "dummy" FED ids/chans
00100   bool insufficient = false;
00101   Feds::const_iterator ifed = feds.begin();
00102   uint16_t fed_ch = 0;
00103   for ( std::vector<SiStripFecCrate>::const_iterator icrate = fec_cabling->crates().begin(); icrate != fec_cabling->crates().end(); icrate++ ) {
00104     for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
00105       for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
00106         for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
00107           for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
00108             if(populateAllFeds){
00109               for ( uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++ ) {
00110                 
00111                 if ( ifed == feds.end() ) { fed_ch++; ifed = feds.begin(); }
00112                 if ( fed_ch == 96 ) {
00113                   insufficient = true;
00114                   break;
00115                 }
00116               
00117                 std::pair<uint16_t,uint16_t> addr = imod->activeApvPair( imod->lldChannel(ipair) );
00118                 SiStripModule::FedChannel fed_channel( (*ifed)/16+1, // 16 FEDs per crate, numbering starts from 1
00119                                                        (*ifed)%16+2, // FED slot starts from 2
00120                                                        *ifed,
00121                                                        fed_ch );
00122                 const_cast<SiStripModule&>(*imod).fedCh( addr.first, fed_channel );
00123                 ifed++;
00124               
00125               }
00126             }else{
00127               // Patch introduced by D.Giordano 2/12/08
00128               //to reproduce the fake cabling used in 2x
00129               //that was designed to fill each fed iteratively
00130               //filling all channels of a fed before going to the next one
00131               if ( 96-fed_ch < imod->nApvPairs() ) { ifed++; fed_ch = 0; } // move to next FED
00132               for ( uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++ ) {
00133                 std::pair<uint16_t,uint16_t> addr = imod->activeApvPair( (*imod).lldChannel(ipair) );
00134                 SiStripModule::FedChannel fed_channel( (*ifed)/16+1, // 16 FEDs per crate, numbering starts from 1
00135                                                        (*ifed)%16+2, // FED slot starts from 2
00136                                                        (*ifed), 
00137                                                        fed_ch );
00138                 const_cast<SiStripModule&>(*imod).fedCh( addr.first, fed_channel );
00139                 fed_ch++;
00140               }
00141 
00142             }
00143           }
00144         }
00145       }
00146     }
00147   }
00148 
00149   if ( insufficient ) {
00150     edm::LogWarning(mlCabling_)
00151       << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
00152       << " Insufficient FED channels to cable entire system!";
00153   }
00154   
00155   // Some debug
00156   std::stringstream ss;
00157   ss << "[SiStripFedCablingFakeESSource::" << __func__ << "]"
00158      <<" First count devices of FEC cabling " << std::endl;
00159   fec_cabling->countDevices().print(ss);
00160   LogTrace(mlCabling_) << ss.str();
00161   
00162   // Build FED cabling using FedChannelConnections
00163   std::vector<FedChannelConnection> conns;
00164   fec_cabling->connections( conns ); 
00165   SiStripFedCabling* cabling = new SiStripFedCabling( conns );
00166   
00167   return cabling;
00168   
00169 }
00170 
00171 // -----------------------------------------------------------------------------
00172 // 
00173 void SiStripFedCablingFakeESSource::setIntervalFor( const edm::eventsetup::EventSetupRecordKey& key, 
00174                                                     const edm::IOVSyncValue& iov_sync, 
00175                                                     edm::ValidityInterval& iov_validity ) {
00176   edm::ValidityInterval infinity( iov_sync.beginOfTime(), iov_sync.endOfTime() );
00177   iov_validity = infinity;
00178 }
00179 
00180