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#include <L1GtHwValidation.h>
Description: compare hardware records with emulator records for L1 GT records.
Implementation: Get the L1 GT records from data and from emulator. Compare every board between data and emulator.
$Date$ $Revision$
Definition at line 52 of file L1GtHwValidation.h.
| L1GtHwValidation::L1GtHwValidation | ( | const edm::ParameterSet & | paramSet | ) | [explicit] |
Definition at line 54 of file L1GtHwValidation.cc.
References CondNull, edm::ParameterSet::getUntrackedParameter(), l1GtConditionCategoryStringToEnum(), l1GtConditionTypeStringToEnum(), l1GtObjectStringToEnum(), LogDebug, m_dbe, m_dirName, m_excludeCondCategTypeObject, m_excludedCondCategory, m_excludedCondType, m_excludedL1GtObject, m_l1GctDataInputTag, m_l1GtDataDaqInputTag, m_l1GtDataEvmInputTag, m_l1GtEmulDaqInputTag, m_l1GtEmulEvmInputTag, ObjNull, cmsCodeRules::cppFunctionSkipper::operator, DQMStore::setCurrentFolder(), DQMStore::setVerbose(), and TypeNull.
:
//
// input tag for the L1 GT hardware DAQ record
m_l1GtDataDaqInputTag(paramSet.getParameter<edm::InputTag>(
"L1GtDataDaqInputTag")),
// input tag for the L1 GT hardware EVM record
m_l1GtDataEvmInputTag(paramSet.getParameter<edm::InputTag>(
"L1GtDataEvmInputTag")),
// input tag for the L1 GT emulator DAQ record
m_l1GtEmulDaqInputTag(paramSet.getParameter<edm::InputTag>(
"L1GtEmulDaqInputTag")),
// input tag for the L1 GT emulator EVM record
m_l1GtEmulEvmInputTag(paramSet.getParameter<edm::InputTag>(
"L1GtEmulEvmInputTag")),
// input tag for the L1 GCT hardware record
m_l1GctDataInputTag(paramSet.getParameter<edm::InputTag>(
"L1GctDataInputTag")),
//
m_dirName(paramSet.getUntrackedParameter("DirName", std::string(
"L1TEMU/GTexpert"))),
//
m_excludeCondCategTypeObject(paramSet.getParameter<std::vector<edm::ParameterSet> >(
"ExcludeCondCategTypeObject")),
//
m_excludeAlgoTrigByName(paramSet.getParameter<std::vector<std::string> >(
"ExcludeAlgoTrigByName")),
//
m_excludeAlgoTrigByBit(paramSet.getParameter<std::vector<int> >(
"ExcludeAlgoTrigByBit")),
//
// initialize counters
m_nrDataEventError(0),
m_nrEmulEventError(0),
// cache
m_l1GtMenuCacheID(0ULL), m_l1GtPfAlgoCacheID(0ULL),
m_l1GtPfTechCacheID(0ULL), m_l1GtTmAlgoCacheID(0ULL),
m_l1GtTmTechCacheID(0ULL),
//
m_dbe(0),
m_agree(true),
m_dataOnly(false),
m_emulOnly(false),
m_dataOnlyMask(false),
m_emulOnlyMask(false),
//
m_nrEvJob(0), m_nrEvRun(0) {
for (std::vector<edm::ParameterSet>::const_iterator
itExclud = m_excludeCondCategTypeObject.begin();
itExclud != m_excludeCondCategTypeObject.end();
++itExclud) {
if (!(itExclud->getParameter<std::string> ("ExcludedCondCategory")).empty()) {
m_excludedCondCategory.push_back(l1GtConditionCategoryStringToEnum(
itExclud->getParameter<std::string>("ExcludedCondCategory")));
} else {
m_excludedCondCategory.push_back(CondNull);
}
if (!(itExclud->getParameter<std::string>("ExcludedCondType")).empty() ) {
m_excludedCondType.push_back(l1GtConditionTypeStringToEnum(
itExclud->getParameter<std::string> ("ExcludedCondType")));
} else {
m_excludedCondType.push_back(TypeNull);
}
if (!(itExclud->getParameter<std::string>("ExcludedL1GtObject")).empty() ) {
m_excludedL1GtObject.push_back(l1GtObjectStringToEnum(
itExclud->getParameter<std::string> ("ExcludedL1GtObject")));
} else {
m_excludedL1GtObject.push_back(ObjNull);
}
}
LogDebug("L1GtHwValidation")
<< "\nInput tag for the L1 GT DAQ hardware record: "
<< m_l1GtDataDaqInputTag
<< "\nInput tag for the L1 GT EVM hardware record: "
<< m_l1GtDataEvmInputTag
<< "\nInput tag for the L1 GT DAQ emulator records: "
<< m_l1GtEmulDaqInputTag
<< "\nInput tag for the L1 GT EVM emulator records: "
<< m_l1GtEmulEvmInputTag
<< "\nInput tag for the L1 GCT hardware record: "
<< m_l1GctDataInputTag << std::endl;
// FIXME print in debug mode ExcludeCondCategTypeObject, ExcludeAlgoTrigByName, etc
m_dbe = edm::Service<DQMStore>().operator->();
if (m_dbe == 0) {
edm::LogInfo("L1GtHwValidation")
<< "\n Unable to get DQMStore service.";
} else {
if (paramSet.getUntrackedParameter<bool>("DQMStore", false)) {
m_dbe->setVerbose(0);
}
m_dbe->setCurrentFolder(m_dirName);
}
}
| L1GtHwValidation::~L1GtHwValidation | ( | ) | [virtual] |
Definition at line 167 of file L1GtHwValidation.cc.
{
// empty
}
| void L1GtHwValidation::analyze | ( | const edm::Event & | iEvent, |
| const edm::EventSetup & | evSetup | ||
| ) | [private, virtual] |
Implements edm::EDAnalyzer.
Definition at line 1857 of file L1GtHwValidation.cc.
References compareDaqRecord(), compareEvmRecord(), compareGt_Gct(), m_nrEvJob, and m_nrEvRun.
{
++m_nrEvJob;
++m_nrEvRun;
// L1 GT DAQ record comparison
compareDaqRecord(iEvent, evSetup);
// L1 GT EVM record comparison
compareEvmRecord(iEvent, evSetup);
// GCT collections from L1 GT PSB versus unpacked GCT
compareGt_Gct(iEvent, evSetup);
}
| void L1GtHwValidation::beginJob | ( | void | ) | [private, virtual] |
Reimplemented from edm::EDAnalyzer.
Definition at line 174 of file L1GtHwValidation.cc.
References bookHistograms(), DQMStore::dirExists(), m_dirName, cmsCodeRules::cppFunctionSkipper::operator, DQMStore::rmdir(), and DQMStore::setCurrentFolder().
{
DQMStore* dbe = 0;
dbe = edm::Service<DQMStore>().operator->();
// clean up directory
if (dbe) {
dbe->setCurrentFolder(m_dirName);
if (dbe->dirExists(m_dirName)) {
dbe->rmdir(m_dirName);
}
dbe->setCurrentFolder(m_dirName);
}
// book histograms
bookHistograms();
}
| void L1GtHwValidation::beginRun | ( | const edm::Run & | run, |
| const edm::EventSetup & | c | ||
| ) | [private, virtual] |
Reimplemented from edm::EDAnalyzer.
Definition at line 193 of file L1GtHwValidation.cc.
References excludedAlgoList(), edm::EventSetup::get(), L1GtTriggerMenu::gtAlgorithmMap(), L1GtPrescaleFactors::gtPrescaleFactors(), L1GtTriggerMask::gtTriggerMask(), L1GtTriggerMenu::gtTriggerMenuImplementation(), LogDebug, m_dbe, m_dirName, m_excludedAlgoList, m_excludedAlgorithmsAgreement, m_fdlDataAlgoDecision, m_fdlDataAlgoDecision_Err, m_fdlDataAlgoDecision_NoMatch, m_fdlDataAlgoDecisionMask, m_fdlDataAlgoDecisionPrescaled, m_fdlDataAlgoDecisionUnprescaled, m_fdlDataEmulAlgoDecision, m_fdlDataEmulAlgoDecision_Err, m_fdlDataEmulAlgoDecisionMask, m_fdlDataEmulAlgoDecisionPrescaled, m_fdlDataEmulAlgoDecisionUnprescaled, m_fdlDataEmulAlgoDecisionUnprescaledAllowed, m_fdlEmulAlgoDecision, m_fdlEmulAlgoDecision_Err, m_fdlEmulAlgoDecision_NoMatch, m_fdlEmulAlgoDecisionMask, m_fdlEmulAlgoDecisionPrescaled, m_fdlEmulAlgoDecisionUnprescaled, m_l1GtMenu, m_l1GtMenuCacheID, m_l1GtPfAlgo, m_l1GtPfAlgoCacheID, m_l1GtPfTech, m_l1GtPfTechCacheID, m_l1GtTmAlgo, m_l1GtTmAlgoCacheID, m_l1GtTmTech, m_l1GtTmTechCacheID, m_nrEvRun, m_prescaleFactorsAlgoTrig, m_prescaleFactorsTechTrig, m_triggerMaskAlgoTrig, m_triggerMaskTechTrig, NumberOfGtRecords, edm::ESHandle< T >::product(), MonitorElement::setBinLabel(), DQMStore::setCurrentFolder(), and TotalBxInEvent.
{
m_nrEvRun = 0;
// get / update the trigger menu from the EventSetup
// local cache & check on cacheIdentifier
unsigned long long l1GtMenuCacheID =
evSetup.get<L1GtTriggerMenuRcd>().cacheIdentifier();
if (m_l1GtMenuCacheID != l1GtMenuCacheID) {
edm::ESHandle<L1GtTriggerMenu> l1GtMenu;
evSetup.get<L1GtTriggerMenuRcd>().get(l1GtMenu);
m_l1GtMenu = l1GtMenu.product();
// compute the list of algorithms excluded from the computing of the agreement flag
m_excludedAlgoList.clear();
excludedAlgoList();
m_l1GtMenuCacheID = l1GtMenuCacheID;
}
// FIXME when the menu changes, make a copy of histograms, and clear the old one
// otherwise the labels are wrong
LogDebug("L1GtHwValidation") << "\nUsing L1 menu: \n "
<< m_l1GtMenu->gtTriggerMenuImplementation() << "\n"
<< std::endl;
const AlgorithmMap& algorithmMap = m_l1GtMenu->gtAlgorithmMap();
for (CItAlgo itAlgo = algorithmMap.begin(); itAlgo != algorithmMap.end(); itAlgo++) {
const int algBitNumber = (itAlgo->second).algoBitNumber();
std::stringstream ss;
std::string algBitString;
ss << std::uppercase << algBitNumber;
ss >> algBitString;
const std::string& aName = algBitString + " " + itAlgo->first;
const char* algName = aName.c_str();
for (int iRec = 0; iRec < NumberOfGtRecords; ++iRec) {
for (int iBxInEvent = 0; iBxInEvent < TotalBxInEvent; ++iBxInEvent) {
// convert [0, TotalBxInEvent] to [-X, +X]
int iIndex = iBxInEvent - ((TotalBxInEvent + 1) / 2 - 1);
int hIndex = (iIndex + 16) % 16;
std::stringstream ss;
std::string str;
ss << std::uppercase << std::hex << hIndex;
ss >> str;
if (iRec == 0) {
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName + "/DAQ/BxInEvent_" + str);
}
} else {
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName + "/EVM/BxInEvent_" + str);
}
}
m_fdlDataAlgoDecision[iBxInEvent][iRec]->setBinLabel(
algBitNumber + 1, algName, 1);
m_fdlDataAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(
algBitNumber + 1, algName, 1);
m_fdlDataAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(
algBitNumber + 1, algName, 1);
m_fdlDataAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(
algBitNumber + 1, algName, 1);
m_fdlDataAlgoDecision_NoMatch[iBxInEvent][iRec]->setBinLabel(
algBitNumber + 1, algName, 1);
m_fdlEmulAlgoDecision[iBxInEvent][iRec]->setBinLabel(
algBitNumber + 1, algName, 1);
m_fdlEmulAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(
algBitNumber + 1, algName, 1);
m_fdlEmulAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(
algBitNumber + 1, algName, 1);
m_fdlEmulAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(
algBitNumber + 1, algName, 1);
m_fdlEmulAlgoDecision_NoMatch[iBxInEvent][iRec]->setBinLabel(
algBitNumber + 1, algName, 1);
m_fdlDataEmulAlgoDecision[iBxInEvent][iRec]->setBinLabel(
algBitNumber + 1, algName, 1);
m_fdlDataEmulAlgoDecisionPrescaled[iBxInEvent][iRec]->setBinLabel(
algBitNumber + 1, algName, 1);
m_fdlDataEmulAlgoDecisionUnprescaled[iBxInEvent][iRec]->setBinLabel(
algBitNumber + 1, algName, 1);
m_fdlDataEmulAlgoDecisionUnprescaledAllowed[iBxInEvent][iRec]->setBinLabel(
algBitNumber + 1, algName, 1);
m_fdlDataEmulAlgoDecisionMask[iBxInEvent][iRec]->setBinLabel(
algBitNumber + 1, algName, 1);
}
if (iRec == 0) {
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName + "/DAQ/");
}
} else {
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName + "/EVM/");
}
}
m_fdlDataAlgoDecision_Err[iRec]->setBinLabel(algBitNumber + 1,
algName, 1);
m_fdlEmulAlgoDecision_Err[iRec]->setBinLabel(algBitNumber + 1,
algName, 1);
m_fdlDataEmulAlgoDecision_Err[iRec]->setBinLabel(algBitNumber
+ 1, algName, 1);
}
//
for (std::vector<int>::const_iterator itAlgo = m_excludedAlgoList.begin(); itAlgo
!= m_excludedAlgoList.end(); ++itAlgo) {
if (algBitNumber == *itAlgo) {
m_excludedAlgorithmsAgreement->setBinLabel(algBitNumber
+ 1, algName, 1);
}
}
}
// get / update the prescale factors from the EventSetup
// local cache & check on cacheIdentifier
unsigned long long l1GtPfAlgoCacheID = evSetup.get<
L1GtPrescaleFactorsAlgoTrigRcd>().cacheIdentifier();
if (m_l1GtPfAlgoCacheID != l1GtPfAlgoCacheID) {
edm::ESHandle<L1GtPrescaleFactors> l1GtPfAlgo;
evSetup.get<L1GtPrescaleFactorsAlgoTrigRcd>().get(l1GtPfAlgo);
m_l1GtPfAlgo = l1GtPfAlgo.product();
m_prescaleFactorsAlgoTrig = &(m_l1GtPfAlgo->gtPrescaleFactors());
m_l1GtPfAlgoCacheID = l1GtPfAlgoCacheID;
}
unsigned long long l1GtPfTechCacheID = evSetup.get<
L1GtPrescaleFactorsTechTrigRcd>().cacheIdentifier();
if (m_l1GtPfTechCacheID != l1GtPfTechCacheID) {
edm::ESHandle<L1GtPrescaleFactors> l1GtPfTech;
evSetup.get<L1GtPrescaleFactorsTechTrigRcd>().get(l1GtPfTech);
m_l1GtPfTech = l1GtPfTech.product();
m_prescaleFactorsTechTrig = &(m_l1GtPfTech->gtPrescaleFactors());
m_l1GtPfTechCacheID = l1GtPfTechCacheID;
}
// get / update the trigger mask from the EventSetup
// local cache & check on cacheIdentifier
unsigned long long l1GtTmAlgoCacheID = evSetup.get<
L1GtTriggerMaskAlgoTrigRcd>().cacheIdentifier();
if (m_l1GtTmAlgoCacheID != l1GtTmAlgoCacheID) {
edm::ESHandle<L1GtTriggerMask> l1GtTmAlgo;
evSetup.get<L1GtTriggerMaskAlgoTrigRcd>().get(l1GtTmAlgo);
m_l1GtTmAlgo = l1GtTmAlgo.product();
m_triggerMaskAlgoTrig = m_l1GtTmAlgo->gtTriggerMask();
m_l1GtTmAlgoCacheID = l1GtTmAlgoCacheID;
}
unsigned long long l1GtTmTechCacheID = evSetup.get<
L1GtTriggerMaskTechTrigRcd>().cacheIdentifier();
if (m_l1GtTmTechCacheID != l1GtTmTechCacheID) {
edm::ESHandle<L1GtTriggerMask> l1GtTmTech;
evSetup.get<L1GtTriggerMaskTechTrigRcd>().get(l1GtTmTech);
m_l1GtTmTech = l1GtTmTech.product();
m_triggerMaskTechTrig = m_l1GtTmTech->gtTriggerMask();
m_l1GtTmTechCacheID = l1GtTmTechCacheID;
}
}
| void L1GtHwValidation::bookHistograms | ( | ) | [private] |
book all histograms for the module
Definition at line 1875 of file L1GtHwValidation.cc.
References DQMStore::book1D(), m_dbe, m_dirName, m_excludedAlgorithmsAgreement, m_fdlDataAlgoDecision, m_fdlDataAlgoDecision_Err, m_fdlDataAlgoDecision_NoMatch, m_fdlDataAlgoDecisionMask, m_fdlDataAlgoDecisionMask_NoMatch, m_fdlDataAlgoDecisionPrescaled, m_fdlDataAlgoDecisionPrescaled_NoMatch, m_fdlDataAlgoDecisionPrescaledMask_NoMatch, m_fdlDataAlgoDecisionUnprescaled, m_fdlDataAlgoDecisionUnprescaled_NoMatch, m_fdlDataAlgoDecisionUnprescaledMask_NoMatch, m_fdlDataEmul, m_fdlDataEmul_Err, m_fdlDataEmulAlgoDecision, m_fdlDataEmulAlgoDecision_Err, m_fdlDataEmulAlgoDecisionMask, m_fdlDataEmulAlgoDecisionPrescaled, m_fdlDataEmulAlgoDecisionUnprescaled, m_fdlDataEmulAlgoDecisionUnprescaledAllowed, m_fdlDataEmulTechDecision, m_fdlDataEmulTechDecision_Err, m_fdlDataEmulTechDecisionMask, m_fdlDataTechDecision, m_fdlDataTechDecision_Err, m_fdlDataTechDecisionMask, m_fdlEmulAlgoDecision, m_fdlEmulAlgoDecision_Err, m_fdlEmulAlgoDecision_NoMatch, m_fdlEmulAlgoDecisionMask, m_fdlEmulAlgoDecisionMask_NoMatch, m_fdlEmulAlgoDecisionPrescaled, m_fdlEmulAlgoDecisionPrescaled_NoMatch, m_fdlEmulAlgoDecisionPrescaledMask_NoMatch, m_fdlEmulAlgoDecisionUnprescaled, m_fdlEmulAlgoDecisionUnprescaled_NoMatch, m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch, m_fdlEmulTechDecision, m_fdlEmulTechDecision_Err, m_fdlEmulTechDecisionMask, m_gtErrorFlag, m_gtfeDataEmul, NumberOfGtRecords, L1GlobalTriggerReadoutSetup::NumberPhysTriggers, L1GlobalTriggerReadoutSetup::NumberTechnicalTriggers, MonitorElement::setBinLabel(), DQMStore::setCurrentFolder(), and TotalBxInEvent.
Referenced by beginJob().
{
// histograms
const unsigned int numberTechTriggers =
L1GlobalTriggerReadoutSetup::NumberTechnicalTriggers;
const unsigned int numberAlgoTriggers =
L1GlobalTriggerReadoutSetup::NumberPhysTriggers;
for (int iRec = 0; iRec < NumberOfGtRecords; ++iRec) {
std::string recString;
if (iRec == 0) {
recString = "Daq_";
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName + "/DAQ/");
}
} else {
recString = "Evm_";
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName + "/EVM/");
}
}
std::string hName;
const char* histName;
hName = recString + "gtfeDataEmul";
histName = hName.c_str();
// GTFE histograms
m_gtfeDataEmul[iRec] = m_dbe->book1D(histName,
"GTFE data vs emul mismatch", 8, 0., 7.);
m_gtfeDataEmul[iRec]->setBinLabel(1, "BoardId", 1);
m_gtfeDataEmul[iRec]->setBinLabel(2, "RecordLength1", 1);
m_gtfeDataEmul[iRec]->setBinLabel(3, "RecordLength0", 1);
m_gtfeDataEmul[iRec]->setBinLabel(4, "BxNr", 1);
m_gtfeDataEmul[iRec]->setBinLabel(5, "SetupVersion", 1);
m_gtfeDataEmul[iRec]->setBinLabel(6, "DaqActiveBoards", 1);
m_gtfeDataEmul[iRec]->setBinLabel(7, "AltNrBxBoard", 1);
m_gtfeDataEmul[iRec]->setBinLabel(8, "TotalTriggerNr", 1);
// FDL histograms
for (int iHist = 0; iHist < TotalBxInEvent; ++iHist) {
// convert [0, TotalBxInEvent] to [-X, +X] and add to histogram name
int iIndex = iHist - ((TotalBxInEvent + 1) / 2 - 1);
int hIndex = (iIndex + 16) % 16;
std::stringstream ss;
std::string str;
ss << std::uppercase << std::hex << hIndex;
ss >> str;
if (iRec == 0) {
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName + "/DAQ/BxInEvent_" + str);
}
} else {
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName + "/EVM/BxInEvent_" + str);
}
}
hName = recString + "FdlDataEmul_" + str;
histName = hName.c_str();
std::string hTitle = "FDL data vs emul mismatch for BxInEvent = "
+ str;
const char* histTitle = hTitle.c_str();
//
m_fdlDataEmul[iHist][iRec] = m_dbe->book1D(histName, histTitle, 13,
0., 13.);
m_fdlDataEmul[iHist][iRec]->setBinLabel(1, "BoardId", 1);
m_fdlDataEmul[iHist][iRec]->setBinLabel(2, "BxInEvent", 1);
m_fdlDataEmul[iHist][iRec]->setBinLabel(3, "BxNr", 1);
m_fdlDataEmul[iHist][iRec]->setBinLabel(4, "EventNr", 1);
m_fdlDataEmul[iHist][iRec]->setBinLabel(5, "TechTrigger", 1);
m_fdlDataEmul[iHist][iRec]->setBinLabel(6, "TechTriggerMask", 1);
m_fdlDataEmul[iHist][iRec]->setBinLabel(7, "AlgoTrigger", 1);
m_fdlDataEmul[iHist][iRec]->setBinLabel(8, "AlgoTriggerMask", 1);
m_fdlDataEmul[iHist][iRec]->setBinLabel(9, "AlgoExtend", 1);
m_fdlDataEmul[iHist][iRec]->setBinLabel(10, "NoAlgo", 1);
m_fdlDataEmul[iHist][iRec]->setBinLabel(11, "FinalORAllParts", 1);
m_fdlDataEmul[iHist][iRec]->setBinLabel(12, "FinalORPhysPart", 1);
m_fdlDataEmul[iHist][iRec]->setBinLabel(13, "LocalBxNr", 1);
// algorithm decision
// data
hName = recString + "Data_AlgoDecision_" + str;
histName = hName.c_str();
hTitle = "Data: algorithm decision word for BxInEvent = " + str;
histTitle = hTitle.c_str();
m_fdlDataAlgoDecision[iHist][iRec] = m_dbe->book1D(histName,
histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
// emul
hName = recString + "Emul_AlgoDecision_" + str;
histName = hName.c_str();
hTitle = "Emul: algorithm decision word for BxInEvent = " + str;
histTitle = hTitle.c_str();
m_fdlEmulAlgoDecision[iHist][iRec] = m_dbe->book1D(histName,
histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
// algorithm decision for prescaled algorithms
// data
hName = recString + "Data_AlgoDecision_Prescaled_" + str;
histName = hName.c_str();
hTitle
= "Data: prescaled algorithms: algorithm decision for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataAlgoDecisionPrescaled[iHist][iRec] = m_dbe->book1D(
histName, histTitle, numberAlgoTriggers, 0.,
numberAlgoTriggers);
// emul
hName = recString + "Emul_AlgoDecision_Prescaled_" + str;
histName = hName.c_str();
hTitle
= "Emul: prescaled algorithms: algorithm decision for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlEmulAlgoDecisionPrescaled[iHist][iRec] = m_dbe->book1D(
histName, histTitle, numberAlgoTriggers, 0.,
numberAlgoTriggers);
// algorithm decision for unprescaled algorithms
// data
hName = recString + "Data_AlgoDecision_Unprescaled_" + str;
histName = hName.c_str();
hTitle
= "Data: unprescaled algorithms: algorithm decision for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataAlgoDecisionUnprescaled[iHist][iRec] = m_dbe->book1D(
histName, histTitle, numberAlgoTriggers, 0.,
numberAlgoTriggers);
// emul
hName = recString + "Emul_AlgoDecision_Unprescaled_" + str;
histName = hName.c_str();
hTitle
= "Emul: unprescaled algorithms: algorithm decision for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlEmulAlgoDecisionUnprescaled[iHist][iRec] = m_dbe->book1D(
histName, histTitle, numberAlgoTriggers, 0.,
numberAlgoTriggers);
// algorithm decision after masking (partition physics)
// data
hName = recString + "Data_AlgoDecisionAfterMask_" + str;
histName = hName.c_str();
hTitle
= "Data, physics partition: algorithm decision word after mask for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataAlgoDecisionMask[iHist][iRec] = m_dbe->book1D(histName,
histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
// emul
hName = recString + "Emul_AlgoDecisionAfterMask_" + str;
histName = hName.c_str();
hTitle
= "Emul, physics partition: algorithm decision word after mask for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlEmulAlgoDecisionMask[iHist][iRec] = m_dbe->book1D(histName,
histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
//
hName = recString + "DataEmul_AlgoDecision_" + str;
histName = hName.c_str();
hTitle
= "Data vs emul: non-matching algorithm decision word for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataEmulAlgoDecision[iHist][iRec] = m_dbe->book1D(histName,
histTitle, numberAlgoTriggers, 0., numberAlgoTriggers);
//
hName = recString + "DataEmul_AlgoDecision_Prescaled_" + str;
histName = hName.c_str();
hTitle
= "Data vs emul: prescaled algorithms with non-matching decision for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataEmulAlgoDecisionPrescaled[iHist][iRec] = m_dbe->book1D(
histName, histTitle, numberAlgoTriggers, 0.,
numberAlgoTriggers);
//
hName = recString + "DataEmul_AlgoDecision_Unprescaled_" + str;
histName = hName.c_str();
hTitle
= "Data vs emul: unprescaled algorithms with non-matching decision for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataEmulAlgoDecisionUnprescaled[iHist][iRec] = m_dbe->book1D(
histName, histTitle, numberAlgoTriggers, 0.,
numberAlgoTriggers);
//
hName = recString + "DataEmul_AlgoDecision_Unprescaled_Allowed_" + str;
histName = hName.c_str();
hTitle
= "Data vs emul: unprescaled algorithms not excluded with non-matching decision for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataEmulAlgoDecisionUnprescaledAllowed[iHist][iRec] = m_dbe->book1D(
histName, histTitle, numberAlgoTriggers, 0.,
numberAlgoTriggers);
//
hName = recString + "Data_AlgoDecision_NoMatch_" + str;
histName = hName.c_str();
hTitle
= "Data: algorithm decision for non-matching cases for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataAlgoDecision_NoMatch[iHist][iRec] = m_dbe->book1D(
histName, histTitle, numberAlgoTriggers, 0.,
numberAlgoTriggers);
//
hName = recString + "Emul_AlgoDecision_NoMatch_" + str;
histName = hName.c_str();
hTitle
= "Emul: algorithm decision for non-matching cases for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlEmulAlgoDecision_NoMatch[iHist][iRec] = m_dbe->book1D(
histName, histTitle, numberAlgoTriggers, 0.,
numberAlgoTriggers);
// prescaled algorithms
hName = recString + "Data_AlgoDecision_Prescaled_NoMatch_" + str;
histName = hName.c_str();
hTitle
= "Data: prescaled algorithms: non-matching algorithm decision for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataAlgoDecisionPrescaled_NoMatch[iHist][iRec]
= m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
0., numberAlgoTriggers);
//
hName = recString + "Emul_AlgoDecision_Prescaled_NoMatch_" + str;
histName = hName.c_str();
hTitle
= "Emul: prescaled algorithms: non-matching algorithm decision for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlEmulAlgoDecisionPrescaled_NoMatch[iHist][iRec]
= m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
0., numberAlgoTriggers);
// unprescaled algorithms - non-matching
hName = recString + "Data_AlgoDecision_Unprescaled_NoMatch_" + str;
histName = hName.c_str();
hTitle
= "Data: unprescaled algorithms: non-matching algorithm decision for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataAlgoDecisionUnprescaled_NoMatch[iHist][iRec]
= m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
0., numberAlgoTriggers);
//
hName = recString + "Emul_AlgoDecision_Unprescaled_NoMatch_" + str;
histName = hName.c_str();
hTitle
= "Emul: unprescaled algorithms: non-matching algorithm decision for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlEmulAlgoDecisionUnprescaled_NoMatch[iHist][iRec]
= m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
0., numberAlgoTriggers);
//
hName = recString + "Data_AlgoDecisionMask_NoMatch_" + str;
histName = hName.c_str();
hTitle
= "Data: algorithm decision for non-matching cases after mask for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataAlgoDecisionMask_NoMatch[iHist][iRec] = m_dbe->book1D(
histName, histTitle, numberAlgoTriggers, 0.,
numberAlgoTriggers);
//
hName = recString + "Emul_AlgoDecisionMask_NoMatch_" + str;
histName = hName.c_str();
hTitle
= "Emul: algorithm decision for non-matching cases after mask for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlEmulAlgoDecisionMask_NoMatch[iHist][iRec] = m_dbe->book1D(
histName, histTitle, numberAlgoTriggers, 0.,
numberAlgoTriggers);
// prescaled algorithms
hName = recString + "Data_AlgoDecisionMask_Prescaled_NoMatch_" + str;
histName = hName.c_str();
hTitle
= "Data: prescaled algorithms: non-matching algorithm decision after mask for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataAlgoDecisionPrescaledMask_NoMatch[iHist][iRec]
= m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
0., numberAlgoTriggers);
//
hName = recString + "Emul_AlgoDecision_PrescaledMask_NoMatch_" + str;
histName = hName.c_str();
hTitle
= "Emul: prescaled algorithms: non-matching algorithm decision after mask for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[iHist][iRec]
= m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
0., numberAlgoTriggers);
// unprescaled algorithms - non-matching
hName = recString + "Data_AlgoDecision_UnprescaledMask_NoMatch_" + str;
histName = hName.c_str();
hTitle
= "Data: unprescaled algorithms: non-matching algorithm decision after mask for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[iHist][iRec]
= m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
0., numberAlgoTriggers);
//
hName = recString + "Emul_AlgoDecision_UnprescaledMask_NoMatch_" + str;
histName = hName.c_str();
hTitle
= "Emul: unprescaled algorithms: non-matching algorithm decision after mask for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[iHist][iRec]
= m_dbe->book1D(histName, histTitle, numberAlgoTriggers,
0., numberAlgoTriggers);
//
hName = recString + "DataEmul_AlgoDecisionAfterMask_" + str;
histName = hName.c_str();
hTitle
= "Data vs emul, physics partition: non-matching algorithm decision word after mask for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataEmulAlgoDecisionMask[iHist][iRec] = m_dbe->book1D(
histName, histTitle, numberAlgoTriggers, 0.,
numberAlgoTriggers);
// technical trigger decision
// data
hName = recString + "Data_TechDecision_" + str;
histName = hName.c_str();
hTitle = "Data technical trigger decision word for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataTechDecision[iHist][iRec] = m_dbe->book1D(histName,
histTitle, numberTechTriggers, 0., numberTechTriggers);
// emul
hName = recString + "Emul_TechDecision_" + str;
histName = hName.c_str();
hTitle = "Emul: technical trigger decision word for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlEmulTechDecision[iHist][iRec] = m_dbe->book1D(histName,
histTitle, numberTechTriggers, 0., numberTechTriggers);
// technical trigger decision after masking (partition physics)
hName = recString + "Data_TechDecisionAfterMask_" + str;
histName = hName.c_str();
hTitle
= "Data technical trigger decision word after mask for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataTechDecisionMask[iHist][iRec] = m_dbe->book1D(histName,
histTitle, numberTechTriggers, 0., numberTechTriggers);
//
hName = recString + "Emul_TechDecisionAfterMask_" + str;
histName = hName.c_str();
hTitle
= "Emul: technical trigger decision word after mask for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlEmulTechDecisionMask[iHist][iRec] = m_dbe->book1D(histName,
histTitle, numberTechTriggers, 0., numberTechTriggers);
//
hName = recString + "DataEmul_TechDecision_" + str;
histName = hName.c_str();
hTitle
= "Data vs emul: non-matching technical trigger decision word for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataEmulTechDecision[iHist][iRec] = m_dbe->book1D(histName,
histTitle, numberTechTriggers, 0., numberTechTriggers);
hName = recString + "DataEmul_TechDecisionAfterMask_" + str;
histName = hName.c_str();
hTitle
= "Data vs emul: non-matching technical trigger decision word after mask for BxInEvent = "
+ str;
histTitle = hTitle.c_str();
m_fdlDataEmulTechDecisionMask[iHist][iRec] = m_dbe->book1D(
histName, histTitle, numberTechTriggers, 0.,
numberTechTriggers);
}
if (iRec == 0) {
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName + "/DAQ/");
}
} else {
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName + "/EVM/");
}
}
hName = recString + "FdlDataEmul_Err";
histName = hName.c_str();
m_fdlDataEmul_Err[iRec]
= m_dbe->book1D(
histName,
"FDL data vs emul mismatch for non-matching BxInEvent in FDL payload",
13, 0., 13.);
m_fdlDataEmul_Err[iRec]->setBinLabel(1, "BoardId", 1);
m_fdlDataEmul_Err[iRec]->setBinLabel(2, "BxInEvent", 1);
m_fdlDataEmul_Err[iRec]->setBinLabel(3, "BxNr", 1);
m_fdlDataEmul_Err[iRec]->setBinLabel(4, "EventNr", 1);
m_fdlDataEmul_Err[iRec]->setBinLabel(5, "TechTrigger", 1);
m_fdlDataEmul_Err[iRec]->setBinLabel(6, "TechTriggerMask", 1);
m_fdlDataEmul_Err[iRec]->setBinLabel(7, "AlgoTrigger", 1);
m_fdlDataEmul_Err[iRec]->setBinLabel(8, "AlgoTriggerMask", 1);
m_fdlDataEmul_Err[iRec]->setBinLabel(9, "AlgoExtend", 1);
m_fdlDataEmul_Err[iRec]->setBinLabel(10, "NoAlgo", 1);
m_fdlDataEmul_Err[iRec]->setBinLabel(11, "FinalORAllParts", 1);
m_fdlDataEmul_Err[iRec]->setBinLabel(12, "FinalORPhysPart", 1);
m_fdlDataEmul_Err[iRec]->setBinLabel(13, "LocalBxNr", 1);
hName = recString + "FdlDataAlgoDecision_Err";
histName = hName.c_str();
m_fdlDataAlgoDecision_Err[iRec]
= m_dbe->book1D(
histName,
"Data: algorithm trigger decision word, non-matching BxInEvent",
numberAlgoTriggers, 0., numberAlgoTriggers);
//
hName = recString + "Emul_AlgoDecision_Err";
histName = hName.c_str();
m_fdlEmulAlgoDecision_Err[iRec]
= m_dbe->book1D(
histName,
"Emul: algorithm trigger decision word, non-matching BxInEvent",
numberAlgoTriggers, 0., numberAlgoTriggers);
hName = recString + "DataEmul_AlgoDecision_Err";
histName = hName.c_str();
m_fdlDataEmulAlgoDecision_Err[iRec]
= m_dbe->book1D(
histName,
"Data vs emul: algorithm trigger decision word, non-matching BxInEvent",
numberAlgoTriggers, 0., numberAlgoTriggers);
//
hName = recString + "Data_TechDecision_Err";
histName = hName.c_str();
m_fdlDataTechDecision_Err[iRec]
= m_dbe->book1D(
histName,
"Data: technical trigger decision word, non-matching BxInEvent",
numberTechTriggers, 0., numberTechTriggers);
hName = recString + "Emul_TechDecision_Err";
histName = hName.c_str();
m_fdlEmulTechDecision_Err[iRec]
= m_dbe->book1D(
histName,
"Emul: technical trigger decision word, non-matching BxInEvent",
numberTechTriggers, 0., numberTechTriggers);
hName = recString + "DataEmul_TechDecision_Err";
histName = hName.c_str();
m_fdlDataEmulTechDecision_Err[iRec]
= m_dbe->book1D(
histName,
"Data vs emul: technical trigger decision word, non-matching BxInEvent",
numberTechTriggers, 0., numberTechTriggers);
}
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName);
}
//
m_excludedAlgorithmsAgreement = m_dbe->book1D(
"ExcludedAlgorithmsFromAgreement",
"Algorithms excluded from data versus emulator agreement flag",
numberAlgoTriggers, 0., numberAlgoTriggers);
//
m_gtErrorFlag = m_dbe->book1D("GTErrorFlag",
"L1 GT error flag for data versus emulator comparison", 5, 0., 5);
m_gtErrorFlag->setBinLabel(1, "Agree", 1);
m_gtErrorFlag->setBinLabel(2, "", 1);
m_gtErrorFlag->setBinLabel(3, "", 1);
m_gtErrorFlag->setBinLabel(4, "Data only", 1);
m_gtErrorFlag->setBinLabel(5, "Emul only", 1);
}
| void L1GtHwValidation::compareDaqRecord | ( | const edm::Event & | iEvent, |
| const edm::EventSetup & | evSetup | ||
| ) | [private, virtual] |
L1 GT DAQ record comparison.
Definition at line 1584 of file L1GtHwValidation.cc.
References L1GtPsbWord::boardId(), L1GtPsbWord::bxInEvent(), compareFDL(), compareGTFE(), comparePSB(), MonitorElement::Fill(), edm::Event::getByLabel(), edm::HandleBase::isValid(), LogDebug, m_agree, m_dataOnly, m_dataOnlyMask, m_dbe, m_dirName, m_emulOnly, m_emulOnlyMask, m_gtErrorFlag, m_l1GtDataDaqInputTag, m_l1GtEmulDaqInputTag, m_myCoutStream, m_nrDataEventError, m_nrEmulEventError, and DQMStore::setCurrentFolder().
Referenced by analyze().
{
// formal index for DAQ record
int iRec = 0;
// reset the flags - they are used for DAQ recor only
m_agree = true;
m_dataOnly = false;
m_emulOnly = false;
m_dataOnlyMask = false;
m_emulOnlyMask = false;
// get the L1 GT hardware DAQ record L1GlobalTriggerReadoutRecord
edm::Handle<L1GlobalTriggerReadoutRecord> gtReadoutRecordData;
iEvent.getByLabel(m_l1GtDataDaqInputTag, gtReadoutRecordData);
bool validData = false;
if (!gtReadoutRecordData.isValid()) {
m_nrDataEventError++;
} else {
validData = true;
}
// get the L1 GT emulator DAQ record L1GlobalTriggerReadoutRecord
edm::Handle<L1GlobalTriggerReadoutRecord> gtReadoutRecordEmul;
iEvent.getByLabel(m_l1GtEmulDaqInputTag, gtReadoutRecordEmul);
bool validEmul = false;
if (!gtReadoutRecordEmul.isValid()) {
m_nrEmulEventError++;
} else {
validEmul = true;
}
if ((!validData) || (!validEmul)) {
edm::LogWarning("L1GtHwValidation")
<< "\n No valid product found: DAQ L1GlobalTriggerReadoutRecord"
<< "\n Data validity [1 = true; 0 = false]: " << validData
<< "\n Emulator validity: [1 = true; 0 = false]: "
<< validEmul << "\n DAQ histograms will not be filled.\n"
<< std::endl;
return;
}
// compare GTFE
const L1GtfeWord& gtfeBlockData = gtReadoutRecordData->gtfeWord();
const L1GtfeWord& gtfeBlockEmul = gtReadoutRecordEmul->gtfeWord();
compareGTFE(iEvent, evSetup, gtfeBlockData, gtfeBlockEmul, iRec);
// FDL comparison
const std::vector<L1GtFdlWord>& gtFdlVectorData =
gtReadoutRecordData->gtFdlVector();
const std::vector<L1GtFdlWord>& gtFdlVectorEmul =
gtReadoutRecordEmul->gtFdlVector();
int gtFdlVectorDataSize = gtFdlVectorData.size();
int gtFdlVectorEmulSize = gtFdlVectorEmul.size();
if (gtFdlVectorDataSize == gtFdlVectorEmulSize) {
m_myCoutStream << "\nData and emulated FDL vector size: identical.\n";
m_myCoutStream << " Size: " << gtFdlVectorDataSize << std::endl;
for (int iFdl = 0; iFdl < gtFdlVectorDataSize; ++iFdl) {
const L1GtFdlWord& fdlBlockData = gtFdlVectorData[iFdl];
const L1GtFdlWord& fdlBlockEmul = gtFdlVectorEmul[iFdl];
compareFDL(iEvent, evSetup, fdlBlockData, fdlBlockEmul, iRec);
}
} else {
m_myCoutStream << "\nData and emulated FDL vector size: different.\n";
m_myCoutStream << " Data: size = " << gtFdlVectorDataSize << std::endl;
m_myCoutStream << " Emul: size = " << gtFdlVectorEmulSize << std::endl;
}
LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
// PSB comparison
const std::vector<L1GtPsbWord>& gtPsbVectorData =
gtReadoutRecordData->gtPsbVector();
const std::vector<L1GtPsbWord>& gtPsbVectorEmul =
gtReadoutRecordEmul->gtPsbVector();
int gtPsbVectorDataSize = gtPsbVectorData.size();
int gtPsbVectorEmulSize = gtPsbVectorEmul.size();
if (gtPsbVectorDataSize == gtPsbVectorEmulSize) {
m_myCoutStream << "\nData and emulated PSB vector size: identical.\n";
m_myCoutStream << " Size: " << gtPsbVectorDataSize << std::endl;
} else {
m_myCoutStream << "\nData and emulated PSB vector size: different.\n";
m_myCoutStream << " Data: size = " << gtPsbVectorDataSize << std::endl;
m_myCoutStream << " Emul: size = " << gtPsbVectorEmulSize << std::endl;
}
// the order of PSB block in the gtPsbVector is different in emulator and in data
// in emulator: all active PSB in one BxInEvent, ordered L1A-1, L1A, L1A+1
// in unpacker: every PSB in all BxInEvent
for (int iPsb = 0; iPsb < gtPsbVectorDataSize; ++iPsb) {
const L1GtPsbWord& psbBlockData = gtPsbVectorData[iPsb];
const boost::uint16_t boardIdData = psbBlockData.boardId();
const int bxInEventData = psbBlockData.bxInEvent();
// search the corresponding PSB in the emulated record using the
// BoardId and the BxInEvent
bool foundPSB = false;
for (int iPsbF = 0; iPsbF < gtPsbVectorEmulSize; ++iPsbF) {
const L1GtPsbWord& psbBlockEmul = gtPsbVectorEmul[iPsbF];
const boost::uint16_t boardIdEmul = psbBlockEmul.boardId();
const int bxInEventEmul = psbBlockEmul.bxInEvent();
if ((boardIdEmul == boardIdData)
&& (bxInEventData == bxInEventEmul)) {
foundPSB = true;
// compare the boards
comparePSB(iEvent, evSetup, psbBlockData, psbBlockEmul);
}
}
if (!foundPSB) {
m_myCoutStream << "\nNo emulated PSB with boardId() = " << std::hex
<< "0x" << std::setw(4) << std::setfill('0') << boardIdData
<< std::setfill(' ') << std::dec << " and BxInEvent = "
<< bxInEventData << " was found";
}
}
edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
// fill the m_gtErrorFlag histogram (only for L1 GT DAQ record)
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName);
}
if (m_agree) {
m_gtErrorFlag->Fill(0.0001);
}
if (m_dataOnly || m_dataOnlyMask) {
m_gtErrorFlag->Fill(3.0001);
}
if (m_emulOnly || m_emulOnlyMask) {
m_gtErrorFlag->Fill(4.0001);
}
}
| void L1GtHwValidation::compareEvmRecord | ( | const edm::Event & | iEvent, |
| const edm::EventSetup & | evSetup | ||
| ) | [private, virtual] |
L1 GT EVM record comparison.
Definition at line 1759 of file L1GtHwValidation.cc.
References compareFDL(), compareGTFE(), edm::Event::getByLabel(), edm::HandleBase::isValid(), LogDebug, m_l1GtDataEvmInputTag, m_l1GtEmulEvmInputTag, m_myCoutStream, m_nrDataEventError, and m_nrEmulEventError.
Referenced by analyze().
{
// formal index for EVM record
int iRec = 1;
// get the L1 GT hardware EVM record L1GlobalTriggerEvmReadoutRecord
edm::Handle<L1GlobalTriggerEvmReadoutRecord> gtReadoutRecordData;
iEvent.getByLabel(m_l1GtDataEvmInputTag, gtReadoutRecordData);
bool validData = false;
if (!gtReadoutRecordData.isValid()) {
m_nrDataEventError++;
} else {
validData = true;
}
// get the L1 GT emulator EVM record L1GlobalTriggerEvmReadoutRecord
edm::Handle<L1GlobalTriggerEvmReadoutRecord> gtReadoutRecordEmul;
iEvent.getByLabel(m_l1GtEmulEvmInputTag, gtReadoutRecordEmul);
bool validEmul = false;
if (!gtReadoutRecordEmul.isValid()) {
m_nrEmulEventError++;
} else {
validEmul = true;
}
if ((!validData) || (!validEmul)) {
edm::LogWarning("L1GtHwValidation")
<< "\n No valid product found: EVM L1GlobalTriggerEvmReadoutRecord"
<< "\n Data validity [1 = true; 0 = false]: " << validData
<< "\n Emulator validity: [1 = true; 0 = false]: "
<< validEmul << "\n EVM histograms will not be filled.\n"
<< std::endl;
return;
}
// compare GTFE
const L1GtfeWord& gtfeBlockData = gtReadoutRecordData->gtfeWord();
const L1GtfeWord& gtfeBlockEmul = gtReadoutRecordEmul->gtfeWord();
compareGTFE(iEvent, evSetup, gtfeBlockData, gtfeBlockEmul, iRec);
// FDL comparison
const std::vector<L1GtFdlWord>& gtFdlVectorData =
gtReadoutRecordData->gtFdlVector();
const std::vector<L1GtFdlWord>& gtFdlVectorEmul =
gtReadoutRecordEmul->gtFdlVector();
int gtFdlVectorDataSize = gtFdlVectorData.size();
int gtFdlVectorEmulSize = gtFdlVectorEmul.size();
if (gtFdlVectorDataSize == gtFdlVectorEmulSize) {
m_myCoutStream << "\nData and emulated FDL vector size: identical.\n";
m_myCoutStream << " Size: " << gtFdlVectorDataSize << std::endl;
for (int iFdl = 0; iFdl < gtFdlVectorDataSize; ++iFdl) {
const L1GtFdlWord& fdlBlockData = gtFdlVectorData[iFdl];
const L1GtFdlWord& fdlBlockEmul = gtFdlVectorEmul[iFdl];
compareFDL(iEvent, evSetup, fdlBlockData, fdlBlockEmul, iRec);
}
} else {
m_myCoutStream << "\nData and emulated FDL vector size: different.\n";
m_myCoutStream << " Data: size = " << gtFdlVectorDataSize << std::endl;
m_myCoutStream << " Emul: size = " << gtFdlVectorEmulSize << std::endl;
}
// FIXME compare TCS
LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
}
| void L1GtHwValidation::compareFDL | ( | const edm::Event & | iEvent, |
| const edm::EventSetup & | evSetup, | ||
| const L1GtFdlWord & | fdlBlockData, | ||
| const L1GtFdlWord & | fdlBlockEmul, | ||
| const int | iRec | ||
| ) | [private, virtual] |
compare the FDL board
Definition at line 624 of file L1GtHwValidation.cc.
References L1GtFdlWord::boardId(), L1GtFdlWord::bxInEvent(), L1GtFdlWord::bxNr(), L1GtFdlWord::eventNr(), excludedAlgo(), MonitorElement::Fill(), L1GtFdlWord::finalOR(), L1GtFdlWord::gtDecisionWord(), L1GtFdlWord::gtDecisionWordExtended(), L1GtFdlWord::gtPrescaleFactorIndexAlgo(), L1GtFdlWord::gtTechnicalTriggerWord(), L1GtFdlWord::localBxNr(), LogDebug, LogTrace, m_agree, m_dataOnly, m_dataOnlyMask, m_dbe, m_dirName, m_emulOnly, m_emulOnlyMask, m_excludedAlgorithmsAgreement, m_fdlDataAlgoDecision, m_fdlDataAlgoDecision_Err, m_fdlDataAlgoDecision_NoMatch, m_fdlDataAlgoDecisionMask, m_fdlDataAlgoDecisionMask_NoMatch, m_fdlDataAlgoDecisionPrescaled, m_fdlDataAlgoDecisionPrescaled_NoMatch, m_fdlDataAlgoDecisionPrescaledMask_NoMatch, m_fdlDataAlgoDecisionUnprescaled, m_fdlDataAlgoDecisionUnprescaled_NoMatch, m_fdlDataAlgoDecisionUnprescaledMask_NoMatch, m_fdlDataEmul, m_fdlDataEmul_Err, m_fdlDataEmulAlgoDecision, m_fdlDataEmulAlgoDecision_Err, m_fdlDataEmulAlgoDecisionMask, m_fdlDataEmulAlgoDecisionPrescaled, m_fdlDataEmulAlgoDecisionUnprescaled, m_fdlDataEmulAlgoDecisionUnprescaledAllowed, m_fdlDataEmulTechDecision, m_fdlDataEmulTechDecision_Err, m_fdlDataEmulTechDecisionMask, m_fdlDataTechDecision, m_fdlDataTechDecision_Err, m_fdlDataTechDecisionMask, m_fdlEmulAlgoDecision, m_fdlEmulAlgoDecision_Err, m_fdlEmulAlgoDecision_NoMatch, m_fdlEmulAlgoDecisionMask, m_fdlEmulAlgoDecisionMask_NoMatch, m_fdlEmulAlgoDecisionPrescaled_NoMatch, m_fdlEmulAlgoDecisionPrescaledMask_NoMatch, m_fdlEmulAlgoDecisionUnprescaled_NoMatch, m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch, m_fdlEmulTechDecision, m_fdlEmulTechDecision_Err, m_fdlEmulTechDecisionMask, m_myCoutStream, m_triggerMaskAlgoTrig, m_triggerMaskTechTrig, L1GtFdlWord::noAlgo(), dtDQMClient_cfg::prescaleFactor, L1GtFdlWord::print(), L1GtFdlWord::printGtDecisionWord(), L1GtFdlWord::printGtDecisionWordExtended(), L1GtFdlWord::printGtTechnicalTriggerWord(), DQMStore::setCurrentFolder(), and TotalBxInEvent.
Referenced by compareDaqRecord(), and compareEvmRecord().
{
// index of physics partition
int PhysicsPartition = 0;
//
std::string recString;
if (iRec == 0) {
recString = "DAQ";
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName + "/DAQ/");
}
} else {
recString = "EVM";
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName + "/EVM/");
}
}
if (fdlBlockData == fdlBlockEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL blocks: identical.\n";
fdlBlockData.print(m_myCoutStream);
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL blocks: different.\n";
m_myCoutStream << "\nData: FDL block\n";
fdlBlockData.print(m_myCoutStream);
m_myCoutStream << "\nEmul: FDL block\n";
fdlBlockEmul.print(m_myCoutStream);
}
LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
// get bunch cross in the GT event record -
// move it first as histograms are BxInEvent dependent
const int bxInEventData = fdlBlockData.bxInEvent();
const int bxInEventEmul = fdlBlockEmul.bxInEvent();
bool matchBxInEvent = false;
if (bxInEventData == bxInEventEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL bxInEvent identical.";
m_myCoutStream << "\n bxInEvent() = " << bxInEventData;
m_myCoutStream << "\n";
matchBxInEvent = true;
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL bxInEvent different.";
m_myCoutStream << "\n Data: bxInEvent() = " << bxInEventData;
m_myCoutStream << "\n Emul: bxInEvent() = " << bxInEventEmul;
m_myCoutStream << "\n";
m_fdlDataEmul_Err[iRec]->Fill(1);
if (iRec == 0) {
m_agree = false;
m_myCoutStream << "\nDisagreement data versus emulator: "
<< "\n Data and emulated FDL bxInEvent different \n";
}
}
LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
// symmetrize
bool validBxInEvent = false;
int histIndex = bxInEventData + (TotalBxInEvent + 1) / 2 - 1;
LogDebug("L1GtHwValidation") << "\n Convert bxInEvent = " << bxInEventData
<< " to histIndex = " << histIndex << std::endl;
if ((histIndex <= TotalBxInEvent) && (histIndex >= 0)) {
validBxInEvent = true;
}
// loop over algorithms and increase the corresponding counters
// get BoardId value
const boost::uint16_t boardIdData = fdlBlockData.boardId();
const boost::uint16_t boardIdEmul = fdlBlockEmul.boardId();
if (boardIdData == boardIdEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL boardId identical.";
m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4)
<< std::setfill('0') << boardIdData << std::setfill(' ')
<< std::dec;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL boardId different.";
m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x"
<< std::setw(4) << std::setfill('0') << boardIdData
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x"
<< std::setw(4) << std::setfill('0') << boardIdEmul
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n";
if (matchBxInEvent && validBxInEvent) {
m_fdlDataEmul[histIndex][iRec]->Fill(0);
} else {
m_fdlDataEmul_Err[iRec]->Fill(0);
}
}
LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
// get BxNr - bunch cross number of the actual bx
const boost::uint16_t bxNrData = fdlBlockData.bxNr();
const boost::uint16_t bxNrEmul = fdlBlockEmul.bxNr();
if (bxNrData == bxNrEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL bxNr identical.";
m_myCoutStream << "\n bxNr() = " << bxNrData;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL bxNr different.";
m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
m_myCoutStream << "\n";
if (matchBxInEvent && validBxInEvent) {
m_fdlDataEmul[histIndex][iRec]->Fill(2);
} else {
m_fdlDataEmul_Err[iRec]->Fill(2);
}
}
LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
// get event number since last L1 reset generated in FDL
const boost::uint32_t eventNrData = fdlBlockData.eventNr();
const boost::uint32_t eventNrEmul = fdlBlockEmul.eventNr();
if (eventNrData == eventNrEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL eventNr identical.";
m_myCoutStream << "\n eventNr() = " << eventNrData;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL eventNr different.";
m_myCoutStream << "\n Data: eventNr() = " << eventNrData;
m_myCoutStream << "\n Emul: eventNr() = " << eventNrEmul;
m_myCoutStream << "\n";
if (matchBxInEvent && validBxInEvent) {
m_fdlDataEmul[histIndex][iRec]->Fill(3);
} else {
m_fdlDataEmul_Err[iRec]->Fill(3);
}
}
LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
// get technical trigger bits
const TechnicalTriggerWord& gtTechnicalTriggerWordData =
fdlBlockData.gtTechnicalTriggerWord();
const TechnicalTriggerWord& gtTechnicalTriggerWordEmul =
fdlBlockEmul.gtTechnicalTriggerWord();
int nTechBits = gtTechnicalTriggerWordData.size();
TechnicalTriggerWord gtTechnicalTriggerWordDataMask(nTechBits);
TechnicalTriggerWord gtTechnicalTriggerWordEmulMask(nTechBits);
unsigned int bitValue = 0;
if (matchBxInEvent && validBxInEvent) {
for (int iBit = 0; iBit < nTechBits; ++iBit) {
unsigned int triggerMask = (m_triggerMaskTechTrig.at(iBit)) & (1
<< PhysicsPartition);
if (gtTechnicalTriggerWordData[iBit]) {
m_fdlDataTechDecision[histIndex][iRec]->Fill(iBit);
bitValue = (triggerMask) ? 0 : 1;
gtTechnicalTriggerWordDataMask[iBit] = bitValue;
if (bitValue) {
m_fdlDataTechDecisionMask[histIndex][iRec]->Fill(iBit);
}
}
if (gtTechnicalTriggerWordEmul.at(iBit)) {
m_fdlEmulTechDecision[histIndex][iRec]->Fill(iBit);
bitValue = (triggerMask) ? 0 : 1;
gtTechnicalTriggerWordEmulMask[iBit] = bitValue;
if (bitValue) {
m_fdlEmulTechDecisionMask[histIndex][iRec]->Fill(iBit);
}
}
}
} else {
for (int iBit = 0; iBit < nTechBits; ++iBit) {
if (gtTechnicalTriggerWordData[iBit]) {
m_fdlDataTechDecision_Err[iRec]->Fill(iBit);
}
if (gtTechnicalTriggerWordEmul.at(iBit)) {
m_fdlEmulTechDecision_Err[iRec]->Fill(iBit);
}
}
}
if (gtTechnicalTriggerWordData == gtTechnicalTriggerWordEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL gtTechnicalTriggerWord identical.\n";
fdlBlockData.printGtTechnicalTriggerWord(m_myCoutStream);
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL gtTechnicalTriggerWord different.";
m_myCoutStream << "\n Data: ";
fdlBlockData.printGtTechnicalTriggerWord(m_myCoutStream);
m_myCoutStream << "\n Emul: ";
fdlBlockEmul.printGtTechnicalTriggerWord(m_myCoutStream);
m_myCoutStream << "\n";
if (matchBxInEvent && validBxInEvent) {
m_fdlDataEmul[histIndex][iRec]->Fill(4);
} else {
m_fdlDataEmul_Err[iRec]->Fill(4);
}
if (matchBxInEvent && validBxInEvent) {
for (int iBit = 0; iBit < nTechBits; ++iBit) {
if (gtTechnicalTriggerWordData[iBit]
!= gtTechnicalTriggerWordEmul.at(iBit)) {
m_fdlDataEmulTechDecision[histIndex][iRec]->Fill(iBit);
}
}
} else {
for (int iBit = 0; iBit < nTechBits; ++iBit) {
if (gtTechnicalTriggerWordData[iBit]
!= gtTechnicalTriggerWordEmul.at(iBit)) {
m_fdlDataEmulTechDecision_Err[iRec]->Fill(iBit);
}
}
}
}
LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
if (gtTechnicalTriggerWordDataMask == gtTechnicalTriggerWordEmulMask) {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL gtTechnicalTriggerWord after mask identical.\n";
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL gtTechnicalTriggerWord after mask different.";
m_myCoutStream << "\n Data: ";
m_myCoutStream << "\n Emul: ";
m_myCoutStream << "\n";
if (matchBxInEvent && validBxInEvent) {
m_fdlDataEmul[histIndex][iRec]->Fill(5);
} else {
m_fdlDataEmul_Err[iRec]->Fill(5);
}
if (matchBxInEvent && validBxInEvent) {
for (int iBit = 0; iBit < nTechBits; ++iBit) {
if (gtTechnicalTriggerWordData[iBit]
!= gtTechnicalTriggerWordEmul.at(iBit)) {
m_fdlDataEmulTechDecisionMask[histIndex][iRec]->Fill(iBit);
}
}
}
}
LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
// get algorithms bits (decision word)
const DecisionWord& gtDecisionWordData = fdlBlockData.gtDecisionWord();
const DecisionWord& gtDecisionWordEmul = fdlBlockEmul.gtDecisionWord();
int nAlgoBits = gtDecisionWordData.size();
DecisionWord gtDecisionWordDataMask(nAlgoBits);
DecisionWord gtDecisionWordEmulMask(nAlgoBits);
// get the index of the prescale factor set from data
int iPfSet = fdlBlockData.gtPrescaleFactorIndexAlgo();
// check that the prescale factor is not out of range for the prescale factor
// record retrieved from event setup
size_t pfSetsSize = (*m_prescaleFactorsAlgoTrig).size();
if (iPfSet < 0) {
LogDebug("L1GtHwValidation")
<< "\nError: index of prescale factor set retrieved from the data \n"
<< "less than zero."
<< "\n Value of index retrieved from data = " << iPfSet
<< std::endl;
// FIXME add a histogram to be used for a quality test
return;
} else if (iPfSet >= (static_cast<int>(pfSetsSize))) {
LogDebug("L1GtHwValidation")
<< "\nError: index of prescale factor set retrieved from the data \n"
<< "greater than the size of the vector of prescale factor sets."
<< "\n Value of index retrieved from data = " << iPfSet
<< "\n Vector size = " << pfSetsSize << std::endl;
// FIXME add a histogram to be used for a quality test
return;
}
const std::vector<int>& prescaleFactorsAlgoTrig =
(*m_prescaleFactorsAlgoTrig).at(iPfSet);
if (matchBxInEvent && validBxInEvent) {
for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
unsigned int triggerMask = (m_triggerMaskAlgoTrig.at(iBit)) & (1
<< PhysicsPartition);
int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
LogTrace("L1GtHwValidation") << "Bit " << iBit
<< ": prescale factor = " << prescaleFactor
<< " trigger mask = " << triggerMask << std::endl;
if (gtDecisionWordData[iBit]) {
m_fdlDataAlgoDecision[histIndex][iRec]->Fill(iBit);
if (prescaleFactor == 1) {
m_fdlDataAlgoDecisionUnprescaled[histIndex][iRec]->Fill(
iBit);
} else {
m_fdlDataAlgoDecisionPrescaled[histIndex][iRec]->Fill(iBit);
}
bitValue = (triggerMask) ? 0 : 1;
gtDecisionWordDataMask[iBit] = bitValue;
if (bitValue) {
m_fdlDataAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
}
}
if (gtDecisionWordEmul.at(iBit)) {
m_fdlEmulAlgoDecision[histIndex][iRec]->Fill(iBit);
bitValue = (triggerMask) ? 0 : 1;
gtDecisionWordEmulMask[iBit] = bitValue;
if (bitValue) {
m_fdlEmulAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
}
}
}
} else {
for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
if (gtDecisionWordData[iBit]) {
m_fdlDataAlgoDecision_Err[iRec]->Fill(iBit);
}
}
for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
if (gtDecisionWordEmul.at(iBit)) {
m_fdlEmulAlgoDecision_Err[iRec]->Fill(iBit);
}
}
if (iRec == 0) {
m_agree = false;
m_myCoutStream << "\nDisagreement data versus emulator: "
<< "\n matchBxInEvent && validBxInEvent false \n";
}
}
if (gtDecisionWordData == gtDecisionWordEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL gtDecisionWord identical.";
fdlBlockData.printGtDecisionWord(m_myCoutStream);
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL gtDecisionWord different.";
m_myCoutStream << "\n Data: ";
fdlBlockData.printGtDecisionWord(m_myCoutStream);
m_myCoutStream << "\n Emul: ";
fdlBlockEmul.printGtDecisionWord(m_myCoutStream);
m_myCoutStream << "\n";
if (matchBxInEvent && validBxInEvent) {
m_fdlDataEmul[histIndex][iRec]->Fill(6);
} else {
m_fdlDataEmul_Err[iRec]->Fill(6);
}
if (matchBxInEvent && validBxInEvent) {
for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
if (gtDecisionWordData[iBit] != gtDecisionWordEmul.at(iBit)) {
m_fdlDataEmulAlgoDecision[histIndex][iRec]->Fill(iBit);
// for excluded algorithms, fill mismatch for BxInEvent = 0 and DAQ record only
if (excludedAlgo(iBit) && (bxInEventData == 0) && (iRec
== 0)) {
m_excludedAlgorithmsAgreement->Fill(iBit);
}
if (prescaleFactor == 1) {
m_fdlDataEmulAlgoDecisionUnprescaled[histIndex][iRec]->Fill(
iBit);
// fill a histogram for allowed algorithm triggers only
if (!excludedAlgo(iBit)) {
m_fdlDataEmulAlgoDecisionUnprescaledAllowed[histIndex][iRec]->Fill(
iBit);
}
} else {
m_fdlDataEmulAlgoDecisionPrescaled[histIndex][iRec]->Fill(
iBit);
}
if (gtDecisionWordData[iBit]) {
m_fdlDataAlgoDecision_NoMatch[histIndex][iRec]->Fill(
iBit);
if (prescaleFactor == 1) {
m_fdlDataAlgoDecisionUnprescaled_NoMatch[histIndex][iRec]->Fill(
iBit);
// compare for agreement only unprescaled algorithms and algorithms which
// are not excluded from comparison
if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
&& (iRec == 0)) {
m_agree = false;
m_dataOnly = true;
m_myCoutStream
<< "\nDisagreement data versus emulator: "
<< "result before mask for algorithm with bit number "
<< iBit
<< "\n Data: true, emulator: false \n";
}
} else {
m_fdlDataAlgoDecisionPrescaled_NoMatch[histIndex][iRec]->Fill(
iBit);
}
} else {
m_fdlEmulAlgoDecision_NoMatch[histIndex][iRec]->Fill(
iBit);
if (prescaleFactor == 1) {
m_fdlEmulAlgoDecisionUnprescaled_NoMatch[histIndex][iRec]->Fill(
iBit);
// compare for agreement only unprescaled algorithms and algorithms which
// are not excluded from comparison
if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
&& (iRec == 0)) {
m_agree = false;
m_emulOnly = true;
m_myCoutStream
<< "\nDisagreement data versus emulator: "
<< "result before mask for algorithm with bit number "
<< iBit
<< "\n Data: false, emulator: true \n";
}
} else {
m_fdlEmulAlgoDecisionPrescaled_NoMatch[histIndex][iRec]->Fill(
iBit);
}
}
}
}
} else {
for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
if (gtDecisionWordData[iBit] != gtDecisionWordEmul.at(iBit)) {
m_fdlDataEmulAlgoDecision_Err[iRec]->Fill(iBit);
}
}
if (iRec == 0) {
m_agree = false;
m_myCoutStream << "\nDisagreement data versus emulator: "
<< "\n matchBxInEvent && validBxInEvent false \n";
}
}
}
if (gtDecisionWordDataMask == gtDecisionWordEmulMask) {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL gtDecisionWord after mask identical.";
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL gtDecisionWord after mask different.";
m_myCoutStream << "\n Data: ";
m_myCoutStream << "\n Emul: ";
m_myCoutStream << "\n";
if (matchBxInEvent && validBxInEvent) {
m_fdlDataEmul[histIndex][iRec]->Fill(7);
} else {
m_fdlDataEmul_Err[iRec]->Fill(7);
}
if (matchBxInEvent && validBxInEvent) {
for (int iBit = 0; iBit < nAlgoBits; ++iBit) {
if (gtDecisionWordDataMask[iBit] != gtDecisionWordEmulMask.at(
iBit)) {
m_fdlDataEmulAlgoDecisionMask[histIndex][iRec]->Fill(iBit);
int prescaleFactor = prescaleFactorsAlgoTrig.at(iBit);
if (gtDecisionWordDataMask[iBit]) {
m_fdlDataAlgoDecisionMask_NoMatch[histIndex][iRec]->Fill(
iBit);
if (prescaleFactor == 1) {
m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[histIndex][iRec]->Fill(
iBit);
// compare for agreement only unprescaled algorithms and algorithms which
// are not excluded from comparison
if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
&& (iRec == 0)) {
m_agree = false;
m_dataOnlyMask = true;
m_myCoutStream
<< "\nDisagreement data versus emulator: "
<< "result after mask for algorithm with bit number "
<< iBit
<< " different in data versus emulator "
<< "\n Data: true, emulator: false \n";
}
} else {
m_fdlDataAlgoDecisionPrescaledMask_NoMatch[histIndex][iRec]->Fill(
iBit);
}
} else {
m_fdlEmulAlgoDecisionMask_NoMatch[histIndex][iRec]->Fill(
iBit);
if (prescaleFactor == 1) {
m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[histIndex][iRec]->Fill(
iBit);
// compare for agreement only unprescaled algorithms and algorithms which
// are not excluded from comparison
if ((!excludedAlgo(iBit)) && (bxInEventData == 0)
&& (iRec == 0)) {
m_agree = false;
m_emulOnlyMask = true;
m_myCoutStream
<< "\nDisagreement data versus emulator: "
<< "result after mask for algorithm with bit number "
<< iBit
<< " different in data versus emulator "
<< "\n Data: false, emulator: true \n";
}
} else {
m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[histIndex][iRec]->Fill(
iBit);
}
}
}
}
}
}
// get extended algorithms bits (extended decision word)
const DecisionWordExtended gtDecisionWordExtendedData =
fdlBlockData.gtDecisionWordExtended();
const DecisionWordExtended gtDecisionWordExtendedEmul =
fdlBlockEmul.gtDecisionWordExtended();
if (gtDecisionWordExtendedData == gtDecisionWordExtendedEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL gtDecisionWordExtended identical.\n";
fdlBlockData.printGtDecisionWordExtended(m_myCoutStream);
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL gtDecisionWordExtended different.\n";
m_myCoutStream << "\n Data: ";
fdlBlockData.printGtDecisionWordExtended(m_myCoutStream);
m_myCoutStream << "\n Emul: ";
fdlBlockEmul.printGtDecisionWordExtended(m_myCoutStream);
m_myCoutStream << "\n";
if (matchBxInEvent && validBxInEvent) {
m_fdlDataEmul[histIndex][iRec]->Fill(8);
} else {
m_fdlDataEmul_Err[iRec]->Fill(8);
}
}
// get NoAlgo
const boost::uint16_t noAlgoData = fdlBlockData.noAlgo();
const boost::uint16_t noAlgoEmul = fdlBlockEmul.noAlgo();
if (noAlgoData == noAlgoEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL noAlgo identical.";
m_myCoutStream << "\n noAlgo() = " << noAlgoData;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL noAlgo different.";
m_myCoutStream << "\n Data: noAlgo() = " << noAlgoData;
m_myCoutStream << "\n Emul: noAlgo() = " << noAlgoEmul;
m_myCoutStream << "\n";
if (matchBxInEvent && validBxInEvent) {
m_fdlDataEmul[histIndex][iRec]->Fill(9);
} else {
m_fdlDataEmul_Err[iRec]->Fill(9);
}
}
// get "Final OR" bits
const boost::uint16_t finalORData = fdlBlockData.finalOR();
const boost::uint16_t finalOREmul = fdlBlockEmul.finalOR();
if (finalORData == finalOREmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL finalOR identical.";
m_myCoutStream << "\n finalOR() = " << std::hex << "0x" << std::setw(2)
<< std::setfill('0') << finalORData << std::setfill(' ')
<< std::dec;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL finalOR different.";
m_myCoutStream << "\n Data: finalOR() = " << std::hex << "0x"
<< std::setw(2) << std::setfill('0') << finalORData
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n Emul: finalOR() = " << std::hex << "0x"
<< std::setw(2) << std::setfill('0') << finalOREmul
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n";
if (matchBxInEvent && validBxInEvent) {
m_fdlDataEmul[histIndex][iRec]->Fill(10);
} else {
m_fdlDataEmul_Err[iRec]->Fill(10);
}
}
// get "Final OR" for physics partition
const int finalORPhysData = finalORData & (1 << PhysicsPartition);
const int finalORPhysEmul = finalOREmul & (1 << PhysicsPartition);
if (finalORPhysData == finalORPhysEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL finalOR for the physics partition identical.";
m_myCoutStream << "\n finalOR() = " << finalORPhysData;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL finalOR for the physics partition different.";
m_myCoutStream << "\n Data: finalOR() = " << finalORPhysData;
m_myCoutStream << "\n Emul: finalOR() = " << finalORPhysEmul;
m_myCoutStream << "\n";
if (matchBxInEvent && validBxInEvent) {
m_fdlDataEmul[histIndex][iRec]->Fill(11);
} else {
m_fdlDataEmul_Err[iRec]->Fill(11);
}
}
// get local bunch cross number of the actual bx
const boost::uint16_t localBxNrData = fdlBlockData.localBxNr();
const boost::uint16_t localBxNrEmul = fdlBlockEmul.localBxNr();
if (localBxNrData == localBxNrEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL localBxNr identical.";
m_myCoutStream << "\n localBxNr() = " << localBxNrData;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated FDL localBxNr different.";
m_myCoutStream << "\n Data: localBxNr() = " << localBxNrData;
m_myCoutStream << "\n Emul: localBxNr() = " << localBxNrEmul;
m_myCoutStream << "\n";
if (matchBxInEvent && validBxInEvent) {
m_fdlDataEmul[histIndex][iRec]->Fill(12);
} else {
m_fdlDataEmul_Err[iRec]->Fill(12);
}
}
edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
}
| void L1GtHwValidation::compareGt_Gct | ( | const edm::Event & | iEvent, |
| const edm::EventSetup & | |||
| ) | [private, virtual] |
compare the GCT collections obtained from L1 GT PSB with the input GCT collections
Definition at line 1849 of file L1GtHwValidation.cc.
Referenced by analyze().
{
// FIXME
}
| void L1GtHwValidation::compareGTFE | ( | const edm::Event & | iEvent, |
| const edm::EventSetup & | evSetup, | ||
| const L1GtfeWord & | gtfeBlockData, | ||
| const L1GtfeWord & | gtfeBlockEmul, | ||
| const int | iRec | ||
| ) | [private, virtual] |
compare the GTFE board
get record length for alternative 1
get record length for alternative 0
get bunch cross number as counted in the GTFE board
get setup version
get boards contributing to EVM respectively DAQ record
alternative for number of BX per board correlated with active boards bit value is 0: take alternative 0 bit value is 1: take alternative 1
get total number of L1A sent since start of run
Definition at line 405 of file L1GtHwValidation.cc.
References L1GtfeWord::activeBoards(), L1GtfeWord::altNrBxBoard(), L1GtfeWord::boardId(), L1GtfeWord::bxNr(), MonitorElement::Fill(), LogDebug, m_dbe, m_dirName, m_gtfeDataEmul, m_myCoutStream, L1GtfeWord::print(), L1GtfeWord::recordLength(), L1GtfeWord::recordLength1(), DQMStore::setCurrentFolder(), L1GtfeWord::setupVersion(), and L1GtfeWord::totalTriggerNr().
Referenced by compareDaqRecord(), and compareEvmRecord().
{
std::string recString;
if (iRec == 0) {
recString = "DAQ";
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName + "/DAQ/");
}
} else {
recString = "EVM";
if (m_dbe) {
m_dbe->setCurrentFolder(m_dirName + "/EVM/");
}
}
if (gtfeBlockData == gtfeBlockEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE blocks: identical.\n";
gtfeBlockData.print(m_myCoutStream);
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE blocks: different.\n";
m_myCoutStream << "\nData: GTFE block\n";
gtfeBlockData.print(m_myCoutStream);
m_myCoutStream << "\nEmul: GTFE block\n";
gtfeBlockEmul.print(m_myCoutStream);
}
LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
// get BoardId value
const boost::uint16_t boardIdData = gtfeBlockData.boardId();
const boost::uint16_t boardIdEmul = gtfeBlockEmul.boardId();
if (boardIdData == boardIdEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE boardId identical.";
m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4)
<< std::setfill('0') << boardIdData << std::setfill(' ')
<< std::dec;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE boardId different.";
m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x"
<< std::setw(4) << std::setfill('0') << boardIdData
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x"
<< std::setw(4) << std::setfill('0') << boardIdEmul
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n";
m_gtfeDataEmul[iRec]->Fill(0);
}
const boost::uint16_t recordLength1Data = gtfeBlockData.recordLength1();
const boost::uint16_t recordLength1Emul = gtfeBlockEmul.recordLength1();
if (recordLength1Data == recordLength1Emul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE recordLength for alternative 1 identical.";
m_myCoutStream << "\n recordLength1() = " << recordLength1Data;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE recordLength for alternative 1 different.";
m_myCoutStream << "\n Data: recordLength1() = " << recordLength1Data;
m_myCoutStream << "\n Emul: recordLength1() = " << recordLength1Emul;
m_myCoutStream << "\n";
m_gtfeDataEmul[iRec]->Fill(1);
}
const boost::uint16_t recordLengthData = gtfeBlockData.recordLength();
const boost::uint16_t recordLengthEmul = gtfeBlockEmul.recordLength();
if (recordLengthData == recordLengthEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE recordLength for alternative 0 identical.";
m_myCoutStream << "\n recordLength() = " << recordLengthData;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE recordLength for alternative 1 different.";
m_myCoutStream << "\n Data: recordLength() = " << recordLengthData;
m_myCoutStream << "\n Emul: recordLength() = " << recordLengthEmul;
m_myCoutStream << "\n";
m_gtfeDataEmul[iRec]->Fill(2);
}
const boost::uint16_t bxNrData = gtfeBlockData.bxNr();
const boost::uint16_t bxNrEmul = gtfeBlockEmul.bxNr();
if (bxNrData == bxNrEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE bxNr identical.";
m_myCoutStream << "\n bxNr() = " << bxNrData;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE bxNr different.";
m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
m_myCoutStream << "\n";
m_gtfeDataEmul[iRec]->Fill(3);
}
const boost::uint32_t setupVersionData = gtfeBlockData.setupVersion();
const boost::uint32_t setupVersionEmul = gtfeBlockEmul.setupVersion();
if (setupVersionData == setupVersionEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE setupVersion identical.";
m_myCoutStream << "\n setupVersion() = " << setupVersionData;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE setupVersion different.";
m_myCoutStream << "\n Data: setupVersion() = " << setupVersionData;
m_myCoutStream << "\n Emul: setupVersion() = " << setupVersionEmul;
m_myCoutStream << "\n";
m_gtfeDataEmul[iRec]->Fill(4);
}
const boost::uint16_t activeBoardsData = gtfeBlockData.activeBoards();
const boost::uint16_t activeBoardsEmul = gtfeBlockEmul.activeBoards();
if (activeBoardsData == activeBoardsEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE activeBoards identical.";
m_myCoutStream << "\n activeBoards() = " << std::hex << "0x"
<< std::setw(4) << std::setfill('0') << activeBoardsData
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE activeBoards different.";
m_myCoutStream << "\n Data: activeBoards() = " << std::hex << "0x"
<< std::setw(4) << std::setfill('0') << activeBoardsData
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n Emul: activeBoards() = " << std::hex << "0x"
<< std::setw(4) << std::setfill('0') << activeBoardsEmul
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n";
m_gtfeDataEmul[iRec]->Fill(5);
}
const boost::uint16_t altNrBxBoardData = gtfeBlockData.altNrBxBoard();
const boost::uint16_t altNrBxBoardEmul = gtfeBlockEmul.altNrBxBoard();
if (altNrBxBoardData == altNrBxBoardEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE altNrBxBoard identical.";
m_myCoutStream << "\n altNrBxBoard() = " << altNrBxBoardData;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE altNrBxBoard different.";
m_myCoutStream << "\n Data: altNrBxBoard() = " << altNrBxBoardData;
m_myCoutStream << "\n Emul: altNrBxBoard() = " << altNrBxBoardEmul;
m_myCoutStream << "\n";
m_gtfeDataEmul[iRec]->Fill(6);
}
const boost::uint32_t totalTriggerNrData = gtfeBlockData.totalTriggerNr();
const boost::uint32_t totalTriggerNrEmul = gtfeBlockEmul.totalTriggerNr();
if (totalTriggerNrData == totalTriggerNrEmul) {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE totalTriggerNr identical.";
m_myCoutStream << "\n totalTriggerNr() = " << totalTriggerNrData;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\n" << recString
<< " Data and emulated GTFE totalTriggerNr different.";
m_myCoutStream << "\n Data: totalTriggerNr() = " << totalTriggerNrData;
m_myCoutStream << "\n Emul: totalTriggerNr() = " << totalTriggerNrEmul;
m_myCoutStream << "\n";
m_gtfeDataEmul[iRec]->Fill(7);
}
edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
}
| void L1GtHwValidation::comparePSB | ( | const edm::Event & | iEvent, |
| const edm::EventSetup & | evSetup, | ||
| const L1GtPsbWord & | psbBlockData, | ||
| const L1GtPsbWord & | psbBlockEmul | ||
| ) | [private, virtual] |
compare the PSB board
get/set A_DATA_CH_IA
get/set B_DATA_CH_IB
Definition at line 1397 of file L1GtHwValidation.cc.
References L1GtPsbWord::aData(), L1GtPsbWord::bData(), L1GtPsbWord::boardId(), L1GtPsbWord::bxInEvent(), L1GtPsbWord::bxNr(), L1GtPsbWord::eventNr(), L1GtPsbWord::localBxNr(), LogDebug, m_myCoutStream, L1GtPsbWord::NumberAData, L1GtPsbWord::NumberBData, and L1GtPsbWord::print().
Referenced by compareDaqRecord().
{
if (psbBlockData == psbBlockEmul) {
m_myCoutStream << "\nData and emulated PSB blocks: identical.\n";
psbBlockData.print(m_myCoutStream);
} else {
m_myCoutStream << "\nData and emulated PSB blocks: different.\n";
m_myCoutStream << "\nData: PSB block\n";
psbBlockData.print(m_myCoutStream);
m_myCoutStream << "\nEmul: PSB block\n";
psbBlockEmul.print(m_myCoutStream);
}
LogDebug("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
// get BoardId value
const boost::uint16_t boardIdData = psbBlockData.boardId();
const boost::uint16_t boardIdEmul = psbBlockEmul.boardId();
if (boardIdData == boardIdEmul) {
m_myCoutStream << "\nData and emulated PSB boardId identical.";
m_myCoutStream << "\n boardId() = " << std::hex << "0x" << std::setw(4)
<< std::setfill('0') << boardIdData << std::setfill(' ')
<< std::dec;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\nData and emulated PSB boardId different.";
m_myCoutStream << "\n Data: boardId() = " << std::hex << "0x"
<< std::setw(4) << std::setfill('0') << boardIdData
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n Emul: boardId() = " << std::hex << "0x"
<< std::setw(4) << std::setfill('0') << boardIdEmul
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n";
}
// get bunch cross in the GT event record
const int bxInEventData = psbBlockData.bxInEvent();
const int bxInEventEmul = psbBlockEmul.bxInEvent();
if (bxInEventData == bxInEventEmul) {
m_myCoutStream << "\nData and emulated PSB bxInEvent identical.";
m_myCoutStream << "\n bxInEvent() = " << bxInEventData;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\nData and emulated PSB bxInEvent different.";
m_myCoutStream << "\n Data: bxInEvent() = " << bxInEventData;
m_myCoutStream << "\n Emul: bxInEvent() = " << bxInEventEmul;
m_myCoutStream << "\n";
}
// get BxNr - bunch cross number of the actual bx
const boost::uint16_t bxNrData = psbBlockData.bxNr();
const boost::uint16_t bxNrEmul = psbBlockEmul.bxNr();
if (bxNrData == bxNrEmul) {
m_myCoutStream << "\nData and emulated PSB bxNr identical.";
m_myCoutStream << "\n bxNr() = " << bxNrData;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\nData and emulated PSB bxNr different.";
m_myCoutStream << "\n Data: bxNr() = " << bxNrData;
m_myCoutStream << "\n Emul: bxNr() = " << bxNrEmul;
m_myCoutStream << "\n";
}
// get event number since last L1 reset generated in FDL
const boost::uint32_t eventNrData = psbBlockData.eventNr();
const boost::uint32_t eventNrEmul = psbBlockEmul.eventNr();
if (eventNrData == eventNrEmul) {
m_myCoutStream << "\nData and emulated PSB eventNr identical.";
m_myCoutStream << "\n eventNr() = " << eventNrData;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\nData and emulated PSB eventNr different.";
m_myCoutStream << "\n Data: eventNr() = " << eventNrData;
m_myCoutStream << "\n Emul: eventNr() = " << eventNrEmul;
m_myCoutStream << "\n";
}
boost::uint16_t valData;
boost::uint16_t valEmul;
for (int iA = 0; iA < psbBlockData.NumberAData; ++iA) {
valData = psbBlockData.aData(iA);
valEmul = psbBlockEmul.aData(iA);
if (valData == valEmul) {
m_myCoutStream << "\nData and emulated PSB aData(" << iA
<< ") identical.";
m_myCoutStream << "\n aData(iA) = " << std::hex << "0x"
<< std::setw(4) << std::setfill('0') << valData
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\nData and emulated PSB aData(" << iA
<< ") different.";
m_myCoutStream << "\n Data: aData(iA) = " << std::hex << "0x"
<< std::setw(4) << std::setfill('0') << valData
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n Emul: aData(iA) = " << std::hex << "0x"
<< std::setw(4) << std::setfill('0') << valEmul
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n";
}
}
for (int iB = 0; iB < psbBlockData.NumberBData; ++iB) {
valData = psbBlockData.bData(iB);
valEmul = psbBlockEmul.bData(iB);
if (valData == valEmul) {
m_myCoutStream << "\nData and emulated PSB bData(" << iB
<< ") identical.";
m_myCoutStream << "\n bData(iA) = " << std::hex << "0x"
<< std::setw(4) << std::setfill('0') << valData
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\nData and emulated PSB bData(" << iB
<< ") different.";
m_myCoutStream << "\n Data: bData(iA) = " << std::hex << "0x"
<< std::setw(4) << std::setfill('0') << valData
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n Emul: bData(iA) = " << std::hex << "0x"
<< std::setw(4) << std::setfill('0') << valEmul
<< std::setfill(' ') << std::dec;
m_myCoutStream << "\n";
}
}
// get local bunch cross number of the actual bx
const boost::uint16_t localBxNrData = psbBlockData.localBxNr();
const boost::uint16_t localBxNrEmul = psbBlockEmul.localBxNr();
if (localBxNrData == localBxNrEmul) {
m_myCoutStream << "\nData and emulated PSB localBxNr identical.";
m_myCoutStream << "\n localBxNr() = " << localBxNrData;
m_myCoutStream << "\n";
} else {
m_myCoutStream << "\nData and emulated PSB localBxNr different.";
m_myCoutStream << "\n Data: localBxNr() = " << localBxNrData;
m_myCoutStream << "\n Emul: localBxNr() = " << localBxNrEmul;
m_myCoutStream << "\n";
}
edm::LogInfo("L1GtHwValidation") << m_myCoutStream.str() << std::endl;
m_myCoutStream.str("");
m_myCoutStream.clear();
}
| void L1GtHwValidation::compareTCS | ( | const edm::Event & | iEvent, |
| const edm::EventSetup & | evSetup, | ||
| const L1TcsWord & | , | ||
| const L1TcsWord & | |||
| ) | [private, virtual] |
| void L1GtHwValidation::endJob | ( | void | ) | [private, virtual] |
Reimplemented from edm::EDAnalyzer.
Definition at line 2727 of file L1GtHwValidation.cc.
References m_nrEvJob.
{
edm::LogInfo("L1GtHwValidation")
<< "\n\nTotal number of events analyzed in this job: " << m_nrEvJob
<< "\n" << std::endl;
return;
}
| void L1GtHwValidation::endRun | ( | const edm::Run & | run, |
| const edm::EventSetup & | c | ||
| ) | [private, virtual] |
Reimplemented from edm::EDAnalyzer.
Definition at line 2716 of file L1GtHwValidation.cc.
References edm::RunBase::id(), LogDebug, m_nrEvJob, and m_nrEvRun.
| bool L1GtHwValidation::excludedAlgo | ( | const int & | iBit | ) | const [private] |
exclusion status for algorithm with bit i
Definition at line 2701 of file L1GtHwValidation.cc.
References m_excludedAlgoList.
Referenced by compareFDL().
{
for (std::vector<int>::const_iterator itAlgo = m_excludedAlgoList.begin(); itAlgo
!= m_excludedAlgoList.end(); ++itAlgo) {
if (iBit == *itAlgo) {
return true;
}
}
return false;
}
| void L1GtHwValidation::excludedAlgoList | ( | ) | [private] |
exclude from comparison some bits with known disagreement - bit list
Definition at line 2545 of file L1GtHwValidation.cc.
References asciidump::at, L1GtTriggerMenu::gtAlgorithmMap(), L1GtTriggerMenu::gtConditionMap(), l1GtConditionCategoryEnumToString(), l1GtConditionTypeEnumToString(), l1GtObjectEnumToString(), LogTrace, m_excludeAlgoTrigByBit, m_excludeAlgoTrigByName, m_excludedAlgoList, m_excludedCondCategory, m_excludedCondType, m_excludedL1GtObject, m_l1GtMenu, matchCondCategory(), matchCondL1GtObject(), and matchCondType().
Referenced by beginRun().
{
const AlgorithmMap& algorithmMap = m_l1GtMenu->gtAlgorithmMap();
(const_cast<L1GtTriggerMenu*> (m_l1GtMenu))->buildGtConditionMap(); //...ugly
for (CItAlgo itAlgo = algorithmMap.begin(); itAlgo != algorithmMap.end(); itAlgo++) {
const std::string& algName = itAlgo->first;
const int algBitNumber = (itAlgo->second).algoBitNumber();
const int chipNr = (itAlgo->second).algoChipNumber();
const ConditionMap& conditionMap = (m_l1GtMenu->gtConditionMap()).at(
chipNr);
const std::vector<L1GtLogicParser::TokenRPN>& aRpnVector =
(itAlgo->second).algoRpnVector();
size_t aRpnVectorSize = aRpnVector.size();
bool algWithExcludedCondition = false;
bool algWithConditionNotInMap = false;
// loop over RpnVector and check each conditions against list of excluded conditions
for (size_t opI = 0; opI < aRpnVectorSize; ++opI) {
const std::string& cndName = (aRpnVector[opI]).operand;
if (!cndName.empty()) {
bool foundCond = false;
CItCond itCond = conditionMap.find(cndName);
if (itCond != conditionMap.end()) {
const L1GtConditionCategory& cCateg = (itCond->second)->condCategory();
const L1GtConditionType& cType = (itCond->second)->condType();
const std::vector<L1GtObject>& objType = (itCond->second)->objectType();
// condition index in the m_excludedCondCategory, m_excludedCondType, m_excludedL1GtObject vectors
int iCond = -1;
for (std::vector<L1GtConditionCategory>::const_iterator
itCateg = m_excludedCondCategory.begin();
itCateg != m_excludedCondCategory.end(); ++itCateg) {
iCond++;
bool matchCondCategoryValue = matchCondCategory(cCateg, (*itCateg));
bool matchCondTypeValue = matchCondType(cType, m_excludedCondType.at(iCond));
bool matchCondL1GtObjectValue = matchCondL1GtObject(objType, m_excludedL1GtObject.at(iCond));
LogTrace("L1GtHwValidation")
<< "\n "
<< "Algorithm: " << algName
<< " Condition: " << cndName
<< "\n "
<< "Category: " << l1GtConditionCategoryEnumToString(cCateg)
<< "; excluded: " << l1GtConditionCategoryEnumToString((*itCateg))
<< "\n "
<< "Type: " << l1GtConditionTypeEnumToString(cType)
<< "; excluded: " << l1GtConditionTypeEnumToString(m_excludedCondType.at(iCond))
<< "\n "
<< "Object excluded: " << l1GtObjectEnumToString(m_excludedL1GtObject.at(iCond))
<< std::endl;
if (matchCondCategoryValue && matchCondTypeValue && matchCondL1GtObjectValue) {
algWithExcludedCondition = true;
}
}
foundCond = true;
}
if (!foundCond) {
// it should never be happen, all conditions are in the maps
algWithConditionNotInMap = true;
LogTrace("L1GtHwValidation") << "\n Error: condition "
<< cndName << " not found in condition map!"
<< "\n Add algorithm " << algName
<< " (bit number " << algBitNumber << ") "
<< "\n to list of algorithms excluded from comparison"
<< "\n data versus emulator." << std::endl;
}
}
}
if (algWithConditionNotInMap) {
// it should never be happen, all conditions are in the maps
m_excludedAlgoList.push_back(algBitNumber);
LogTrace("L1GtHwValidation")
<< "\n Error: one or more conditions from algorithm "
<< algName << " (bit number " << algBitNumber << ") "
<< " not found in condition map!"
<< "\n Add it to list of algorithms excluded from comparison"
<< "\n data versus emulator." << std::endl;
}
if (algWithExcludedCondition) {
m_excludedAlgoList.push_back(algBitNumber);
LogTrace("L1GtHwValidation") << "\n Algorithm " << algName
<< " (bit number " << algBitNumber
<< ") contains an excluded condition."
<< "\n Add it to list of algorithms excluded from comparison"
<< "\n data versus emulator." << std::endl;
}
// add algorithm triggers from ExcludeAlgoTrigByName
for (std::vector<std::string>::const_iterator
itExcl = m_excludeAlgoTrigByName.begin();
itExcl!= m_excludeAlgoTrigByName.end(); ++itExcl) {
if ((*itExcl) == algName) {
m_excludedAlgoList.push_back(algBitNumber);
LogTrace("L1GtHwValidation") << "\n Algorithm " << algName
<< " (bit number " << algBitNumber
<< ")\n added to list of algorithms excluded from comparison"
<< " \n data versus emulator by ExcludeAlgoTrigByName." << std::endl;
}
}
// add algorithm triggers from ExcludeAlgoTrigByBit
for (std::vector<int>::const_iterator
itExcl = m_excludeAlgoTrigByBit.begin();
itExcl!= m_excludeAlgoTrigByBit.end(); ++itExcl) {
if ((*itExcl) == algBitNumber) {
m_excludedAlgoList.push_back(algBitNumber);
LogTrace("L1GtHwValidation") << "\n Algorithm " << algName
<< " (bit number " << algBitNumber
<< ")\n added to list of algorithms excluded from comparison"
<< " \n data versus emulator by ExcludeAlgoTrigByBit." << std::endl;
}
}
}
}
| bool L1GtHwValidation::matchCondCategory | ( | const L1GtConditionCategory & | conditionCategory, |
| const L1GtConditionCategory & | excludedCategory | ||
| ) | [private] |
return true if an algorithm has a condition of that category for CondNull, it returns always true
Definition at line 2482 of file L1GtHwValidation.cc.
References CondNull.
Referenced by excludedAlgoList().
{
bool matchValue = false;
if (excludedCategory == CondNull) {
matchValue = true;
} else {
if (conditionCategory == excludedCategory) {
matchValue = true;
}
}
return matchValue;
}
| bool L1GtHwValidation::matchCondL1GtObject | ( | const std::vector< L1GtObject > & | condObjects, |
| const L1GtObject & | excludedObject | ||
| ) | [private] |
return true if an algorithm has a condition containing that object for ObjNull, it returns always true
Definition at line 2517 of file L1GtHwValidation.cc.
References ObjNull.
Referenced by excludedAlgoList().
{
bool matchValue = false;
if (excludedObject == ObjNull) {
matchValue = true;
} else {
for (std::vector<L1GtObject>::const_iterator itCondObj =
condObjects.begin(); itCondObj != condObjects.end(); ++itCondObj) {
if ((*itCondObj) == excludedObject) {
matchValue = true;
}
}
}
return matchValue;
}
| bool L1GtHwValidation::matchCondType | ( | const L1GtConditionType & | conditionType, |
| const L1GtConditionType & | excludedType | ||
| ) | [private] |
return true if an algorithm has a condition of that type for TypeNull, it returns always true
Definition at line 2500 of file L1GtHwValidation.cc.
References TypeNull.
Referenced by excludedAlgoList().
{
bool matchValue = false;
if (excludedType == TypeNull) {
matchValue = true;
} else {
if (conditionType == excludedType) {
matchValue = true;
}
}
return matchValue;
}
bool L1GtHwValidation::m_agree [private] |
Definition at line 198 of file L1GtHwValidation.h.
Referenced by compareDaqRecord(), and compareFDL().
bool L1GtHwValidation::m_dataOnly [private] |
Definition at line 199 of file L1GtHwValidation.h.
Referenced by compareDaqRecord(), and compareFDL().
bool L1GtHwValidation::m_dataOnlyMask [private] |
Definition at line 201 of file L1GtHwValidation.h.
Referenced by compareDaqRecord(), and compareFDL().
DQMStore* L1GtHwValidation::m_dbe [private] |
internal members
Definition at line 196 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), compareDaqRecord(), compareFDL(), compareGTFE(), and L1GtHwValidation().
std::string L1GtHwValidation::m_dirName [private] |
directory name for L1Extra plots
Definition at line 134 of file L1GtHwValidation.h.
Referenced by beginJob(), beginRun(), bookHistograms(), compareDaqRecord(), compareFDL(), compareGTFE(), and L1GtHwValidation().
bool L1GtHwValidation::m_emulOnly [private] |
Definition at line 200 of file L1GtHwValidation.h.
Referenced by compareDaqRecord(), and compareFDL().
bool L1GtHwValidation::m_emulOnlyMask [private] |
Definition at line 202 of file L1GtHwValidation.h.
Referenced by compareDaqRecord(), and compareFDL().
std::vector<int> L1GtHwValidation::m_excludeAlgoTrigByBit [private] |
exclude algorithm triggers from comparison data - emulator by algorithm bit number
Definition at line 144 of file L1GtHwValidation.h.
Referenced by excludedAlgoList().
std::vector<std::string> L1GtHwValidation::m_excludeAlgoTrigByName [private] |
exclude algorithm triggers from comparison data - emulator by algorithm name
Definition at line 141 of file L1GtHwValidation.h.
Referenced by excludedAlgoList().
std::vector<edm::ParameterSet> L1GtHwValidation::m_excludeCondCategTypeObject [private] |
exclude algorithm triggers from comparison data - emulator by condition category and / or type
Definition at line 138 of file L1GtHwValidation.h.
Referenced by L1GtHwValidation().
std::vector<int> L1GtHwValidation::m_excludedAlgoList [private] |
Definition at line 278 of file L1GtHwValidation.h.
Referenced by beginRun(), excludedAlgo(), and excludedAlgoList().
Definition at line 263 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
std::vector<L1GtConditionCategory> L1GtHwValidation::m_excludedCondCategory [private] |
excluded condition categories
Definition at line 150 of file L1GtHwValidation.h.
Referenced by excludedAlgoList(), and L1GtHwValidation().
std::vector<L1GtConditionType> L1GtHwValidation::m_excludedCondType [private] |
excluded condition types
Definition at line 153 of file L1GtHwValidation.h.
Referenced by excludedAlgoList(), and L1GtHwValidation().
std::vector<L1GtObject> L1GtHwValidation::m_excludedL1GtObject [private] |
excluded L1 GT objects
Definition at line 156 of file L1GtHwValidation.h.
Referenced by excludedAlgoList(), and L1GtHwValidation().
MonitorElement* L1GtHwValidation::m_fdlDataAlgoDecision[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 217 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
Definition at line 227 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataAlgoDecision_NoMatch[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 221 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataAlgoDecisionMask[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 220 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataAlgoDecisionMask_NoMatch[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 224 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataAlgoDecisionPrescaled[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 218 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataAlgoDecisionPrescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 222 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataAlgoDecisionPrescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 225 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 219 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataAlgoDecisionUnprescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 223 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataAlgoDecisionUnprescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 226 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
FDL (0 for DAQ, 1 for EVM record)
Definition at line 215 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
Definition at line 248 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataEmulAlgoDecision[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 242 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
Definition at line 247 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataEmulAlgoDecisionMask[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 246 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataEmulAlgoDecisionPrescaled[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 243 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataEmulAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 244 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataEmulAlgoDecisionUnprescaledAllowed[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 245 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataEmulTechDecision[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 259 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
Definition at line 261 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataEmulTechDecisionMask[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 260 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataTechDecision[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 251 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
Definition at line 253 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlDataTechDecisionMask[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 252 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlEmulAlgoDecision[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 229 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
Definition at line 239 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlEmulAlgoDecision_NoMatch[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 233 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlEmulAlgoDecisionMask[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 232 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlEmulAlgoDecisionMask_NoMatch[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 236 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlEmulAlgoDecisionPrescaled[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 230 of file L1GtHwValidation.h.
Referenced by beginRun(), and bookHistograms().
MonitorElement* L1GtHwValidation::m_fdlEmulAlgoDecisionPrescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 234 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlEmulAlgoDecisionPrescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 237 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaled[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 231 of file L1GtHwValidation.h.
Referenced by beginRun(), and bookHistograms().
MonitorElement* L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaled_NoMatch[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 235 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlEmulAlgoDecisionUnprescaledMask_NoMatch[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 238 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlEmulTechDecision[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 255 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
Definition at line 257 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_fdlEmulTechDecisionMask[TotalBxInEvent][NumberOfGtRecords] [private] |
Definition at line 256 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareFDL().
MonitorElement* L1GtHwValidation::m_gtErrorFlag [private] |
PSB.
ErrorFlag a la HardwareValidation
Definition at line 270 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareDaqRecord().
histograms
GTFE
Definition at line 212 of file L1GtHwValidation.h.
Referenced by bookHistograms(), and compareGTFE().
input tag for the L1 GCT hardware record
Definition at line 131 of file L1GtHwValidation.h.
Referenced by L1GtHwValidation().
input tag for the L1 GT hardware DAQ record
Definition at line 119 of file L1GtHwValidation.h.
Referenced by compareDaqRecord(), and L1GtHwValidation().
input tag for the L1 GT hardware EVM record
Definition at line 122 of file L1GtHwValidation.h.
Referenced by compareEvmRecord(), and L1GtHwValidation().
input tag for the L1 GT emulator DAQ record
Definition at line 125 of file L1GtHwValidation.h.
Referenced by compareDaqRecord(), and L1GtHwValidation().
input tag for the L1 GT emulator EVM record
Definition at line 128 of file L1GtHwValidation.h.
Referenced by compareEvmRecord(), and L1GtHwValidation().
const L1GtTriggerMenu* L1GtHwValidation::m_l1GtMenu [private] |
trigger menu
Definition at line 169 of file L1GtHwValidation.h.
Referenced by beginRun(), and excludedAlgoList().
unsigned long long L1GtHwValidation::m_l1GtMenuCacheID [private] |
Definition at line 170 of file L1GtHwValidation.h.
Referenced by beginRun().
const L1GtPrescaleFactors* L1GtHwValidation::m_l1GtPfAlgo [private] |
unsigned long long L1GtHwValidation::m_l1GtPfAlgoCacheID [private] |
Definition at line 174 of file L1GtHwValidation.h.
Referenced by beginRun().
const L1GtPrescaleFactors* L1GtHwValidation::m_l1GtPfTech [private] |
Definition at line 176 of file L1GtHwValidation.h.
Referenced by beginRun().
unsigned long long L1GtHwValidation::m_l1GtPfTechCacheID [private] |
Definition at line 177 of file L1GtHwValidation.h.
Referenced by beginRun().
const L1GtTriggerMask* L1GtHwValidation::m_l1GtTmAlgo [private] |
unsigned long long L1GtHwValidation::m_l1GtTmAlgoCacheID [private] |
Definition at line 184 of file L1GtHwValidation.h.
Referenced by beginRun().
const L1GtTriggerMask* L1GtHwValidation::m_l1GtTmTech [private] |
Definition at line 186 of file L1GtHwValidation.h.
Referenced by beginRun().
unsigned long long L1GtHwValidation::m_l1GtTmTechCacheID [private] |
Definition at line 187 of file L1GtHwValidation.h.
Referenced by beginRun().
std::ostringstream L1GtHwValidation::m_myCoutStream [private] |
an output stream to print into it can then be directed to whatever log level is desired
Definition at line 160 of file L1GtHwValidation.h.
Referenced by compareDaqRecord(), compareEvmRecord(), compareFDL(), compareGTFE(), and comparePSB().
int L1GtHwValidation::m_nrDataEventError [private] |
counters
Definition at line 163 of file L1GtHwValidation.h.
Referenced by compareDaqRecord(), and compareEvmRecord().
int L1GtHwValidation::m_nrEmulEventError [private] |
Definition at line 164 of file L1GtHwValidation.h.
Referenced by compareDaqRecord(), and compareEvmRecord().
int L1GtHwValidation::m_nrEvJob [private] |
Definition at line 274 of file L1GtHwValidation.h.
int L1GtHwValidation::m_nrEvRun [private] |
Definition at line 275 of file L1GtHwValidation.h.
Referenced by analyze(), beginRun(), and endRun().
const std::vector<std::vector<int> >* L1GtHwValidation::m_prescaleFactorsAlgoTrig [private] |
Definition at line 179 of file L1GtHwValidation.h.
Referenced by beginRun().
const std::vector<std::vector<int> >* L1GtHwValidation::m_prescaleFactorsTechTrig [private] |
Definition at line 180 of file L1GtHwValidation.h.
Referenced by beginRun().
std::vector<unsigned int> L1GtHwValidation::m_triggerMaskAlgoTrig [private] |
Definition at line 189 of file L1GtHwValidation.h.
Referenced by beginRun(), and compareFDL().
std::vector<unsigned int> L1GtHwValidation::m_triggerMaskTechTrig [private] |
Definition at line 190 of file L1GtHwValidation.h.
Referenced by beginRun(), and compareFDL().
const int L1GtHwValidation::NumberOfGtRecords = 2 [static, private] |
Definition at line 207 of file L1GtHwValidation.h.
Referenced by beginRun(), and bookHistograms().
const int L1GtHwValidation::TotalBxInEvent = 5 [static, private] |
Definition at line 206 of file L1GtHwValidation.h.
Referenced by beginRun(), bookHistograms(), and compareFDL().
1.7.3