Reference Manual

Go to the documentation of this file.
00001 // Last commit: $Id: SiStripFecCabling.cc,v 1.29 2010/02/20 20:55:05 wmtan Exp $
00002 
00003 #include "FWCore/Utilities/interface/typelookup.h"
00004 #include "CalibFormats/SiStripObjects/interface/SiStripFecCabling.h"
00005 #include "DataFormats/SiStripCommon/interface/SiStripConstants.h"
00006 #include "FWCore/MessageLogger/interface/MessageLogger.h"
00007 #include <iostream>
00008 #include <iomanip>
00009 
00010 using namespace sistrip;
00011 
00012 // -----------------------------------------------------------------------------
00013 //
00014 SiStripFecCabling::SiStripFecCabling( const SiStripFedCabling& fed_cabling ) 
00015   : crates_() 
00016 {
00017   LogTrace(mlCabling_)
00018     << "[SiStripFecCabling::" << __func__ << "]"
00019     << " Constructing object...";
00020   crates_.reserve(4);
00021   buildFecCabling( fed_cabling );
00022 }
00023 
00024 // -----------------------------------------------------------------------------
00025 //
00026 void SiStripFecCabling::buildFecCabling( const SiStripFedCabling& fed_cabling ) {
00027   LogTrace(mlCabling_)
00028     << "[SiStripFecCabling::" << __func__ << "]"
00029     << " Building FEC cabling...";
00030 
00031   // Retrieve and iterate through FED ids
00032   const std::vector<uint16_t>& feds = fed_cabling.feds();
00033   std::vector<uint16_t>::const_iterator ifed;
00034   for ( ifed = feds.begin(); ifed != feds.end(); ifed++ ) {
00035 
00036     // Retrieve and iterate through FED channel connections
00037     const std::vector<FedChannelConnection>& conns = fed_cabling.connections( *ifed ); 
00038     std::vector<FedChannelConnection>::const_iterator iconn;
00039     for ( iconn = conns.begin(); iconn != conns.end(); iconn++ ) {
00040 
00041       // Check that FED id is not invalid and add devices
00042       if ( iconn->fedId() != sistrip::invalid_ ) { addDevices( *iconn ); } 
00043       
00044     }
00045   }
00046 
00047   // Consistency checks
00048   for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
00049     for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
00050       for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
00051         for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
00052           for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
00053             //@@ need consistency checks here!
00054           }
00055         }
00056       }
00057     }
00058   }
00059   LogTrace(mlCabling_)
00060     << "[SiStripFecCabling::" << __func__ << "]"
00061     << " Finished building FEC cabling";
00062 }
00063 
00064 // -----------------------------------------------------------------------------
00065 //
00066 void SiStripFecCabling::addDevices( const FedChannelConnection& conn ) {
00067   std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin();
00068   while ( icrate != crates().end() && (*icrate).fecCrate() != conn.fecCrate() ) { icrate++; }
00069   if ( icrate == crates().end() ) { 
00070     crates_.push_back( SiStripFecCrate( conn ) ); 
00071   } else { 
00072     const_cast<SiStripFecCrate&>(*icrate).addDevices( conn ); 
00073   }
00074 }
00075 
00076 // -----------------------------------------------------------------------------
00077 //
00078 void SiStripFecCabling::connections( std::vector<FedChannelConnection>& conns ) const {
00079   LogTrace(mlCabling_)
00080     << "[SiStripFecCabling::" << __func__ << "]"
00081     << " Building vector of FedChannelConnection objects...";
00082   conns.clear();
00083   for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
00084     for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
00085       for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
00086         for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
00087           for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
00088             for ( uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++ ) {
00089               conns.push_back( FedChannelConnection( icrate->fecCrate(), 
00090                                                      ifec->fecSlot(), 
00091                                                      iring->fecRing(), 
00092                                                      iccu->ccuAddr(), 
00093                                                      imod->ccuChan(), 
00094                                                      imod->activeApvPair( imod->lldChannel(ipair) ).first, 
00095                                                      imod->activeApvPair( imod->lldChannel(ipair) ).second,
00096                                                      imod->dcuId(), 
00097                                                      imod->detId(), 
00098                                                      imod->nApvPairs(),
00099                                                      imod->fedCh(ipair).fedId_, 
00100                                                      imod->fedCh(ipair).fedCh_, 
00101                                                      imod->length(),
00102                                                      imod->dcu(), 
00103                                                      imod->pll(), 
00104                                                      imod->mux(), 
00105                                                      imod->lld() ) );
00106               uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
00107               uint16_t fed_slot = imod->fedCh(ipair).fedSlot_;
00108               conns.back().fedCrate( fed_crate );
00109               conns.back().fedSlot( fed_slot );
00110             }
00111           }
00112         }
00113       }
00114     }
00115   }
00116 }
00117 
00118 // -----------------------------------------------------------------------------
00119 //
00120 const SiStripModule& SiStripFecCabling::module( const FedChannelConnection& conn ) const {
00121 
00122   std::stringstream ss;
00123   std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin();
00124   while ( icrate != crates().end() && icrate->fecCrate() != conn.fecCrate() ) { icrate++; }
00125   if ( icrate != crates().end() ) { 
00126     std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin();
00127     while ( ifec != icrate->fecs().end() && ifec->fecSlot() != conn.fecSlot() ) { ifec++; }
00128     if ( ifec != icrate->fecs().end() ) { 
00129       std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin();
00130       while ( iring != ifec->rings().end() && iring->fecRing() != conn.fecRing() ) { iring++; }
00131       if ( iring != ifec->rings().end() ) { 
00132         std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin();
00133         while ( iccu != iring->ccus().end() && iccu->ccuAddr() != conn.ccuAddr() ) { iccu++; }
00134         if ( iccu != iring->ccus().end() ) { 
00135           std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin();
00136           while ( imod != iccu->modules().end() && imod->ccuChan() != conn.ccuChan() ) { imod++; }
00137           if ( imod != iccu->modules().end() ) { 
00138             return *imod;
00139           } else { 
00140             ss << "[SiStripFecCabling::" << __func__ << "]"
00141                << " CCU channel " << conn.ccuChan() 
00142                << " not found!"; }
00143         } else { 
00144           ss << "[SiStripFecCabling::" << __func__ << "]"
00145              << " CCU address " << conn.ccuAddr() 
00146              << " not found!"; }
00147       } else { 
00148         ss << "[SiStripFecCabling::" << __func__ << "]"
00149            << " FEC ring " << conn.fecRing() 
00150            << " not found!"; }
00151     } else { 
00152       ss << "[SiStripFecCabling::" << __func__ << "]"
00153          << " FEC slot " << conn.fecSlot() 
00154          << " not found!"; }
00155   } else { 
00156     ss << "[SiStripFecCabling::" << __func__ << "]"
00157        << " FEC crate " << conn.fecCrate() 
00158        << " not found!"; 
00159   }
00160 
00161   if ( !ss.str().empty() ) { edm::LogWarning(mlCabling_) << ss.str(); }
00162   static FedChannelConnection temp;
00163   static const SiStripModule module(temp);
00164   return module;
00165 }
00166 
00167 // -----------------------------------------------------------------------------
00168 //
00169 const SiStripModule& SiStripFecCabling::module( const uint32_t& dcu_id ) const {
00170   for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
00171     for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
00172       for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
00173         for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
00174           for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
00175             if ( (*imod).dcuId() == dcu_id ) { return *imod; }
00176           }
00177         }
00178       }
00179     }
00180   }
00181   static FedChannelConnection temp;
00182   static const SiStripModule module(temp);
00183   return module;
00184 }
00185 
00186 // -----------------------------------------------------------------------------
00187 //
00188 NumberOfDevices SiStripFecCabling::countDevices() const {
00189   
00190   NumberOfDevices num_of_devices; // simple container class used for counting
00191 
00192   std::vector<uint16_t> fed_crates; 
00193   std::vector<uint16_t> fed_slots; 
00194   std::vector<uint16_t> fed_ids; 
00195   for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
00196     for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
00197       for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
00198         for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
00199           for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
00200 
00201             // APVs
00202             if ( imod->activeApv(32) ) { num_of_devices.nApvs_++; }
00203             if ( imod->activeApv(33) ) { num_of_devices.nApvs_++; }
00204             if ( imod->activeApv(34) ) { num_of_devices.nApvs_++; }
00205             if ( imod->activeApv(35) ) { num_of_devices.nApvs_++; }
00206             if ( imod->activeApv(36) ) { num_of_devices.nApvs_++; }
00207             if ( imod->activeApv(37) ) { num_of_devices.nApvs_++; }
00208             if ( imod->dcuId() ) { num_of_devices.nDcuIds_++; }
00209             if ( imod->detId() ) { num_of_devices.nDetIds_++; }
00210 
00211             // APV pairs
00212             num_of_devices.nApvPairs_ += imod->nApvPairs();
00213             if      ( imod->nApvPairs() == 0 ) { num_of_devices.nApvPairs0_++; }
00214             else if ( imod->nApvPairs() == 1 ) { num_of_devices.nApvPairs1_++; }
00215             else if ( imod->nApvPairs() == 2 ) { num_of_devices.nApvPairs2_++; }
00216             else if ( imod->nApvPairs() == 3 ) { num_of_devices.nApvPairs3_++; }
00217             else { num_of_devices.nApvPairsX_++; }
00218 
00219             // FED crates, slots, ids, channels
00220             for ( uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++ ) {
00221 
00222               uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
00223               uint16_t fed_slot  = imod->fedCh(ipair).fedSlot_;
00224               uint16_t fed_id    = imod->fedCh(ipair).fedId_;
00225 
00226               if ( fed_id ) { 
00227 
00228                 num_of_devices.nFedChans_++;
00229                 
00230                 std::vector<uint16_t>::iterator icrate = find( fed_crates.begin(), fed_crates.end(), fed_crate );
00231                 if ( icrate == fed_crates.end() ) { 
00232                   num_of_devices.nFedCrates_++; 
00233                   fed_crates.push_back(fed_crate); 
00234                 }
00235                 
00236                 std::vector<uint16_t>::iterator islot = find( fed_slots.begin(), fed_slots.end(), fed_slot );
00237                 if ( islot == fed_slots.end() ) { 
00238                   num_of_devices.nFedSlots_++; 
00239                   fed_slots.push_back(fed_slot); 
00240                 }
00241 
00242                 std::vector<uint16_t>::iterator ifed = find( fed_ids.begin(), fed_ids.end(), fed_id );
00243                 if ( ifed == fed_ids.end() ) { 
00244                   num_of_devices.nFedIds_++; 
00245                   fed_ids.push_back(fed_id); 
00246                 }
00247 
00248               }
00249 
00250             }
00251 
00252             // FE devices
00253             if ( imod->dcu() ) { num_of_devices.nDcus_++; }
00254             if ( imod->mux() ) { num_of_devices.nMuxes_++; }
00255             if ( imod->pll() ) { num_of_devices.nPlls_++; }
00256             if ( imod->lld() ) { num_of_devices.nLlds_++; }
00257 
00258             // FE modules
00259             num_of_devices.nCcuChans_++;
00260           } 
00261           num_of_devices.nCcuAddrs_++;
00262         }
00263         num_of_devices.nFecRings_++;
00264       }
00265       num_of_devices.nFecSlots_++;
00266     }
00267     num_of_devices.nFecCrates_++;
00268   }
00269   
00270   return num_of_devices;
00271   
00272 }
00273 
00274 // -----------------------------------------------------------------------------
00275 //
00276 void SiStripFecCabling::print( std::stringstream& ss ) const {
00277   uint32_t valid = 0;
00278   uint32_t total = 0;
00279   ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
00280   ss << "Printing cabling for " << crates().size() << " crates" << std::endl;
00281   for ( std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); icrate++ ) {
00282     ss << "Printing cabling for " << icrate->fecs().size() << " FECs for crate " << icrate->fecCrate() << std::endl;
00283     for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
00284       ss << "Printing cabling for " << ifec->rings().size() << " rings for FEC " << ifec->fecSlot() << std::endl;
00285       for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
00286         ss << "Printing cabling for " << iring->ccus().size() << " CCUs for ring " << iring->fecRing() << std::endl;
00287         for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
00288           ss << "Printing cabling for " << iccu->modules().size() << " modules for CCU " << iccu->ccuAddr() << std::endl;
00289           for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
00290 
00291             SiStripModule::FedCabling conns = imod->fedChannels();
00292             SiStripModule::FedCabling::const_iterator ii = conns.begin();
00293             SiStripModule::FedCabling::const_iterator jj = conns.end();
00294             for ( ; ii != jj; ++ii ) {
00295               if ( ii->second.fedId_ != sistrip::invalid_ &&
00296                    ii->second.fedCh_ != sistrip::invalid_ ) { valid++; }
00297               total++;
00298             }
00299             ss << *imod << std::endl;
00300           } 
00301         }
00302       }
00303     }
00304   }
00305   ss << "Number of connected:   " << valid << std::endl
00306      << "Number of connections: " << total << std::endl;
00307 }
00308 
00309 // -----------------------------------------------------------------------------
00310 //
00311 void SiStripFecCabling::terse( std::stringstream& ss ) const {
00312   ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
00313   for ( std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); icrate++ ) {
00314     for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
00315       for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
00316         for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
00317           for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
00318             imod->terse(ss); 
00319             ss << std::endl;
00320           } 
00321         }
00322       }
00323     }
00324   }
00325 }
00326 
00327 // -----------------------------------------------------------------------------
00328 //
00329 std::ostream& operator<< ( std::ostream& os, const SiStripFecCabling& cabling ) {
00330   std::stringstream ss;
00331   cabling.print(ss);
00332   os << ss.str();
00333   return os;
00334 }
/data/refman/pasoursint/CMSSW_4_4_5_patch3/src/CalibFormats/SiStripObjects/src/SiStripFecCabling.cc
