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#include <SiStripFecCabling.h>
Public Member Functions | |
| void | addDevices (const FedChannelConnection &conn) |
| void | buildFecCabling (const SiStripFedCabling &) |
| void | connections (std::vector< FedChannelConnection > &) const |
| NumberOfDevices | countDevices () const |
| const std::vector < SiStripFecCrate > & | crates () const |
| void | dcuId (const FedChannelConnection &conn) |
| void | detId (const FedChannelConnection &conn) |
| const std::vector< SiStripFec > & | fecs () const |
| const SiStripModule & | module (const FedChannelConnection &conn) const |
| const SiStripModule & | module (const uint32_t &dcu_id) const |
| void | nApvPairs (const FedChannelConnection &conn) |
| void | print (std::stringstream &) const |
| SiStripFecCabling (const SiStripFedCabling &) | |
| SiStripFecCabling () | |
| void | terse (std::stringstream &) const |
| ~SiStripFecCabling () | |
Private Attributes | |
| std::vector< SiStripFecCrate > | crates_ |
Definition at line 25 of file SiStripFecCabling.h.
| SiStripFecCabling::SiStripFecCabling | ( | const SiStripFedCabling & | fed_cabling | ) |
Definition at line 14 of file SiStripFecCabling.cc.
References buildFecCabling(), crates_, LogTrace, and sistrip::mlCabling_.
: crates_() { LogTrace(mlCabling_) << "[SiStripFecCabling::" << __func__ << "]" << " Constructing object..."; crates_.reserve(4); buildFecCabling( fed_cabling ); }
| SiStripFecCabling::SiStripFecCabling | ( | ) | [inline] |
Definition at line 34 of file SiStripFecCabling.h.
{;}
| SiStripFecCabling::~SiStripFecCabling | ( | ) | [inline] |
Definition at line 36 of file SiStripFecCabling.h.
{;} //@@ needs implementation!!
| void SiStripFecCabling::addDevices | ( | const FedChannelConnection & | conn | ) |
Definition at line 66 of file SiStripFecCabling.cc.
References SiStripFecCrate::addDevices(), crates(), crates_, end, and FedChannelConnection::fecCrate().
Referenced by buildFecCabling(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDetIds(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices(), SiStripFedCablingBuilderFromDb::buildFecCablingFromFedConnections(), and SiStripFedCablingFakeESSource::make().
{
std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin();
while ( icrate != crates().end() && (*icrate).fecCrate() != conn.fecCrate() ) { icrate++; }
if ( icrate == crates().end() ) {
crates_.push_back( SiStripFecCrate( conn ) );
} else {
const_cast<SiStripFecCrate&>(*icrate).addDevices( conn );
}
}
| void SiStripFecCabling::buildFecCabling | ( | const SiStripFedCabling & | fed_cabling | ) |
Definition at line 26 of file SiStripFecCabling.cc.
References addDevices(), begin, SiStripFedCabling::connections(), crates(), SiStripFedCabling::feds(), sistrip::invalid_, LogTrace, and sistrip::mlCabling_.
Referenced by SiStripFedCablingBuilderFromDb::getFecCabling(), and SiStripFecCabling().
{
LogTrace(mlCabling_)
<< "[SiStripFecCabling::" << __func__ << "]"
<< " Building FEC cabling...";
// Retrieve and iterate through FED ids
const std::vector<uint16_t>& feds = fed_cabling.feds();
std::vector<uint16_t>::const_iterator ifed;
for ( ifed = feds.begin(); ifed != feds.end(); ifed++ ) {
// Retrieve and iterate through FED channel connections
const std::vector<FedChannelConnection>& conns = fed_cabling.connections( *ifed );
std::vector<FedChannelConnection>::const_iterator iconn;
for ( iconn = conns.begin(); iconn != conns.end(); iconn++ ) {
// Check that FED id is not invalid and add devices
if ( iconn->fedId() != sistrip::invalid_ ) { addDevices( *iconn ); }
}
}
// Consistency checks
for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
//@@ need consistency checks here!
}
}
}
}
}
LogTrace(mlCabling_)
<< "[SiStripFecCabling::" << __func__ << "]"
<< " Finished building FEC cabling";
}
| void SiStripFecCabling::connections | ( | std::vector< FedChannelConnection > & | conns | ) | const |
Definition at line 78 of file SiStripFecCabling.cc.
References begin, crates(), first, LogTrace, sistrip::mlCabling_, and edm::second().
Referenced by SiStripFedCablingBuilderFromDb::getFedCabling(), and SiStripFedCablingFakeESSource::make().
{
LogTrace(mlCabling_)
<< "[SiStripFecCabling::" << __func__ << "]"
<< " Building vector of FedChannelConnection objects...";
conns.clear();
for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
for ( uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++ ) {
conns.push_back( FedChannelConnection( icrate->fecCrate(),
ifec->fecSlot(),
iring->fecRing(),
iccu->ccuAddr(),
imod->ccuChan(),
imod->activeApvPair( imod->lldChannel(ipair) ).first,
imod->activeApvPair( imod->lldChannel(ipair) ).second,
imod->dcuId(),
imod->detId(),
imod->nApvPairs(),
imod->fedCh(ipair).fedId_,
imod->fedCh(ipair).fedCh_,
imod->length(),
imod->dcu(),
imod->pll(),
imod->mux(),
imod->lld() ) );
uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
uint16_t fed_slot = imod->fedCh(ipair).fedSlot_;
conns.back().fedCrate( fed_crate );
conns.back().fedSlot( fed_slot );
}
}
}
}
}
}
}
| NumberOfDevices SiStripFecCabling::countDevices | ( | ) | const |
Definition at line 188 of file SiStripFecCabling.cc.
References begin, crates(), spr::find(), NumberOfDevices::nApvPairs0_, NumberOfDevices::nApvPairs1_, NumberOfDevices::nApvPairs2_, NumberOfDevices::nApvPairs3_, NumberOfDevices::nApvPairs_, NumberOfDevices::nApvPairsX_, NumberOfDevices::nApvs_, NumberOfDevices::nCcuAddrs_, NumberOfDevices::nCcuChans_, NumberOfDevices::nDcuIds_, NumberOfDevices::nDcus_, NumberOfDevices::nDetIds_, NumberOfDevices::nFecCrates_, NumberOfDevices::nFecRings_, NumberOfDevices::nFecSlots_, NumberOfDevices::nFedChans_, NumberOfDevices::nFedCrates_, NumberOfDevices::nFedIds_, NumberOfDevices::nFedSlots_, NumberOfDevices::nLlds_, NumberOfDevices::nMuxes_, and NumberOfDevices::nPlls_.
Referenced by SiStripFedCablingBuilderFromDb::buildFecCabling(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices(), and SiStripFedCablingFakeESSource::make().
{
NumberOfDevices num_of_devices; // simple container class used for counting
std::vector<uint16_t> fed_crates;
std::vector<uint16_t> fed_slots;
std::vector<uint16_t> fed_ids;
for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
// APVs
if ( imod->activeApv(32) ) { num_of_devices.nApvs_++; }
if ( imod->activeApv(33) ) { num_of_devices.nApvs_++; }
if ( imod->activeApv(34) ) { num_of_devices.nApvs_++; }
if ( imod->activeApv(35) ) { num_of_devices.nApvs_++; }
if ( imod->activeApv(36) ) { num_of_devices.nApvs_++; }
if ( imod->activeApv(37) ) { num_of_devices.nApvs_++; }
if ( imod->dcuId() ) { num_of_devices.nDcuIds_++; }
if ( imod->detId() ) { num_of_devices.nDetIds_++; }
// APV pairs
num_of_devices.nApvPairs_ += imod->nApvPairs();
if ( imod->nApvPairs() == 0 ) { num_of_devices.nApvPairs0_++; }
else if ( imod->nApvPairs() == 1 ) { num_of_devices.nApvPairs1_++; }
else if ( imod->nApvPairs() == 2 ) { num_of_devices.nApvPairs2_++; }
else if ( imod->nApvPairs() == 3 ) { num_of_devices.nApvPairs3_++; }
else { num_of_devices.nApvPairsX_++; }
// FED crates, slots, ids, channels
for ( uint16_t ipair = 0; ipair < imod->nApvPairs(); ipair++ ) {
uint16_t fed_crate = imod->fedCh(ipair).fedCrate_;
uint16_t fed_slot = imod->fedCh(ipair).fedSlot_;
uint16_t fed_id = imod->fedCh(ipair).fedId_;
if ( fed_id ) {
num_of_devices.nFedChans_++;
std::vector<uint16_t>::iterator icrate = find( fed_crates.begin(), fed_crates.end(), fed_crate );
if ( icrate == fed_crates.end() ) {
num_of_devices.nFedCrates_++;
fed_crates.push_back(fed_crate);
}
std::vector<uint16_t>::iterator islot = find( fed_slots.begin(), fed_slots.end(), fed_slot );
if ( islot == fed_slots.end() ) {
num_of_devices.nFedSlots_++;
fed_slots.push_back(fed_slot);
}
std::vector<uint16_t>::iterator ifed = find( fed_ids.begin(), fed_ids.end(), fed_id );
if ( ifed == fed_ids.end() ) {
num_of_devices.nFedIds_++;
fed_ids.push_back(fed_id);
}
}
}
// FE devices
if ( imod->dcu() ) { num_of_devices.nDcus_++; }
if ( imod->mux() ) { num_of_devices.nMuxes_++; }
if ( imod->pll() ) { num_of_devices.nPlls_++; }
if ( imod->lld() ) { num_of_devices.nLlds_++; }
// FE modules
num_of_devices.nCcuChans_++;
}
num_of_devices.nCcuAddrs_++;
}
num_of_devices.nFecRings_++;
}
num_of_devices.nFecSlots_++;
}
num_of_devices.nFecCrates_++;
}
return num_of_devices;
}
| const std::vector< SiStripFecCrate > & SiStripFecCabling::crates | ( | ) | const [inline] |
Definition at line 79 of file SiStripFecCabling.h.
References crates_.
Referenced by addDevices(), SiStripFedCablingBuilderFromDb::assignDcuAndDetIds(), SiStripCommissioningSource::beginRun(), buildFecCabling(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDetIds(), SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices(), connections(), countDevices(), SiStripCommissioningSource::createCablingTasks(), SiStripFedCablingFakeESSource::make(), module(), print(), terse(), and TrackerMap::TrackerMap().
{ return crates_; }
| void SiStripFecCabling::dcuId | ( | const FedChannelConnection & | conn | ) | [inline] |
Definition at line 88 of file SiStripFecCabling.h.
References FedChannelConnection::dcuId(), and module().
Referenced by SiStripFedCablingBuilderFromDb::buildFecCablingFromDevices().
{
const_cast<SiStripModule&>(module(conn)).dcuId(conn.dcuId());
}
| void SiStripFecCabling::detId | ( | const FedChannelConnection & | conn | ) | [inline] |
Definition at line 92 of file SiStripFecCabling.h.
References FedChannelConnection::detId(), and module().
{
const_cast<SiStripModule&>(module(conn)).detId(conn.detId());
}
| const std::vector< SiStripFec > & SiStripFecCabling::fecs | ( | ) | const [inline] |
Definition at line 82 of file SiStripFecCabling.h.
References crates_.
| const SiStripModule & SiStripFecCabling::module | ( | const FedChannelConnection & | conn | ) | const |
Definition at line 120 of file SiStripFecCabling.cc.
References FedChannelConnection::ccuAddr(), FedChannelConnection::ccuChan(), crates(), end, FedChannelConnection::fecCrate(), FedChannelConnection::fecRing(), FedChannelConnection::fecSlot(), sistrip::mlCabling_, and cond::rpcobtemp::temp.
Referenced by dcuId(), detId(), SiStripCommissioningSource::fillCablingHistos(), module(), and nApvPairs().
{
std::stringstream ss;
std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin();
while ( icrate != crates().end() && icrate->fecCrate() != conn.fecCrate() ) { icrate++; }
if ( icrate != crates().end() ) {
std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin();
while ( ifec != icrate->fecs().end() && ifec->fecSlot() != conn.fecSlot() ) { ifec++; }
if ( ifec != icrate->fecs().end() ) {
std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin();
while ( iring != ifec->rings().end() && iring->fecRing() != conn.fecRing() ) { iring++; }
if ( iring != ifec->rings().end() ) {
std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin();
while ( iccu != iring->ccus().end() && iccu->ccuAddr() != conn.ccuAddr() ) { iccu++; }
if ( iccu != iring->ccus().end() ) {
std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin();
while ( imod != iccu->modules().end() && imod->ccuChan() != conn.ccuChan() ) { imod++; }
if ( imod != iccu->modules().end() ) {
return *imod;
} else {
ss << "[SiStripFecCabling::" << __func__ << "]"
<< " CCU channel " << conn.ccuChan()
<< " not found!"; }
} else {
ss << "[SiStripFecCabling::" << __func__ << "]"
<< " CCU address " << conn.ccuAddr()
<< " not found!"; }
} else {
ss << "[SiStripFecCabling::" << __func__ << "]"
<< " FEC ring " << conn.fecRing()
<< " not found!"; }
} else {
ss << "[SiStripFecCabling::" << __func__ << "]"
<< " FEC slot " << conn.fecSlot()
<< " not found!"; }
} else {
ss << "[SiStripFecCabling::" << __func__ << "]"
<< " FEC crate " << conn.fecCrate()
<< " not found!";
}
if ( !ss.str().empty() ) { edm::LogWarning(mlCabling_) << ss.str(); }
static FedChannelConnection temp;
static const SiStripModule module(temp);
return module;
}
| const SiStripModule & SiStripFecCabling::module | ( | const uint32_t & | dcu_id | ) | const |
Definition at line 169 of file SiStripFecCabling.cc.
References begin, crates(), module(), and cond::rpcobtemp::temp.
{
for ( std::vector<SiStripFecCrate>::const_iterator icrate = this->crates().begin(); icrate != this->crates().end(); icrate++ ) {
for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
if ( (*imod).dcuId() == dcu_id ) { return *imod; }
}
}
}
}
}
static FedChannelConnection temp;
static const SiStripModule module(temp);
return module;
}
| void SiStripFecCabling::nApvPairs | ( | const FedChannelConnection & | conn | ) | [inline] |
Definition at line 96 of file SiStripFecCabling.h.
References module(), and FedChannelConnection::nApvPairs().
{
const_cast<SiStripModule&>(module(conn)).nApvPairs(conn.nApvPairs());
}
| void SiStripFecCabling::print | ( | std::stringstream & | ss | ) | const |
Definition at line 276 of file SiStripFecCabling.cc.
References begin, crates(), sistrip::invalid_, pileupDistInMC::total, and TrackValidation_HighPurity_cff::valid.
Referenced by operator<<().
{
uint32_t valid = 0;
uint32_t total = 0;
ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
ss << "Printing cabling for " << crates().size() << " crates" << std::endl;
for ( std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); icrate++ ) {
ss << "Printing cabling for " << icrate->fecs().size() << " FECs for crate " << icrate->fecCrate() << std::endl;
for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
ss << "Printing cabling for " << ifec->rings().size() << " rings for FEC " << ifec->fecSlot() << std::endl;
for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
ss << "Printing cabling for " << iring->ccus().size() << " CCUs for ring " << iring->fecRing() << std::endl;
for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
ss << "Printing cabling for " << iccu->modules().size() << " modules for CCU " << iccu->ccuAddr() << std::endl;
for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
SiStripModule::FedCabling conns = imod->fedChannels();
SiStripModule::FedCabling::const_iterator ii = conns.begin();
SiStripModule::FedCabling::const_iterator jj = conns.end();
for ( ; ii != jj; ++ii ) {
if ( ii->second.fedId_ != sistrip::invalid_ &&
ii->second.fedCh_ != sistrip::invalid_ ) { valid++; }
total++;
}
ss << *imod << std::endl;
}
}
}
}
}
ss << "Number of connected: " << valid << std::endl
<< "Number of connections: " << total << std::endl;
}
| void SiStripFecCabling::terse | ( | std::stringstream & | ss | ) | const |
Definition at line 311 of file SiStripFecCabling.cc.
References begin, and crates().
{
ss << "[SiStripFecCabling::" << __func__ << "] Printing FEC cabling:" << std::endl;
for ( std::vector<SiStripFecCrate>::const_iterator icrate = crates().begin(); icrate != crates().end(); icrate++ ) {
for ( std::vector<SiStripFec>::const_iterator ifec = icrate->fecs().begin(); ifec != icrate->fecs().end(); ifec++ ) {
for ( std::vector<SiStripRing>::const_iterator iring = ifec->rings().begin(); iring != ifec->rings().end(); iring++ ) {
for ( std::vector<SiStripCcu>::const_iterator iccu = iring->ccus().begin(); iccu != iring->ccus().end(); iccu++ ) {
for ( std::vector<SiStripModule>::const_iterator imod = iccu->modules().begin(); imod != iccu->modules().end(); imod++ ) {
imod->terse(ss);
ss << std::endl;
}
}
}
}
}
}
std::vector<SiStripFecCrate> SiStripFecCabling::crates_ [private] |
Definition at line 73 of file SiStripFecCabling.h.
Referenced by addDevices(), crates(), fecs(), and SiStripFecCabling().
1.7.3