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/data/refman/pasoursint/CMSSW_4_1_8_patch13/src/DQM/SiStripCommissioningClients/src/FedCablingHistograms.cc

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00001 #include "DQM/SiStripCommissioningClients/interface/FedCablingHistograms.h"
00002 #include "CondFormats/SiStripObjects/interface/FedCablingAnalysis.h"
00003 #include "DQM/SiStripCommissioningAnalysis/interface/FedCablingAlgorithm.h"
00004 #include "DQM/SiStripCommissioningSummary/interface/SummaryGenerator.h"
00005 #include "DataFormats/SiStripCommon/interface/SiStripConstants.h"
00006 #include "DataFormats/SiStripCommon/interface/SiStripEnumsAndStrings.h"
00007 #include "DQM/SiStripCommon/interface/ExtractTObject.h"
00008 #include "FWCore/MessageLogger/interface/MessageLogger.h"
00009 #include <iostream>
00010 #include <sstream>
00011 #include <iomanip>
00012 #include "TProfile.h"
00013 
00014 using namespace std;
00015 using namespace sistrip;
00016 
00017 // -----------------------------------------------------------------------------
00019 FedCablingHistograms::FedCablingHistograms( const edm::ParameterSet& pset,
00020                                             DQMStore* bei ) 
00021   : CommissioningHistograms( pset.getParameter<edm::ParameterSet>("FedCablingParameters"),
00022                              bei,
00023                              sistrip::FED_CABLING ),
00024     factory_( new Factory )
00025 {
00026   LogTrace(mlDqmClient_) 
00027     << "[FedCablingHistograms::" << __func__ << "]"
00028     << " Constructing object...";
00029 }
00030 
00031 // -----------------------------------------------------------------------------
00033 FedCablingHistograms::~FedCablingHistograms() {
00034   LogTrace(mlDqmClient_) 
00035     << "[FedCablingHistograms::" << __func__ << "]"
00036     << " Destructing object...";
00037 }
00038 
00039 // -----------------------------------------------------------------------------         
00041 void FedCablingHistograms::histoAnalysis( bool debug ) {
00042   LogTrace(mlDqmClient_)
00043     << "[FedCablingHistograms::" << __func__ << "]";
00044 
00045   uint16_t valid = 0;
00046   HistosMap::const_iterator iter;
00047   Analyses::iterator ianal;
00048   
00049   // Clear map holding analysis objects
00050   for ( ianal = data_.begin(); ianal != data_.end(); ianal++ ) { 
00051     if ( ianal->second ) { delete ianal->second; }
00052   } 
00053   data_.clear();
00054   
00055   // Iterate through map containing histograms
00056   for ( iter = histos().begin(); 
00057         iter != histos().end(); iter++ ) {
00058     
00059     // Check vector of histos is not empty
00060     if ( iter->second.empty() ) {
00061       edm::LogWarning(mlDqmClient_)
00062         << "[FedCablingHistograms::" << __func__ << "]"
00063         << " Zero histograms found!";
00064       continue;
00065     }
00066     
00067     // Retrieve pointers to histos
00068     std::vector<TH1*> profs;
00069     Histos::const_iterator ihis = iter->second.begin(); 
00070     for ( ; ihis != iter->second.end(); ihis++ ) {
00071       TProfile* prof = ExtractTObject<TProfile>().extract( (*ihis)->me_ );
00072       if ( prof ) { profs.push_back(prof); }
00073     } 
00074     
00075     // Perform histo analysis
00076     FedCablingAnalysis* anal = new FedCablingAnalysis( iter->first );
00077     FedCablingAlgorithm algo( this->pset(), anal );
00078     algo.analysis( profs );
00079     data_[iter->first] = anal; 
00080     if ( anal->isValid() ) { valid++; }
00081     
00082   }
00083   
00084   if ( !histos().empty() ) {
00085     edm::LogVerbatim(mlDqmClient_) 
00086       << "[FedCablingHistograms::" << __func__ << "]"
00087       << " Analyzed histograms for " << histos().size() 
00088       << " FED channels, of which " << valid 
00089       << " (" << 100 * valid / histos().size()
00090       << "%) are valid.";
00091   } else {
00092     edm::LogWarning(mlDqmClient_) 
00093       << "[FedCablingHistograms::" << __func__ << "]"
00094       << " No histograms to analyze!";
00095   }
00096   
00097 }
00098 
00099 // -----------------------------------------------------------------------------         
00101 void FedCablingHistograms::printAnalyses() {
00102   Analyses::iterator ianal = data_.begin();
00103   Analyses::iterator janal = data_.end();
00104   for ( ; ianal != janal; ++ianal ) { 
00105     if ( ianal->second ) { 
00106       std::stringstream ss;
00107       ianal->second->print( ss ); 
00108       if ( ianal->second->isValid() ) { LogTrace(mlDqmClient_) << ss.str(); 
00109       } else { edm::LogWarning(mlDqmClient_) << ss.str(); }
00110     }
00111   }
00112 }
00113 
00114 // -----------------------------------------------------------------------------
00116 void FedCablingHistograms::createSummaryHisto( const sistrip::Monitorable& histo, 
00117                                                const sistrip::Presentation& type, 
00118                                                const std::string& dir,
00119                                                const sistrip::Granularity& gran ) {
00120   LogTrace(mlDqmClient_)
00121     << "[FedCablingHistograms::" << __func__ << "]";
00122   
00123   // Check view 
00124   sistrip::View view = SiStripEnumsAndStrings::view(dir);
00125   if ( view == sistrip::UNKNOWN_VIEW ) { return; }
00126   
00127   // Analyze histograms if not done already
00128   if ( data_.empty() ) { histoAnalysis( false ); }
00129   
00130   // Extract data to be histogrammed
00131   uint32_t xbins = factory_->init( histo, type, view, dir, gran, data_ );
00132   
00133   // Create summary histogram (if it doesn't already exist)
00134   TH1* summary = histogram( histo, type, view, dir, xbins );
00135 
00136   // Fill histogram with data
00137   factory_->fill( *summary );
00138   
00139 }
00140 
00141 
00142 
00143