#include <algorithm>
#include <cuda_runtime.h>
#include "CUDADataFormats/SiPixelDigi/interface/SiPixelDigisCUDA.h"
#include "CUDADataFormats/SiPixelDigi/interface/SiPixelDigiErrorsCUDA.h"
#include "CUDADataFormats/SiPixelCluster/interface/SiPixelClustersCUDA.h"
#include "FWCore/Utilities/interface/typedefs.h"
#include "HeterogeneousCore/CUDAUtilities/interface/SimpleVector.h"
#include "HeterogeneousCore/CUDAUtilities/interface/host_unique_ptr.h"
#include "HeterogeneousCore/CUDAUtilities/interface/host_noncached_unique_ptr.h"
#include "DataFormats/SiPixelRawData/interface/SiPixelErrorCompact.h"
#include "DataFormats/SiPixelRawData/interface/SiPixelFormatterErrors.h"
#include "SiPixelClusterThresholds.h"
Go to the source code of this file.
Namespaces | |
pixelgpudetails | |
Functions | |
__host__ __device__ uint32_t | pixelgpudetails::pack (uint32_t row, uint32_t col, uint32_t adc) |
__host__ constexpr __device__ Packing | pixelgpudetails::packing () |
constexpr uint32_t | pixelgpudetails::pixelToChannel (int row, int col) |
Variables | |
const uint32_t | pixelgpudetails::ADC_bits = 8 |
const uint32_t | pixelgpudetails::ADC_mask = ~(~uint32_t(0) << ADC_bits) |
const uint32_t | pixelgpudetails::ADC_shift = 0 |
const uint32_t | pixelgpudetails::bladeMask = 0x3F |
const uint32_t | pixelgpudetails::bladeStartBit = 12 |
const uint32_t | pixelgpudetails::COL_bits_l1 = 6 |
const uint32_t | pixelgpudetails::COL_mask = ~(~uint32_t(0) << COL_bits_l1) |
const uint32_t | pixelgpudetails::COL_shift = ROW_shift + ROW_bits_l1 |
const uint32_t | pixelgpudetails::DCOL_bits = 5 |
const uint32_t | pixelgpudetails::DCOL_mask = ~(~uint32_t(0) << DCOL_bits) |
const uint32_t | pixelgpudetails::DCOL_shift = PXID_shift + PXID_bits |
const uint32_t | pixelgpudetails::diskMask = 0xF |
const uint32_t | pixelgpudetails::diskStartBit = 18 |
const uint32_t | pixelgpudetails::ERROR_mask = ~(~uint32_t(0) << ROC_bits_l1) |
const uint32_t | pixelgpudetails::ladderMask = 0xFF |
const uint32_t | pixelgpudetails::ladderStartBit = 12 |
const uint32_t | pixelgpudetails::layerMask = 0xF |
const uint32_t | pixelgpudetails::layerStartBit = 20 |
const uint32_t | pixelgpudetails::LINK_bits = 6 |
const uint32_t | pixelgpudetails::LINK_bits_l1 = 6 |
const uint32_t | pixelgpudetails::LINK_mask = ~(~uint32_t(0) << LINK_bits_l1) |
const uint32_t | pixelgpudetails::LINK_shift = ROC_shift + ROC_bits_l1 |
const uint32_t | pixelgpudetails::MAX_WORD = 2000 |
const uint32_t | pixelgpudetails::maxROCIndex = 8 |
const uint32_t | pixelgpudetails::moduleMask = 0x3FF |
const uint32_t | pixelgpudetails::moduleStartBit = 2 |
const uint32_t | pixelgpudetails::numColsInRoc = 52 |
const uint32_t | pixelgpudetails::numRowsInRoc = 80 |
const uint32_t | pixelgpudetails::OMIT_ERR_bits = 1 |
const uint32_t | pixelgpudetails::OMIT_ERR_mask = ~(~uint32_t(0) << OMIT_ERR_bits) |
const uint32_t | pixelgpudetails::OMIT_ERR_shift = 20 |
const uint32_t | pixelgpudetails::panelMask = 0x3 |
const uint32_t | pixelgpudetails::panelStartBit = 10 |
const uint32_t | pixelgpudetails::PXID_bits = 8 |
const uint32_t | pixelgpudetails::PXID_mask = ~(~uint32_t(0) << PXID_bits) |
const uint32_t | pixelgpudetails::PXID_shift = ADC_shift + ADC_bits |
const uint32_t | pixelgpudetails::ROC_bits = 5 |
const uint32_t | pixelgpudetails::ROC_bits_l1 = 5 |
const uint32_t | pixelgpudetails::ROC_mask = ~(~uint32_t(0) << ROC_bits_l1) |
const uint32_t | pixelgpudetails::ROC_shift = DCOL_shift + DCOL_bits |
const uint32_t | pixelgpudetails::ROW_bits_l1 = 7 |
const uint32_t | pixelgpudetails::ROW_mask = ~(~uint32_t(0) << ROW_bits_l1) |
const uint32_t | pixelgpudetails::ROW_shift = ADC_shift + ADC_bits |